OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [m32r/] [constraints.md] - Blame information for rev 473

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
;; Constraint definitions for Renesas M32R cpu for GNU C compiler
2
;; Copyright (C) 2007 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
;;
6
;; GCC is free software; you can redistribute it and/or modify it
7
;; under the terms of the GNU General Public License as published
8
;; by the Free Software Foundation; either version 3, or (at your
9
;; option) any later version.
10
 
11
;; GCC is distributed in the hope that it will be useful, but WITHOUT
12
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
;; License for more details.
15
;;
16
;; You should have received a copy of the GNU General Public License
17
;; along with GCC; see the file COPYING3.  If not see
18
;; .
19
 
20
 
21
;; The letters I, J, K, L, M, N, O, P in a register constraint string
22
;; can be used to stand for particular ranges of immediate operands.
23
;; The letters Q, R, S, T, U are used to segregate specific types of
24
;; operands, usually memory references, for the target machine.
25
;;
26
;; I is used for 8-bit signed immediates.
27
;; J is used for 16-bit signed immediates.
28
;; K is used for 16-bit unsigned immediates.
29
;; L is used for 16-bit immediates left shifted by 16 (sign ???).
30
;; M is used for 24-bit unsigned immediates.
31
;; N is used for 8-bit signed immediates for compares
32
;;   (values in the range -127 to +128).
33
;; O is used for 5-bit unsigned immediates (shift count).
34
;; P is used for 16-bit signed immediates for compares
35
;;     (values in the range -32767 to +32768).
36
;;
37
;; Q is for symbolic addresses loadable with ld24.
38
;; R is for symbolic addresses when ld24 can't be used.
39
;; S is for stores with pre {inc,dec}rement
40
;; T is for indirect of a pointer.
41
;; U is for loads with post increment.
42
;; W is used for an immediate value of 0.
43
;;
44
;; Register constraints
45
 
46
(define_register_constraint "a" "ACCUM_REGS"
47
  "@internal")
48
 
49
(define_register_constraint "c" "CARRY_REG"
50
  "@internal")
51
 
52
;; Integer constraints
53
(define_constraint "I"
54
  "8-bit signed immediate."
55
  (and (match_code "const_int")
56
       (match_test "ival >= -0x80 && ival <= 0x7f")))
57
 
58
(define_constraint "J"
59
  "16-bit signed immediate."
60
  (and (match_code "const_int")
61
       (match_test "ival >= -0x8000 && ival <= 0x7fff")))
62
 
63
(define_constraint "K"
64
  "16-bit unsigned immediate."
65
  (and (match_code "const_int")
66
       (match_test "(unsigned HOST_WIDE_INT) ival <= 0x0000ffff")))
67
 
68
(define_constraint "L"
69
  "16-bit signed immediate left shifted by 16."
70
  (and (match_code "const_int")
71
       (match_test "(ival & 0xffff) == 0")
72
       (match_test "(ival >> 16) >= -0x8000 && (ival >> 16) <= 0x7fff")))
73
 
74
(define_constraint "M"
75
  "24-bit unsigned immediate."
76
  (and (match_code "const_int")
77
       (match_test "(unsigned HOST_WIDE_INT) ival <= 0x00ffffff")))
78
 
79
(define_constraint "N"
80
  "8-bit signed immediate for compare."
81
  (and (match_code "const_int")
82
       (match_test "ival >= -127 && ival <= 128")))
83
 
84
(define_constraint "O"
85
  "5-bit unsigned immediate."
86
  (and (match_code "const_int")
87
       (match_test "ival >= 0 && ival < 32")))
88
 
89
(define_constraint "P"
90
  "16-bit signed immediate for compare."
91
  (and (match_code "const_int")
92
       (match_test "ival >= -0x7fff && ival <= 0x8000")))
93
 
94
;; Floating-point constraints
95
(define_constraint "G"
96
  "Double constant loadable with 2 ldi insns."
97
  (and (match_code "const_double")
98
       (match_test "easy_di_const (op)")))
99
 
100
(define_constraint "H"
101
  "Double constant loadable with movdf."
102
  (and (match_code "const_double")
103
       (match_test "easy_df_const (op)")))
104
 
105
;; Extra constraints
106
(define_constraint "Q"
107
  "A symbolic address loadable when ld24."
108
  (ior (and (match_test "TARGET_ADDR24")
109
            (match_test "GET_CODE (op) == LABEL_REF"))
110
       (match_test "addr24_operand (op, VOIDmode)")))
111
 
112
(define_constraint "R"
113
  "A symbolic address loadable with ld24 can't be used."
114
  (ior (and (match_test "TARGET_ADDR32")
115
            (match_test "GET_CODE (op) == LABEL_REF"))
116
       (match_test "addr32_operand (op, VOIDmode)")))
117
 
118
(define_constraint "S"
119
  "A store with pre {inc,dec}rement."
120
  (and (match_code "mem")
121
       (match_test "STORE_PREINC_PREDEC_P (GET_MODE (op), XEXP (op, 0))")))
122
 
123
(define_constraint "T"
124
  "An indirect of a pointer."
125
  (and (match_code "mem")
126
       (match_test "memreg_operand (op, GET_MODE (op))")))
127
 
128
(define_constraint "U"
129
  "A load with post increment."
130
  (and (match_code "mem")
131
       (match_test "LOAD_POSTINC_P (GET_MODE (op), XEXP (op, 0))")))
132
 
133
(define_constraint "W"
134
  "zero immediate."
135
  (and (match_code "const_int")
136
       (match_test "ival == 0")))
137
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.