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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [mcore/] [predicates.md] - Blame information for rev 282

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1 282 jeremybenn
;; Predicate definitions for Motorola MCore.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;; Nonzero if OP is a normal arithmetic register.
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(define_predicate "mcore_arith_reg_operand"
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  (match_code "reg,subreg")
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{
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  if (! register_operand (op, mode))
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    return 0;
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  if (GET_CODE (op) == SUBREG)
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    op = SUBREG_REG (op);
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  if (GET_CODE (op) == REG)
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    return REGNO (op) != CC_REG;
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34
  return 1;
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})
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;; Nonzero if OP can be source of a simple move operation.
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(define_predicate "mcore_general_movsrc_operand"
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  (match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
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{
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  /* Any (MEM LABEL_REF) is OK.  That is a pc-relative load.  */
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  if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
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    return 1;
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  return general_operand (op, mode);
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})
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;; Nonzero if OP can be destination of a simple move operation.
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(define_predicate "mcore_general_movdst_operand"
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  (match_code "mem,reg,subreg")
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{
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  if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
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    return 0;
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  return general_operand (op, mode);
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})
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;; Nonzero if OP should be recognized during reload for an ixh/ixw
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;; operand.  See the ixh/ixw patterns.
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(define_predicate "mcore_reload_operand"
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  (match_code "mem,reg,subreg")
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{
66
  if (mcore_arith_reg_operand (op, mode))
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    return 1;
68
 
69
  if (! reload_in_progress)
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    return 0;
71
 
72
  return GET_CODE (op) == MEM;
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})
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;; Nonzero if OP is a valid source operand for an arithmetic insn.
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(define_predicate "mcore_arith_J_operand"
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  (match_code "const_int,reg,subreg")
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{
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  if (register_operand (op, mode))
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    return 1;
82
 
83
  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
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    return 1;
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86
  return 0;
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})
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;; Nonzero if OP is a valid source operand for an arithmetic insn.
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(define_predicate "mcore_arith_K_operand"
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  (match_code "const_int,reg,subreg")
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{
94
  if (register_operand (op, mode))
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    return 1;
96
 
97
  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
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    return 1;
99
 
100
  return 0;
101
})
102
 
103
;; Nonzero if OP is a valid source operand for a shift or rotate insn.
104
 
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(define_predicate "mcore_arith_K_operand_not_0"
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  (match_code "const_int,reg,subreg")
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{
108
  if (register_operand (op, mode))
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    return 1;
110
 
111
  if (   GET_CODE (op) == CONST_INT
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      && CONST_OK_FOR_K (INTVAL (op))
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      && INTVAL (op) != 0)
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    return 1;
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116
  return 0;
117
})
118
 
119
;; TODO: Add a comment here.
120
 
121
(define_predicate "mcore_arith_M_operand"
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  (match_code "const_int,reg,subreg")
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{
124
  if (register_operand (op, mode))
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    return 1;
126
 
127
  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
128
    return 1;
129
 
130
  return 0;
131
})
132
 
133
;; TODO: Add a comment here.
134
 
135
(define_predicate "mcore_arith_K_S_operand"
136
  (match_code "const_int,reg,subreg")
137
{
138
  if (register_operand (op, mode))
139
    return 1;
140
 
141
  if (GET_CODE (op) == CONST_INT)
142
    {
143
      if (CONST_OK_FOR_K (INTVAL (op)) || (mcore_num_zeros (INTVAL (op)) <= 2))
144
        return 1;
145
    }
146
 
147
  return 0;
148
})
149
 
150
;; Nonzero if OP is a valid source operand for a cmov with two consts
151
;; +/- 1.
152
 
153
(define_predicate "mcore_arith_O_operand"
154
  (match_code "const_int,reg,subreg")
155
{
156
  if (register_operand (op, mode))
157
    return 1;
158
 
159
  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
160
    return 1;
161
 
162
  return 0;
163
})
164
 
165
;; Nonzero if OP is a valid source operand for loading.
166
 
167
(define_predicate "mcore_arith_imm_operand"
168
  (match_code "const_int,reg,subreg")
169
{
170
  if (register_operand (op, mode))
171
    return 1;
172
 
173
  if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
174
    return 1;
175
 
176
  return 0;
177
})
178
 
179
;; TODO: Add a comment here.
180
 
181
(define_predicate "mcore_arith_any_imm_operand"
182
  (match_code "const_int,reg,subreg")
183
{
184
  if (register_operand (op, mode))
185
    return 1;
186
 
187
  if (GET_CODE (op) == CONST_INT)
188
    return 1;
189
 
190
  return 0;
191
})
192
 
193
;; Nonzero if OP is a valid source operand for a btsti.
194
 
195
(define_predicate "mcore_literal_K_operand"
196
  (match_code "const_int")
197
{
198
  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
199
    return 1;
200
 
201
  return 0;
202
})
203
 
204
;; Nonzero if OP is a valid source operand for an add/sub insn.
205
 
206
(define_predicate "mcore_addsub_operand"
207
  (match_code "const_int,reg,subreg")
208
{
209
  if (register_operand (op, mode))
210
    return 1;
211
 
212
  if (GET_CODE (op) == CONST_INT)
213
    {
214
      /* The following has been removed because it precludes large constants from being
215
         returned as valid source operands for and add/sub insn.  While large
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         constants may not directly be used in an add/sub, they may if first loaded
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         into a register.  Thus, this predicate should indicate that they are valid,
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         and the constraint in mcore.md should control whether an additional load to
219
         register is needed. (see mcore.md, addsi). -- DAC 4/2/1998
220
 
221
      if (CONST_OK_FOR_J (INTVAL (op)) || CONST_OK_FOR_L (INTVAL (op)))
222
        return 1;
223
 
224
         However we do still need to check to make sure that the constant is not too
225
         big, especially if we are running on a 64-bit OS...  Nickc 8/1/07.  */
226
 
227
      if (trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
228
        return 0;
229
 
230
      return 1;
231
 
232
    }
233
 
234
  return 0;
235
})
236
 
237
;; Nonzero if OP is a valid source operand for a compare operation.
238
 
239
(define_predicate "mcore_compare_operand"
240
  (match_code "const_int,reg,subreg")
241
{
242
  if (register_operand (op, mode))
243
    return 1;
244
 
245
  if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
246
    return 1;
247
 
248
  return 0;
249
})
250
 
251
;; Return 1 if OP is a load multiple operation.  It is known to be a
252
;; PARALLEL and the first section will be tested.
253
 
254
(define_predicate "mcore_load_multiple_operation"
255
  (match_code "parallel")
256
{
257
  int count = XVECLEN (op, 0);
258
  int dest_regno;
259
  rtx src_addr;
260
  int i;
261
 
262
  /* Perform a quick check so we don't blow up below.  */
263
  if (count <= 1
264
      || GET_CODE (XVECEXP (op, 0, 0)) != SET
265
      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
266
      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
267
    return 0;
268
 
269
  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
270
  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
271
 
272
  for (i = 1; i < count; i++)
273
    {
274
      rtx elt = XVECEXP (op, 0, i);
275
 
276
      if (GET_CODE (elt) != SET
277
          || GET_CODE (SET_DEST (elt)) != REG
278
          || GET_MODE (SET_DEST (elt)) != SImode
279
          || REGNO (SET_DEST (elt))    != (unsigned) (dest_regno + i)
280
          || GET_CODE (SET_SRC (elt))  != MEM
281
          || GET_MODE (SET_SRC (elt))  != SImode
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          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
283
          || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
284
          || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
285
          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
286
        return 0;
287
    }
288
 
289
  return 1;
290
})
291
 
292
;; Similar, but tests for store multiple.
293
 
294
(define_predicate "mcore_store_multiple_operation"
295
  (match_code "parallel")
296
{
297
  int count = XVECLEN (op, 0);
298
  int src_regno;
299
  rtx dest_addr;
300
  int i;
301
 
302
  /* Perform a quick check so we don't blow up below.  */
303
  if (count <= 1
304
      || GET_CODE (XVECEXP (op, 0, 0)) != SET
305
      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
306
      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
307
    return 0;
308
 
309
  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
310
  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
311
 
312
  for (i = 1; i < count; i++)
313
    {
314
      rtx elt = XVECEXP (op, 0, i);
315
 
316
      if (GET_CODE (elt) != SET
317
          || GET_CODE (SET_SRC (elt)) != REG
318
          || GET_MODE (SET_SRC (elt)) != SImode
319
          || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
320
          || GET_CODE (SET_DEST (elt)) != MEM
321
          || GET_MODE (SET_DEST (elt)) != SImode
322
          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
323
          || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
324
          || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
325
          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
326
        return 0;
327
    }
328
 
329
  return 1;
330
})
331
 
332
;; TODO: Add a comment here.
333
 
334
(define_predicate "mcore_call_address_operand"
335
  (match_code "reg,subreg,const_int,symbol_ref")
336
{
337
  return register_operand (op, mode) || CONSTANT_P (op);
338
})

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