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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [mep/] [mep-core.cpu] - Blame information for rev 282

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1 282 jeremybenn
; Toshiba MeP Media Engine architecture description.  -*- Scheme -*-
2
; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2009
3
; Free Software Foundation, Inc.
4
; Contributed by Red Hat, Inc.
5
;
6
; This file is part of GCC.
7
;
8
; GCC is free software; you can redistribute it and/or modify it under
9
; the terms of the GNU General Public License as published by the Free
10
; Software Foundation; either version 3, or (at your option) any later
11
; version.
12
;
13
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16
; for more details.
17
;
18
; You should have received a copy of the GNU General Public License
19
; along with GCC; see the file COPYING3.  If not see
20
; .
21
 
22
(include "simplify.inc")
23
 
24
(define-pmacro isa-enum ()
25
  (isas mep
26
; begin-isa-enum
27
        ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
28
; end-isa-enum
29
  )
30
)
31
 
32
(define-arch
33
  (name mep)
34
  (comment "Toshiba MeP Media Engine")
35
  (insn-lsb0? #f) ;; work around cgen limitation
36
  (machs mep h1 c5)
37
  isa-enum
38
)
39
 
40
(define-isa
41
  (name mep)
42
  (comment "MeP core instruction set")
43
  (default-insn-word-bitsize 32)
44
  (default-insn-bitsize 32)
45
  (base-insn-bitsize 32)
46
)
47
 
48
; begin-isas
49
(define-isa
50
  (name ext_core1)
51
  (comment "MeP core extension instruction set")
52
  (default-insn-word-bitsize 32)
53
  (default-insn-bitsize 32)
54
  (base-insn-bitsize 32)
55
)
56
 
57
(define-isa
58
  (name ext_cop1_16)
59
  (comment "MeP coprocessor instruction set")
60
  (default-insn-word-bitsize 32)
61
  (default-insn-bitsize 32)
62
  (base-insn-bitsize 32)
63
)
64
 
65
(define-isa
66
  (name ext_cop1_32)
67
  (comment "MeP coprocessor instruction set")
68
  (default-insn-word-bitsize 32)
69
  (default-insn-bitsize 32)
70
  (base-insn-bitsize 32)
71
)
72
 
73
(define-isa
74
  (name ext_cop1_48)
75
  (comment "MeP coprocessor instruction set")
76
  (default-insn-word-bitsize 32)
77
  (default-insn-bitsize 32)
78
  (base-insn-bitsize 32)
79
)
80
 
81
(define-isa
82
  (name ext_cop1_64)
83
  (comment "MeP coprocessor instruction set")
84
  (default-insn-word-bitsize 32)
85
  (default-insn-bitsize 32)
86
  (base-insn-bitsize 32)
87
)
88
 
89
(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
90
 
91
(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32))
92
 
93
(define-pmacro all-core-isa-list () mep,ext_core1)
94
; end-isas
95
 
96
(define-cpu
97
  (name mepf)
98
  (comment "MeP family")
99
  (endian either)
100
  (insn-chunk-bitsize 16)
101
  (word-bitsize 32)
102
)
103
 
104
(define-mach
105
  (name mep)
106
  (comment "MeP media engine")
107
  (cpu mepf)
108
  isa-enum
109
)
110
 
111
(define-mach
112
  (name h1)
113
  (comment "H1 media engine")
114
  (cpu mepf)
115
  isa-enum
116
)
117
 
118
(define-mach
119
  (name c5)
120
  (comment "C5 media engine")
121
  (cpu mepf)
122
  isa-enum
123
)
124
 
125
(define-model
126
  (name mep)
127
  (comment "MeP media engine processor")
128
  (mach c5) ; mach gets changed by MeP-Integrator
129
 
130
  (unit u-exec "execution unit" ()
131
        1 1 ; issue done
132
        () () () ())
133
 
134
  ; Branch unit
135
  (unit u-branch "Branch Unit" ()
136
 
137
        () ; state
138
        () ; inputs
139
        ((pc)) ; outputs
140
        () ; profile action (default)
141
        )
142
 
143
  ; Multiply unit
144
  (unit u-multiply "Multiply Unit" ()
145
 
146
        () ; state
147
        () ; inputs
148
        () ; outputs
149
        () ; profile action (default)
150
        )
151
 
152
  ; Divide unit
153
  (unit u-divide "Divide Unit" ()
154
 
155
        () ; state
156
        () ; inputs
157
        () ; outputs
158
        () ; profile action (default)
159
        )
160
 
161
  ; Stcb unit
162
  (unit u-stcb "stcb Unit" ()
163
 
164
        () ; state
165
        () ; inputs
166
        () ; outputs
167
        () ; profile action (default)
168
        )
169
 
170
  ; Ldcb unit
171
  (unit u-ldcb "ldcb Unit" ()
172
 
173
        () ; state
174
        () ; inputs
175
        () ; outputs
176
        () ; profile action (default)
177
        )
178
 
179
  ; Load gpr unit
180
  (unit u-load-gpr "Load into GPR Unit" ()
181
 
182
        () ; state
183
        () ; inputs
184
        ((loadreg INT -1)) ; outputs
185
        () ; profile action (default)
186
        )
187
 
188
  (unit u-ldcb-gpr "Ldcb into GPR Unit" ()
189
 
190
        () ; state
191
        () ; inputs
192
        ((loadreg INT -1)) ; outputs
193
        () ; profile action (default)
194
        )
195
 
196
  ; Multiply into GPR unit
197
  (unit u-mul-gpr "Multiply into GPR Unit" ()
198
 
199
        () ; state
200
        () ; inputs
201
        ((resultreg INT -1)) ; outputs
202
        () ; profile action (default)
203
        )
204
 
205
  ; Use gpr unit -- stalls if GPR not ready
206
  (unit u-use-gpr "Use GPR Unit" ()
207
 
208
        () ; state
209
        ((usereg INT -1)) ; inputs
210
        () ; outputs
211
        () ; profile action (default)
212
        )
213
 
214
  ; Use ctrl-reg unit -- stalls if CTRL-REG not ready
215
  (unit u-use-ctrl-reg "Use CTRL-REG Unit" ()
216
 
217
        () ; state
218
        ((usereg INT -1)) ; inputs
219
        () ; outputs
220
        () ; profile action (default)
221
        )
222
 
223
  ; Store ctrl-reg unit -- stalls if CTRL-REG not ready
224
  (unit u-store-ctrl-reg "Store CTRL-REG Unit" ()
225
 
226
        () ; state
227
        () ; inputs
228
        ((storereg INT -1)) ; outputs
229
        () ; profile action (default)
230
        )
231
)
232
 
233
; Hardware elements.
234
 
235
(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ())
236
 
237
(define-hardware
238
  (name h-gpr)
239
  (comment "General purpose registers")
240
  (attrs all-mep-isas CACHE-ADDR PROFILE)
241
  (type register SI (16))
242
  (indices keyword "$"
243
           (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5)
244
            ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
245
            ; "$8" is the preferred name for register 8, but "$tp", "$gp"
246
            ; and "$sp" are preferred for their respective registers.
247
            (fp  8) (tp 13) (gp 14) (sp 15)
248
            ("12" 12) ("13" 13) ("14" 14) ("15" 15)))
249
)
250
 
251
(define-hardware
252
  (name h-csr)
253
  (comment "Control/special registers")
254
  (attrs all-mep-isas PROFILE)
255
  (type register SI (32))
256
  (indices keyword "$"
257
           ((pc 0)   (lp 1)   (sar 2)   (rpb  4) (rpe 5)   (rpc 6)
258
            (hi 7)   (lo 8)   (mb0 12)  (me0 13) (mb1 14)  (me1 15)
259
            (psw 16) (id 17)  (tmp 18)  (epc 19) (exc 20)  (cfg 21)
260
            (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28)
261
; begin-extra-csr-registers
262
            (vid 22)
263
; end-extra-csr-registers
264
  ))
265
  (get (index) (c-call SI "cgen_get_csr_value" index))
266
  (set (index newval) (c-call VOID "cgen_set_csr_value" index newval))
267
)
268
 
269
(define-pmacro (-reg-pair n) ((.sym n) n))
270
(define-hardware
271
  (name h-cr64)
272
  (comment "64-bit coprocessor registers")
273
  (attrs all-mep-isas)
274
  ; This assumes that the data path of the co-pro is 64 bits.
275
  (type register DI (32))
276
  (indices keyword "$c" (.map -reg-pair (.iota 32)))
277
  (set (index newval) (c-call VOID "h_cr64_queue_set" index newval))
278
)
279
(define-hardware
280
  (name h-cr64-w)
281
  (comment "64-bit coprocessor registers, pending writes")
282
  (attrs all-mep-isas)
283
  ; This assumes that the data path of the co-pro is 64 bits.
284
  (type register DI (32))
285
)
286
 
287
(define-hardware
288
  (name h-cr)
289
  (comment "32-bit coprocessor registers")
290
  (attrs all-mep-isas VIRTUAL)
291
  (type register SI (32))
292
  (indices keyword "$c" (.map -reg-pair (.iota 32)))
293
  (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
294
  (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
295
)
296
 
297
;; Given a coprocessor control register number N, expand to a
298
;; name/index pair: ($ccrN N)
299
(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n))
300
 
301
(define-hardware
302
  (name h-ccr)
303
  (comment "Coprocessor control registers")
304
  (attrs all-mep-isas)
305
  (type register SI (64))
306
  (indices keyword "" (.map -ccr-reg-pair (.iota 64)))
307
  (set (index newval) (c-call VOID "h_ccr_queue_set" index newval))
308
)
309
(define-hardware
310
  (name h-ccr-w)
311
  (comment "Coprocessor control registers, pending writes")
312
  (attrs all-mep-isas)
313
  (type register SI (64))
314
)
315
 
316
 
317
; Instruction fields.  Bit numbering reversed.
318
 
319
; Conventions:
320
;
321
; N = number of bits in value
322
; A = alignment (2 or 4, omit for 1)
323
; B = leftmost (i.e. closest to zero) bit position
324
;
325
; -- Generic Fields (f-*) --
326
; N             number of bits in *value* (1-24)
327
; [us]          signed vs unsigned
328
; B             position of left-most bit (4-16)
329
; aA            opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc)
330
; n             opt. for noncontiguous fields
331
; f-foo-{hi,lo} msb/lsb parts of field f-foo
332
;
333
; -- Operands --
334
; pcrelNaA      PC-relative branch target (signed)
335
; pcabsNaA      Absolute branch target (unsigned)
336
;
337
; [us]dispNaA   [un]signed displacement
338
; [us]immN      [un]signed immediate value
339
; addrNaA       absolute address (unsigned)
340
;
341
; Additional prefixes may be used for special cases.
342
 
343
(dnf f-major   "major opcode"            (all-mep-core-isas)    0  4)
344
 
345
(dnf f-rn      "register n"              (all-mep-core-isas)    4  4)
346
(dnf f-rn3     "register 0-7"            (all-mep-core-isas)    5  3)
347
(dnf f-rm      "register m"              (all-mep-core-isas)    8  4)
348
(dnf f-rl      "register l"              (all-mep-core-isas)   12  4)
349
(dnf f-sub2    "sub opcode (2 bits)"     (all-mep-core-isas)   14  2)
350
(dnf f-sub3    "sub opcode (3 bits)"     (all-mep-core-isas)   13  3)
351
(dnf f-sub4    "sub opcode (4 bits)"     (all-mep-core-isas)   12  4)
352
(dnf f-ext     "extended field"          (all-mep-core-isas)   16  8)
353
(dnf f-ext4    "extended field 16:4"     (all-mep-core-isas)   16  4)
354
(dnf f-ext62   "extended field 20:2"     (all-mep-core-isas)   20  2)
355
(dnf f-crn     "copro register n"        (all-mep-core-isas)    4  4)
356
 
357
(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
358
(df f-csrn-lo "cr lo 4u8"  (all-mep-core-isas)  8 4 UINT #f #f)
359
(define-multi-ifield
360
  (name f-csrn)
361
  (comment "control reg")
362
  (attrs all-mep-core-isas)
363
  (mode UINT)
364
  (subfields f-csrn-hi f-csrn-lo)
365
  (insert (sequence ()
366
                    (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf))
367
                    (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4))))
368
  (extract (set (ifield f-csrn)
369
                (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo))))
370
  )
371
 
372
(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f)
373
(df f-crnx-lo "crx lo 4u4"  (all-mep-core-isas)  4 4 UINT #f #f)
374
(define-multi-ifield
375
  (name f-crnx)
376
  (comment "copro register n (0-31)")
377
  (attrs all-mep-core-isas)
378
  (mode UINT)
379
  (subfields f-crnx-hi f-crnx-lo)
380
  (insert (sequence ()
381
                    (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf))
382
                    (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4))))
383
  (extract (set (ifield f-crnx)
384
                (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo))))
385
  )
386
 
387
; Miscellaneous fields.
388
 
389
(define-pmacro (dnfb n)
390
  (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1))
391
 
392
; Define small fields used throughout the instruction set description.
393
; Each field (eg. `f-N') is at single bit field at position N.
394
 
395
(dnfb  0)
396
(dnfb  1)
397
(dnfb  2)
398
(dnfb  3)
399
(dnfb  4)
400
(dnfb  5)
401
(dnfb  6)
402
(dnfb  7)
403
(dnfb  8)
404
(dnfb  9)
405
(dnfb  10)
406
(dnfb  11)
407
(dnfb  12)
408
(dnfb  13)
409
(dnfb  14)
410
(dnfb  15)
411
(dnfb  16)
412
(dnfb  17)
413
(dnfb  18)
414
(dnfb  19)
415
(dnfb  20)
416
(dnfb  21)
417
(dnfb  22)
418
(dnfb  23)
419
(dnfb  24)
420
(dnfb  25)
421
(dnfb  26)
422
(dnfb  27)
423
(dnfb  28)
424
(dnfb  29)
425
(dnfb  30)
426
(dnfb  31)
427
 
428
; Branch/Jump target addresses
429
 
430
(df f-8s8a2 "pc-rel addr (8 bits)"    (all-mep-core-isas PCREL-ADDR)  8  7 INT
431
    ((value pc) (sra SI (sub SI value    pc) 1))
432
    ((value pc) (add SI (sll SI value 1) pc)))
433
 
434
(df f-12s4a2 "pc-rel addr (12 bits)"  (all-mep-core-isas PCREL-ADDR)  4 11 INT
435
    ((value pc) (sra SI (sub SI value    pc) 1))
436
    ((value pc) (add SI (sll SI value 1) pc)))
437
 
438
(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT
439
    ((value pc) (sra SI (sub SI value    pc) 1))
440
    ((value pc) (add SI (sll SI value 1) pc)))
441
 
442
(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16  INT #f #f)
443
(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR)  5  7 UINT #f #f)
444
(define-multi-ifield
445
  (name f-24s5a2n)
446
  (comment "pc-rel addr (24 bits align 2)")
447
  (attrs all-mep-core-isas PCREL-ADDR)
448
  (mode INT)
449
  (subfields f-24s5a2n-hi f-24s5a2n-lo)
450
  (insert (sequence ()
451
                    (set (ifield f-24s5a2n)
452
                         (sub (ifield f-24s5a2n) pc))
453
                    (set (ifield f-24s5a2n-lo)
454
                         (srl (and (ifield f-24s5a2n) #xfe) 1))
455
                    (set (ifield f-24s5a2n-hi)
456
                         (sra INT (ifield f-24s5a2n) 8))))
457
  (extract (set (ifield f-24s5a2n)
458
                (add SI (or (sll (ifield f-24s5a2n-hi) 8)
459
                            (sll (ifield f-24s5a2n-lo) 1))
460
                     pc)))
461
  )
462
 
463
(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
464
(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas)  5  7 UINT #f #f)
465
(define-multi-ifield
466
  (name f-24u5a2n)
467
  (comment "abs jump target (24 bits, alignment 2)")
468
  (attrs all-mep-core-isas ABS-ADDR)
469
  (mode UINT)
470
  (subfields f-24u5a2n-hi f-24u5a2n-lo)
471
  (insert (sequence ()
472
                    (set (ifield f-24u5a2n-lo)
473
                         (srl (and (ifield f-24u5a2n) #xff) 1))
474
                    (set (ifield f-24u5a2n-hi)
475
                         (srl (ifield f-24u5a2n) 8))
476
                    ))
477
  (extract (set (ifield f-24u5a2n)
478
                (or (sll (ifield f-24u5a2n-hi) 8)
479
                    (sll (ifield f-24u5a2n-lo) 1))))
480
  )
481
 
482
; Displacement fields.
483
 
484
(df f-2u6     "SAR offset (2 bits)"    (all-mep-core-isas)  6  2 UINT #f #f)
485
(df f-7u9     "tp-rel b (7 bits)"      (all-mep-core-isas)  9  7 UINT #f #f)
486
(df f-7u9a2   "tp-rel h (7 bits)"      (all-mep-core-isas)  9  6 UINT
487
    ((value pc) (srl SI value 1))
488
    ((value pc) (sll SI value 1)))
489
(df f-7u9a4   "tp/sp-rel w (7 bits)"   (all-mep-core-isas)  9  5 UINT
490
    ((value pc) (srl SI value 2))
491
    ((value pc) (sll SI value 2)))
492
(df f-16s16   "general 16-bit s-val"   (all-mep-core-isas) 16 16  INT #f #f)
493
 
494
; Immediate fields.
495
 
496
(df f-2u10   "swi level (2 bits)"      (all-mep-core-isas) 10  2 UINT #f #f)
497
(df f-3u5    "bit offset (3 bits)"     (all-mep-core-isas)  5  3 UINT #f #f)
498
(df f-4u8    "bCC const (4 bits)"      (all-mep-core-isas)  8  4 UINT #f #f)
499
(df f-5u8    "slt & shifts (5 bits)"   (all-mep-core-isas)  8  5 UINT #f #f)
500
(df f-5u24   "clip immediate (5 bits)" (all-mep-core-isas) 24  5 UINT #f #f)
501
(df f-6s8    "add immediate (6 bits)"  (all-mep-core-isas)  8  6  INT #f #f)
502
(df f-8s8    "add imm (8 bits)"        (all-mep-core-isas)  8  8  INT #f #f)
503
(df f-16u16  "general 16-bit u-val"    (all-mep-core-isas) 16 16 UINT #f #f)
504
(df f-12u16  "cmov fixed 1"            (all-mep-core-isas) 16 12 UINT #f #f)
505
(df f-3u29   "cmov fixed 2"            (all-mep-core-isas) 29  3 UINT #f #f)
506
 
507
 
508
; These are all for the coprocessor opcodes
509
 
510
; The field is like IJKiiiiiii where I and J are toggled if K is set,
511
; for compatibility with older cores.
512
(define-pmacro (compute-cdisp10 val)
513
  (cond SI
514
        ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200)
515
         (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400))
516
        (else
517
         (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)))
518
        )
519
  )
520
(define-pmacro (extend-cdisp10 val)
521
  (cond SI
522
        ((and SI (compute-cdisp10 val) #x200)
523
         (sub (and SI (compute-cdisp10 val) #x3ff) #x400))
524
        (else
525
         (and SI (compute-cdisp10 val) #x3ff))
526
        )
527
  )
528
 
529
(df f-cdisp10    "cop imm10"          (all-mep-core-isas)   22  10 INT
530
    ((value pc) (extend-cdisp10 value))
531
    ((value pc) (extend-cdisp10 value))
532
    )
533
 
534
; Non-contiguous fields.
535
 
536
(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
537
(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas)  8  6 UINT #f #f)
538
(define-multi-ifield
539
  (name f-24u8a4n)
540
  (comment "absolute 24-bit address")
541
  (attrs all-mep-core-isas)
542
  (mode UINT)
543
  (subfields f-24u8a4n-hi f-24u8a4n-lo)
544
  (insert (sequence ()
545
                    (set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8))
546
                    (set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2))))
547
  (extract (set (ifield f-24u8a4n)
548
                (or (sll (ifield f-24u8a4n-hi) 8)
549
                    (sll (ifield f-24u8a4n-lo) 2))))
550
  )
551
 
552
(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
553
(df f-24u8n-lo "24u8n lo  8u8"  (all-mep-core-isas)  8  8 UINT #f #f)
554
(define-multi-ifield
555
  (name f-24u8n)
556
  (comment "24-bit constant")
557
  (attrs all-mep-core-isas)
558
  (mode UINT)
559
  (subfields f-24u8n-hi f-24u8n-lo)
560
  (insert (sequence ()
561
                    (set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8))
562
                    (set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff))))
563
  (extract (set (ifield f-24u8n)
564
                (or (sll (ifield f-24u8n-hi) 8)
565
                    (ifield f-24u8n-lo))))
566
  )
567
 
568
(df f-24u4n-hi "24u4n hi  8u4"  (all-mep-core-isas)  4  8 UINT #f #f)
569
(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
570
(define-multi-ifield
571
  (name f-24u4n)
572
  (comment "coprocessor code")
573
  (attrs all-mep-core-isas)
574
  (mode UINT)
575
  (subfields f-24u4n-hi f-24u4n-lo)
576
  (insert (sequence ()
577
                    (set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16))
578
                    (set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff))))
579
  (extract (set (ifield f-24u4n)
580
                (or (sll (ifield f-24u4n-hi) 16)
581
                    (ifield f-24u4n-lo))))
582
  )
583
 
584
(define-multi-ifield
585
  (name f-callnum)
586
  (comment "system call number field")
587
  (attrs all-mep-core-isas)
588
  (mode UINT)
589
  (subfields f-5 f-6 f-7 f-11)
590
  (insert (sequence ()
591
                    (set (ifield f-5)  (and (srl (ifield f-callnum) 3) 1))
592
                    (set (ifield f-6)  (and (srl (ifield f-callnum) 2) 1))
593
                    (set (ifield f-7)  (and (srl (ifield f-callnum) 1) 1))
594
                    (set (ifield f-11) (and (ifield f-callnum) 1))))
595
  (extract (set (ifield f-callnum)
596
                (or (sll (ifield f-5) 3)
597
                    (or (sll (ifield f-6) 2)
598
                        (or (sll (ifield f-7) 1)
599
                            (ifield f-11))))))
600
  )
601
 
602
(df f-ccrn-hi "ccrn hi  2u28" (all-mep-core-isas) 28 2 UINT #f #f)
603
(df f-ccrn-lo "ccrn lo  4u4"  (all-mep-core-isas)  4 4 UINT #f #f)
604
(define-multi-ifield
605
  (name f-ccrn)
606
  (comment "Coprocessor register number field")
607
  (attrs all-mep-core-isas)
608
  (mode UINT)
609
  (subfields f-ccrn-hi f-ccrn-lo)
610
  (insert (sequence ()
611
                    (set (ifield f-ccrn-hi)  (and (srl (ifield f-ccrn) 4) #x3))
612
                    (set (ifield f-ccrn-lo)  (and (ifield f-ccrn) #xf))))
613
  (extract (set (ifield f-ccrn)
614
                (or (sll (ifield f-ccrn-hi) 4)
615
                    (ifield f-ccrn-lo))))
616
  )
617
 
618
; Operands.
619
 
620
;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct
621
;; operation.  The others are mostly kept for backwards compatibility,
622
;; although they do affect the dummy prototypes in
623
;; gcc/config/mep/intrinsics.h.
624
(define-attr
625
  (type enum)
626
  (for operand)
627
  (name CDATA)
628
  (comment "datatype to use for C intrinsics mapping")
629
  (values LABEL REGNUM FMAX_FLOAT FMAX_INT
630
          POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT)
631
  (default LONG))
632
 
633
(define-attr
634
  (type enum)
635
  (for insn)
636
  (name CPTYPE)
637
  (comment "datatype to use for coprocessor values")
638
  (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI)
639
  (default CP_DATA_BUS_INT))
640
 
641
(define-attr
642
  (type enum)
643
  (for insn)
644
  (name CRET)
645
  ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed.
646
  ;; FIRST - the first argument is the return value.
647
  ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter.
648
  (values VOID FIRST FIRSTCOPY)
649
  (default VOID)
650
  (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it."))
651
 
652
(define-attr
653
  (type integer)
654
  (for operand)
655
  (name ALIGN)
656
  (comment "alignment of immediate operands")
657
  (default 1))
658
 
659
(define-attr
660
  (for operand)
661
  (type boolean)
662
  (name RELOC_IMPLIES_OVERFLOW)
663
  (comment "Operand should not be considered as a candidate for relocs"))
664
 
665
(define-attr
666
  (for hardware)
667
  (type boolean)
668
  (name IS_FLOAT)
669
  (comment "Register contains a floating point value"))
670
 
671
(define-pmacro (dpop name commment attrib hwr field func)
672
  (define-full-operand name comment attrib
673
    hwr DFLT field ((parse func)) () ()))
674
(define-pmacro (dprp name commment attrib hwr field pafunc prfunc)
675
  (define-full-operand name comment attrib
676
    hwr DFLT field ((parse pafunc) (print prfunc)) () ()))
677
 
678
(dnop r0        "register 0"              (all-mep-core-isas) h-gpr   0)
679
(dnop rn        "register Rn"             (all-mep-core-isas) h-gpr   f-rn)
680
(dnop rm        "register Rm"             (all-mep-core-isas) h-gpr   f-rm)
681
(dnop rl        "register Rl"             (all-mep-core-isas) h-gpr   f-rl)
682
(dnop rn3       "register 0-7"            (all-mep-core-isas) h-gpr   f-rn3)
683
 
684
;; Variants of RM/RN with different CDATA attributes.  See comment above
685
;; CDATA for more details.
686
 
687
(dnop rma       "register Rm holding pointer"          (all-mep-core-isas (CDATA POINTER)) h-gpr   f-rm)
688
 
689
(dnop rnc       "register Rn holding char"             (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
690
(dnop rnuc      "register Rn holding unsigned char"    (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
691
(dnop rns       "register Rn holding short"            (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
692
(dnop rnus      "register Rn holding unsigned short"   (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
693
(dnop rnl       "register Rn holding long"             (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
694
(dnop rnul      "register Rn holding unsigned  long"   (all-mep-core-isas (CDATA ULONG))   h-gpr   f-rn)
695
 
696
(dnop rn3c       "register 0-7 holding unsigned char"    (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
697
(dnop rn3uc      "register 0-7 holding byte"             (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
698
(dnop rn3s       "register 0-7 holding unsigned short"   (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
699
(dnop rn3us      "register 0-7 holding short"            (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
700
(dnop rn3l       "register 0-7 holding unsigned long"    (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
701
(dnop rn3ul      "register 0-7 holding long"             (all-mep-core-isas (CDATA ULONG)) h-gpr   f-rn3)
702
 
703
 
704
(dnop lp        "link pointer"            (all-mep-core-isas) h-csr   1)
705
(dnop sar       "shift amount register"   (all-mep-core-isas) h-csr   2)
706
(dnop hi        "high result"             (all-mep-core-isas) h-csr   7)
707
(dnop lo        "low result"              (all-mep-core-isas) h-csr   8)
708
(dnop mb0       "modulo begin register 0" (all-mep-core-isas) h-csr  12)
709
(dnop me0       "modulo end register 0"   (all-mep-core-isas) h-csr  13)
710
(dnop mb1       "modulo begin register 1" (all-mep-core-isas) h-csr  14)
711
(dnop me1       "modulo end register 1"   (all-mep-core-isas) h-csr  15)
712
(dnop psw       "program status word"     (all-mep-core-isas) h-csr  16)
713
(dnop epc       "exception prog counter"  (all-mep-core-isas) h-csr  19)
714
(dnop exc       "exception cause"         (all-mep-core-isas) h-csr  20)
715
(dnop npc       "nmi program counter"     (all-mep-core-isas) h-csr  23)
716
(dnop dbg       "debug register"          (all-mep-core-isas) h-csr  24)
717
(dnop depc      "debug exception pc"      (all-mep-core-isas) h-csr  25)
718
(dnop opt       "option register"         (all-mep-core-isas) h-csr  26)
719
(dnop r1        "register 1"              (all-mep-core-isas) h-gpr   1)
720
(dnop tp        "tiny data area pointer"  (all-mep-core-isas) h-gpr  13)
721
(dnop sp        "stack pointer"           (all-mep-core-isas) h-gpr  15)
722
(dprp tpr       "TP register"             (all-mep-core-isas) h-gpr  13       "tpreg" "tpreg")
723
(dprp spr       "SP register"             (all-mep-core-isas) h-gpr  15       "spreg" "spreg")
724
 
725
(define-full-operand
726
  csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr
727
  DFLT f-csrn ((parse "csrn")) () ()
728
)
729
 
730
(dnop csrn-idx  "control/special reg idx" (all-mep-core-isas) h-uint  f-csrn)
731
(dnop crn64     "copro Rn (64-bit)"       (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64  f-crn)
732
(dnop crn       "copro Rn (32-bit)"       (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr    f-crn)
733
(dnop crnx64    "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64  f-crnx)
734
(dnop crnx      "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr    f-crnx)
735
(dnop ccrn      "copro control reg CCRn"  (all-mep-core-isas (CDATA REGNUM)) h-ccr   f-ccrn)
736
(dnop cccc      "copro flags"             (all-mep-core-isas) h-uint  f-rm)
737
 
738
(dprp pcrel8a2  "pc-rel addr (8 bits)"    (all-mep-core-isas (CDATA LABEL) RELAX) h-sint  f-8s8a2   "mep_align" "address")
739
(dprp pcrel12a2 "pc-rel addr (12 bits)"   (all-mep-core-isas (CDATA LABEL) RELAX) h-sint  f-12s4a2  "mep_align" "address")
740
(dprp pcrel17a2 "pc-rel addr (17 bits)"   (all-mep-core-isas (CDATA LABEL) RELAX) h-sint  f-17s16a2 "mep_align" "address")
741
(dprp pcrel24a2 "pc-rel addr (24 bits)"   (all-mep-core-isas (CDATA LABEL))       h-sint  f-24s5a2n "mep_align" "address")
742
(dprp pcabs24a2 "pc-abs addr (24 bits)"   (all-mep-core-isas (CDATA LABEL))       h-uint  f-24u5a2n "mep_alignu" "address")
743
 
744
(dpop sdisp16   "displacement (16 bits)"  (all-mep-core-isas) h-sint  f-16s16    "signed16")
745
(dpop simm16    "signed imm (16 bits)"    (all-mep-core-isas) h-sint  f-16s16    "signed16")
746
(dpop uimm16    "unsigned imm (16 bits)"  (all-mep-core-isas) h-uint  f-16u16    "unsigned16")
747
(dnop code16    "uci/dsp code (16 bits)"  (all-mep-core-isas) h-uint  f-16u16)
748
 
749
(dnop udisp2    "SSARB addend (2 bits)"   (all-mep-core-isas) h-sint  f-2u6)
750
(dnop uimm2     "interrupt (2 bits)"      (all-mep-core-isas) h-uint  f-2u10)
751
 
752
(dnop simm6     "add const (6 bits)"      (all-mep-core-isas) h-sint  f-6s8)
753
(dnop simm8     "mov const (8 bits)"      (all-mep-core-isas RELOC_IMPLIES_OVERFLOW)
754
                                             h-sint  f-8s8)
755
 
756
(dpop addr24a4  "sw/lw addr (24 bits)"    (all-mep-core-isas (ALIGN 4)) h-uint  f-24u8a4n  "mep_alignu")
757
(dnop code24    "coprocessor code"        (all-mep-core-isas) h-uint  f-24u4n)
758
 
759
(dnop callnum   "system call number"      (all-mep-core-isas) h-uint  f-callnum)
760
(dnop uimm3     "bit immediate (3 bits)"  (all-mep-core-isas) h-uint  f-3u5)
761
(dnop uimm4     "bCC const (4 bits)"      (all-mep-core-isas) h-uint  f-4u8)
762
(dnop uimm5     "bit/shift val (5 bits)"  (all-mep-core-isas) h-uint  f-5u8)
763
 
764
(dpop udisp7    "tp-rel b (7 bits)"       (all-mep-core-isas)           h-uint  f-7u9      "unsigned7")
765
(dpop udisp7a2  "tp-rel h (7 bits)"       (all-mep-core-isas (ALIGN 2)) h-uint  f-7u9a2    "unsigned7")
766
(dpop udisp7a4  "tp/sp-rel w (7 bits)"    (all-mep-core-isas (ALIGN 4)) h-uint  f-7u9a4    "unsigned7")
767
(dpop uimm7a4   "sp w-addend (7 bits)"    (all-mep-core-isas (ALIGN 4)) h-uint  f-7u9a4    "mep_alignu")
768
 
769
(dnop uimm24    "immediate (24 bits)"     (all-mep-core-isas) h-uint  f-24u8n)
770
 
771
(dnop cimm4     "cache immed'te (4 bits)" (all-mep-core-isas) h-uint  f-rn)
772
(dnop cimm5     "clip immediate (5 bits)" (all-mep-core-isas) h-uint  f-5u24)
773
 
774
(dpop cdisp10   "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
775
(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
776
(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
777
(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
778
 
779
; Special operand representing the various ways that the literal zero can be
780
; specified.
781
(define-full-operand
782
  zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil
783
  ((parse "zero")) () ()
784
)
785
 
786
; Attributes.
787
 
788
(define-attr
789
  (for insn)
790
  (type boolean)
791
  (name OPTIONAL_BIT_INSN)
792
  (comment "optional bit manipulation instruction"))
793
 
794
(define-attr
795
  (for insn)
796
  (type boolean)
797
  (name OPTIONAL_MUL_INSN)
798
  (comment "optional 32-bit multiply instruction"))
799
 
800
(define-attr
801
  (for insn)
802
  (type boolean)
803
  (name OPTIONAL_DIV_INSN)
804
  (comment "optional 32-bit divide instruction"))
805
 
806
(define-attr
807
  (for insn)
808
  (type boolean)
809
  (name OPTIONAL_DEBUG_INSN)
810
  (comment "optional debug instruction"))
811
 
812
(define-attr
813
  (for insn)
814
  (type boolean)
815
  (name OPTIONAL_LDZ_INSN)
816
  (comment "optional leading zeroes instruction"))
817
 
818
(define-attr
819
  (for insn)
820
  (type boolean)
821
  (name OPTIONAL_ABS_INSN)
822
  (comment "optional absolute difference instruction"))
823
 
824
(define-attr
825
  (for insn)
826
  (type boolean)
827
  (name OPTIONAL_AVE_INSN)
828
  (comment "optional average instruction"))
829
 
830
(define-attr
831
  (for insn)
832
  (type boolean)
833
  (name OPTIONAL_MINMAX_INSN)
834
  (comment "optional min/max instruction"))
835
 
836
(define-attr
837
  (for insn)
838
  (type boolean)
839
  (name OPTIONAL_CLIP_INSN)
840
  (comment "optional clipping instruction"))
841
 
842
(define-attr
843
  (for insn)
844
  (type boolean)
845
  (name OPTIONAL_SAT_INSN)
846
  (comment "optional saturation instruction"))
847
 
848
(define-attr
849
  (for insn)
850
  (type boolean)
851
  (name OPTIONAL_UCI_INSN)
852
  (comment "optional UCI instruction"))
853
 
854
(define-attr
855
  (for insn)
856
  (type boolean)
857
  (name OPTIONAL_DSP_INSN)
858
  (comment "optional DSP instruction"))
859
 
860
(define-attr
861
  (for insn)
862
  (type boolean)
863
  (name OPTIONAL_CP_INSN)
864
  (comment "optional coprocessor-related instruction"))
865
 
866
(define-attr
867
  (for insn)
868
  (type boolean)
869
  (name OPTIONAL_CP64_INSN)
870
  (comment "optional coprocessor-related 64 data bit instruction"))
871
 
872
(define-attr
873
  (for insn)
874
  (type boolean)
875
  (name OPTIONAL_VLIW64)
876
  (comment "optional vliw64 mode (vliw32 is default)"))
877
 
878
(define-attr
879
  (for insn)
880
  (type enum)
881
  (name STALL)
882
  (attrs META)
883
  (values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET
884
          ADVCK MUL MULR DIV)
885
  (default NONE)
886
  (comment "gcc stall attribute"))
887
 
888
(define-attr
889
  (for insn)
890
  (type string)
891
  (name INTRINSIC)
892
  (attrs META)
893
  (comment "gcc intrinsic name"))
894
 
895
(define-attr
896
  (for insn)
897
  (type enum)
898
  (name SLOT)
899
  (attrs META)
900
  (values NONE C3 V1 V3 P0S P0 P1)
901
  (default NONE)
902
  (comment "coprocessor slot type"))
903
 
904
(define-attr
905
  (for insn)
906
  (type boolean)
907
  (name MAY_TRAP)
908
  (comment "instruction may generate an exception"))
909
 
910
; Attributes for scheduling restrictions in vliw mode
911
 
912
(define-attr
913
  (for insn)
914
  (type boolean)
915
  (name VLIW_ALONE)
916
  (comment "instruction can be scheduled alone in vliw mode"))
917
 
918
(define-attr
919
  (for insn)
920
  (type boolean)
921
  (name VLIW_NO_CORE_NOP)
922
  (comment "there is no corresponding nop core instruction"))
923
 
924
(define-attr
925
  (for insn)
926
  (type boolean)
927
  (name VLIW_NO_COP_NOP)
928
  (comment "there is no corresponding nop coprocessor instruction"))
929
 
930
(define-attr
931
  (for insn)
932
  (type boolean)
933
  (name VLIW64_NO_MATCHING_NOP)
934
  (comment "there is no corresponding nop coprocessor instruction"))
935
(define-attr
936
  (for insn)
937
  (type boolean)
938
  (name VLIW32_NO_MATCHING_NOP)
939
  (comment "there is no corresponding nop coprocessor instruction"))
940
 
941
(define-attr
942
  (for insn)
943
  (type boolean)
944
  (name VOLATILE)
945
  (comment "Insn is volatile."))
946
 
947
(define-attr
948
  (for insn)
949
  (type integer)
950
  (name LATENCY)
951
  (comment "The latency of this insn, used for scheduling as an intrinsic in gcc")
952
  (default 0))
953
 
954
; The MeP config tool will edit this.
955
(define-attr
956
  (type enum)
957
  (for insn)
958
  (name CONFIG)
959
  (values NONE ; config-attr-start
960
        default
961
          ) ; config-attr-end
962
)
963
 
964
 
965
; Enumerations.
966
 
967
(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_
968
  f-major
969
  (.map .str (.iota 16))
970
)
971
 
972
 
973
(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa)
974
  (define-insn
975
    (name xname)
976
    (comment xcomment)
977
    (.splice attrs (.unsplice xattrs) (ISA isa))
978
    (syntax xsyntax)
979
    (format xformat)
980
    (semantics xsemantics)
981
    (.splice timing (.unsplice xtiming))
982
    )
983
)
984
 
985
(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa)
986
  (dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit)
987
)
988
 
989
; For making profiling calls and dynamic configuration
990
(define-pmacro (cg-profile caller callee)
991
  (c-call "cg_profile" caller callee)
992
)
993
; For dynamic configuration only
994
(define-pmacro (cg-profile-jump caller callee)
995
  (c-call "cg_profile_jump" caller callee)
996
)
997
 
998
; For defining Core Instructions
999
(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming)
1000
  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list)
1001
)
1002
(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit)
1003
  (dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list)
1004
)
1005
 
1006
; For defining Coprocessor Instructions
1007
;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop)
1008
;)
1009
 
1010
;; flag setting macro
1011
(define-pmacro (set-bit xop xbitnum xval)
1012
  (set xop (or
1013
            (and xop (inv (sll 1 xbitnum)))
1014
            (and (sll 1 xbitnum) (sll xval xbitnum)))))
1015
 
1016
;; some flags we commonly use in vliw reasoning / mode-switching etc.
1017
(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1))
1018
(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1))
1019
(define-pmacro (get-rm.lsb) (and rm 1))
1020
(define-pmacro (get-psw.om) (and (srl psw 12) 1))
1021
(define-pmacro (get-psw.nmi) (and (srl psw 9) 1))
1022
(define-pmacro (get-psw.iep) (and (srl psw 1) 1))
1023
(define-pmacro (get-psw.ump) (and (srl psw 3) 1))
1024
(define-pmacro (get-epc.etom) (and epc 1))
1025
(define-pmacro (get-npc.ntom) (and npc 1))
1026
(define-pmacro (get-lp.ltom) (and lp 1))
1027
 
1028
(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval))
1029
(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval))
1030
(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval))
1031
(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval))
1032
(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval))
1033
 
1034
 
1035
;; the "3 way switch" depending on our current operating mode and vliw status flags
1036
(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl)
1037
  (cond
1038
   ((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl)
1039
   ((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl)
1040
   (else core-rtl)))
1041
 
1042
;; the varying-pcrel idiom
1043
(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc)
1044
  (core-vliw-switch (set xtarg (add pc xa))
1045
                    (set xtarg (add pc xb))
1046
                    (set xtarg (add pc xc))))
1047
 
1048
;; the increasing-alignment idiom in branch displacements
1049
(define-pmacro (set-vliw-alignment-modified xtarg zaddr)
1050
  (core-vliw-switch (set xtarg (and zaddr (inv 1)))
1051
                    (set xtarg (and zaddr (inv 3)))
1052
                    (set xtarg (and zaddr (inv 7)))))
1053
 
1054
;; the increasing-alignment idiom in option-only form
1055
(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr)
1056
  (if (get-opt.vliw32)
1057
      (set xtarg (and zaddr (inv 3)))
1058
      (set xtarg (and zaddr (inv 7)))))
1059
 
1060
 
1061
 
1062
; pmacros needed for coprocessor modulo addressing.
1063
 
1064
; Taken from supplement ``The operation of the modulo addressing'' in
1065
; Toshiba documentation rev 2.2, p. 34.
1066
 
1067
(define-pmacro (compute-mask0)
1068
  (sequence SI ((SI temp))
1069
    (set temp (or mb0 me0))
1070
    (srl (const SI -1) (c-call SI "do_ldz" temp))))
1071
 
1072
(define-pmacro (mod0 immed)
1073
  (sequence SI ((SI modulo-mask))
1074
            (set modulo-mask (compute-mask0))
1075
            (if SI (eq (and rma modulo-mask) me0)
1076
                (or (and rma (inv modulo-mask)) mb0)
1077
                (add rma (ext SI immed)))))
1078
 
1079
(define-pmacro (compute-mask1)
1080
  (sequence SI ((SI temp))
1081
    (set temp (or mb1 me1))
1082
    (srl (const SI -1) (c-call SI "do_ldz" temp))))
1083
 
1084
(define-pmacro (mod1 immed)
1085
  (sequence SI ((SI modulo-mask))
1086
            (set modulo-mask (compute-mask1))
1087
            (if SI (eq (and rma modulo-mask) me1)
1088
                (or (and rma (inv modulo-mask)) mb1)
1089
                (add rma (ext SI immed)))))
1090
 
1091
 
1092
; Instructions.
1093
 
1094
; A pmacro for use in semantic bodies of unimplemented insns.
1095
(define-pmacro (unimp mnemonic) (nop))
1096
 
1097
; Core specific instructions
1098
; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
1099
(include "mep-c5.cpu") ; -- exposed by MeP-Integrator
1100
 
1101
; Load/store instructions.
1102
 
1103
(dnci sb "store byte (register indirect)" ((STALL STORE))
1104
     "sb $rnc,($rma)"
1105
     (+ MAJ_0 rnc rma (f-sub4 8))
1106
     (sequence ()
1107
               (c-call VOID "check_write_to_text" rma)
1108
               (set (mem UQI rma) (and rnc #xff)))
1109
     ((mep (unit u-use-gpr (in usereg rnc))
1110
           (unit u-use-gpr (in usereg rma))
1111
           (unit u-exec))))
1112
 
1113
(dnci sh "store half-word (register indirect)" ((STALL STORE))
1114
     "sh $rns,($rma)"
1115
     (+ MAJ_0 rns rma (f-sub4 9))
1116
     (sequence ()
1117
               (c-call VOID "check_write_to_text" (and rma (inv 1)))
1118
               (set (mem UHI (and rma (inv 1))) (and rns #xffff)))
1119
     ((mep (unit u-use-gpr (in usereg rns))
1120
           (unit u-use-gpr (in usereg rma))
1121
           (unit u-exec))))
1122
 
1123
(dnci sw "store word (register indirect)" ((STALL STORE))
1124
     "sw $rnl,($rma)"
1125
     (+ MAJ_0 rnl rma (f-sub4 10))
1126
     (sequence ()
1127
               (c-call VOID "check_write_to_text" (and rma (inv 3)))
1128
               (set (mem USI (and rma (inv 3))) rnl))
1129
     ((mep (unit u-use-gpr (in usereg rnl))
1130
           (unit u-use-gpr (in usereg rma))
1131
           (unit u-exec))))
1132
 
1133
(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2))
1134
     "lb $rnc,($rma)"
1135
     (+ MAJ_0 rnc rma (f-sub4 12))
1136
     (set rnc (ext SI (mem QI rma)))
1137
     ((mep (unit u-use-gpr (in usereg rma))
1138
           (unit u-exec)
1139
           (unit u-load-gpr (out loadreg rnc)))))
1140
 
1141
(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
1142
     "lh $rns,($rma)"
1143
     (+ MAJ_0 rns rma (f-sub4 13))
1144
     (set rns (ext SI (mem HI (and rma (inv 1)))))
1145
     ((mep (unit u-use-gpr (in usereg rma))
1146
           (unit u-exec)
1147
           (unit u-load-gpr (out loadreg rns)))))
1148
 
1149
(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2))
1150
     "lw $rnl,($rma)"
1151
     (+ MAJ_0 rnl rma (f-sub4 14))
1152
     (set rnl (mem SI (and rma (inv 3))))
1153
     ((mep (unit u-use-gpr (in usereg rma))
1154
           (unit u-exec)
1155
           (unit u-load-gpr (out loadreg rnl)))))
1156
 
1157
(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2))
1158
     "lbu $rnuc,($rma)"
1159
     (+ MAJ_0 rnuc rma (f-sub4 11))
1160
     (set rnuc (zext SI (mem UQI rma)))
1161
     ((mep (unit u-use-gpr (in usereg rma))
1162
           (unit u-exec)
1163
           (unit u-load-gpr (out loadreg rnuc)))))
1164
 
1165
(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
1166
     "lhu $rnus,($rma)"
1167
     (+ MAJ_0 rnus rma (f-sub4 15))
1168
     (set rnus (zext SI (mem UHI (and rma (inv 1)))))
1169
     ((mep (unit u-use-gpr (in usereg rma))
1170
           (unit u-exec)
1171
           (unit u-load-gpr (out loadreg rnus)))))
1172
 
1173
(dnci sw-sp "store word (sp relative)" ((STALL STORE))
1174
     "sw $rnl,$udisp7a4($spr)"
1175
     (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2))
1176
     (sequence ()
1177
               (c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3)))
1178
               (set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl))
1179
     ((mep (unit u-use-gpr (in usereg rnl))
1180
           (unit u-use-gpr (in usereg sp))
1181
           (unit u-exec))))
1182
 
1183
 
1184
(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2))
1185
     "lw $rnl,$udisp7a4($spr)"
1186
     (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3))
1187
     (set rnl (mem SI (and (add udisp7a4 sp) (inv 3))))
1188
     ((mep (unit u-use-gpr (in usereg sp))
1189
           (unit u-exec)
1190
           (unit u-load-gpr (out loadreg rnl)))))
1191
 
1192
(dnci sb-tp "store byte (tp relative)" ((STALL STORE))
1193
     "sb $rn3c,$udisp7($tpr)"
1194
     (+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7)
1195
     (sequence ()
1196
               (c-call VOID "check_write_to_text" (add (zext SI udisp7) tp))
1197
               (set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff)))
1198
     ((mep (unit u-use-gpr (in usereg rn3c))
1199
           (unit u-use-gpr (in usereg tp))
1200
           (unit u-exec))))
1201
 
1202
(dnci sh-tp "store half-word (tp relative)" ((STALL STORE))
1203
     "sh $rn3s,$udisp7a2($tpr)"
1204
     (+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0))
1205
     (sequence ()
1206
               (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1)))
1207
               (set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff)))
1208
     ((mep (unit u-use-gpr (in usereg rn3s))
1209
           (unit u-use-gpr (in usereg tp))
1210
           (unit u-exec))))
1211
 
1212
(dnci sw-tp "store word (tp relative)" ((STALL STORE))
1213
     "sw $rn3l,$udisp7a4($tpr)"
1214
     (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2))
1215
     (sequence ()
1216
               (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3)))
1217
               (set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l))
1218
     ((mep (unit u-use-gpr (in usereg rn3l))
1219
           (unit u-use-gpr (in usereg tp))
1220
           (unit u-exec))))
1221
 
1222
(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2))
1223
     "lb $rn3c,$udisp7($tpr)"
1224
     (+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7)
1225
     (set rn3c (ext SI (mem QI (add (zext SI udisp7) tp))))
1226
     ((mep (unit u-use-gpr (in usereg tp))
1227
           (unit u-exec)
1228
           (unit u-load-gpr (out loadreg rn3c)))))
1229
 
1230
(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
1231
     "lh $rn3s,$udisp7a2($tpr)"
1232
     (+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0))
1233
     (set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
1234
     ((mep (unit u-use-gpr (in usereg tp))
1235
           (unit u-exec)
1236
           (unit u-load-gpr (out loadreg rn3s)))))
1237
 
1238
(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2))
1239
     "lw $rn3l,$udisp7a4($tpr)"
1240
     (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3))
1241
     (set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))))
1242
     ((mep (unit u-use-gpr (in usereg tp))
1243
           (unit u-exec)
1244
           (unit u-load-gpr (out loadreg rn3l)))))
1245
 
1246
(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2))
1247
     "lbu $rn3uc,$udisp7($tpr)"
1248
     (+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7)
1249
     (set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp))))
1250
     ((mep (unit u-use-gpr (in usereg tp))
1251
           (unit u-exec)
1252
           (unit u-load-gpr (out loadreg rn3uc)))))
1253
 
1254
(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
1255
     "lhu $rn3us,$udisp7a2($tpr)"
1256
     (+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1))
1257
     (set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
1258
     ((mep (unit u-use-gpr (in usereg tp))
1259
           (unit u-exec)
1260
           (unit u-load-gpr (out loadreg rn3us)))))
1261
 
1262
(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE))
1263
     "sb $rnc,$sdisp16($rma)"
1264
     (+ MAJ_12 rnc rma (f-sub4 8) sdisp16)
1265
     (sequence ()
1266
               (c-call VOID "check_write_to_text" (add rma (ext SI sdisp16)))
1267
               (set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff)))
1268
     ((mep (unit u-use-gpr (in usereg rnc))
1269
           (unit u-use-gpr (in usereg rma))
1270
           (unit u-exec))))
1271
 
1272
(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE))
1273
     "sh $rns,$sdisp16($rma)"
1274
     (+ MAJ_12 rns rma (f-sub4 9) sdisp16)
1275
     (sequence ()
1276
               (c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1)))
1277
               (set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff)))
1278
     ((mep (unit u-use-gpr (in usereg rns))
1279
           (unit u-use-gpr (in usereg rma))
1280
           (unit u-exec))))
1281
 
1282
(dnci sw16 "store word (16 bit displacement)" ((STALL STORE))
1283
     "sw $rnl,$sdisp16($rma)"
1284
     (+ MAJ_12 rnl rma (f-sub4 10) sdisp16)
1285
     (sequence ()
1286
               (c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3)))
1287
               (set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl))
1288
     ((mep (unit u-use-gpr (in usereg rnl))
1289
           (unit u-use-gpr (in usereg rma))
1290
           (unit u-exec))))
1291
 
1292
(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1293
     "lb $rnc,$sdisp16($rma)"
1294
     (+ MAJ_12 rnc rma (f-sub4 12) sdisp16)
1295
     (set rnc (ext SI (mem QI (add rma (ext SI sdisp16)))))
1296
     ((mep (unit u-use-gpr (in usereg rma))
1297
           (unit u-exec)
1298
           (unit u-load-gpr (out loadreg rnc)))))
1299
 
1300
(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1301
     "lh $rns,$sdisp16($rma)"
1302
     (+ MAJ_12 rns rma (f-sub4 13) sdisp16)
1303
     (set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
1304
     ((mep (unit u-use-gpr (in usereg rma))
1305
           (unit u-exec)
1306
           (unit u-load-gpr (out loadreg rns)))))
1307
 
1308
(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1309
     "lw $rnl,$sdisp16($rma)"
1310
     (+ MAJ_12 rnl rma (f-sub4 14) sdisp16)
1311
     (set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3))))
1312
     ((mep (unit u-use-gpr (in usereg rma))
1313
           (unit u-exec)
1314
           (unit u-load-gpr (out loadreg rnl)))))
1315
 
1316
(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1317
     "lbu $rnuc,$sdisp16($rma)"
1318
     (+ MAJ_12 rnuc rma (f-sub4 11) sdisp16)
1319
     (set rnuc (zext SI (mem QI (add rma (ext SI sdisp16)))))
1320
     ((mep (unit u-use-gpr (in usereg rma))
1321
           (unit u-exec)
1322
           (unit u-load-gpr (out loadreg rnuc)))))
1323
 
1324
(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1325
     "lhu $rnus,$sdisp16($rma)"
1326
     (+ MAJ_12 rnus rma (f-sub4 15) sdisp16)
1327
     (set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
1328
     ((mep (unit u-use-gpr (in usereg rma))
1329
           (unit u-exec)
1330
           (unit u-load-gpr (out loadreg rnus)))))
1331
 
1332
(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE))
1333
     "sw $rnl,($addr24a4)"
1334
     (+ MAJ_14 rnl addr24a4 (f-sub2 2))
1335
     (sequence ()
1336
               (c-call VOID "check_write_to_text" (zext SI addr24a4))
1337
               (set (mem SI (zext SI addr24a4)) rnl))
1338
     ((mep (unit u-use-gpr (in usereg rnl))
1339
           (unit u-exec))))
1340
 
1341
(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2))
1342
     "lw $rnl,($addr24a4)"
1343
     (+ MAJ_14 rnl addr24a4 (f-sub2 3))
1344
     (set rnl (mem SI (zext SI addr24a4)))
1345
     ((mep (unit u-exec)
1346
           (unit u-load-gpr (out loadreg rnl)))))
1347
 
1348
 
1349
; Extension instructions.
1350
 
1351
(dnci extb "sign extend byte" ()
1352
     "extb $rn"
1353
     (+ MAJ_1 rn (f-rm 0) (f-sub4 13))
1354
     (set rn (ext SI (and QI rn #xff)))
1355
     ((mep (unit u-use-gpr (in usereg rn))
1356
           (unit u-exec))))
1357
 
1358
(dnci exth "sign extend half-word" ()
1359
     "exth $rn"
1360
     (+ MAJ_1 rn (f-rm 2) (f-sub4 13))
1361
     (set rn (ext SI (and HI rn #xffff)))
1362
     ((mep (unit u-use-gpr (in usereg rn))
1363
           (unit u-exec))))
1364
 
1365
(dnci extub "zero extend byte" ()
1366
     "extub $rn"
1367
     (+ MAJ_1 rn (f-rm 8) (f-sub4 13))
1368
     (set rn (zext SI (and rn #xff)))
1369
     ((mep (unit u-use-gpr (in usereg rn))
1370
           (unit u-exec))))
1371
 
1372
(dnci extuh "zero extend half-word" ()
1373
     "extuh $rn"
1374
     (+ MAJ_1 rn (f-rm 10) (f-sub4 13))
1375
     (set rn (zext SI (and rn #xffff)))
1376
     ((mep (unit u-use-gpr (in usereg rn))
1377
           (unit u-exec))))
1378
 
1379
 
1380
; Shift amount manipulation instructions.
1381
 
1382
(dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE)
1383
     "ssarb $udisp2($rm)"
1384
     (+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12))
1385
     (if (c-call BI "big_endian_p")
1386
         (set sar (zext SI (mul (and (add udisp2 rm) 3) 8)))
1387
         (set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8)))))
1388
     ((mep (unit u-use-gpr (in usereg rm))
1389
           (unit u-exec))))
1390
 
1391
 
1392
; Move instructions.
1393
 
1394
(dnci mov "move" ()
1395
     "mov $rn,$rm"
1396
     (+ MAJ_0 rn rm (f-sub4 0))
1397
     (set rn rm)
1398
     ((mep (unit u-use-gpr (in usereg rm))
1399
           (unit u-exec))))
1400
 
1401
(dnci movi8 "move 8-bit immediate" ()
1402
     "mov $rn,$simm8"
1403
     (+ MAJ_5 rn simm8)
1404
     (set rn (ext SI simm8))
1405
     ())
1406
 
1407
(dnci movi16 "move 16-bit immediate" ()
1408
     "mov $rn,$simm16"
1409
     (+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16)
1410
     (set rn (ext SI simm16))
1411
     ())
1412
 
1413
(dnci movu24 "move 24-bit unsigned immediate" ()
1414
     "movu $rn3,$uimm24"
1415
     (+ MAJ_13 (f-4 0) rn3 uimm24)
1416
     (set rn3 (zext SI uimm24))
1417
     ())
1418
 
1419
(dnci movu16 "move 16-bit unsigned immediate" ()
1420
     "movu $rn,$uimm16"
1421
     (+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16)
1422
     (set rn (zext SI uimm16))
1423
     ())
1424
 
1425
(dnci movh "move high 16-bit immediate" ()
1426
     "movh $rn,$uimm16"
1427
     (+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16)
1428
     (set rn (sll uimm16 16))
1429
     ())
1430
 
1431
 
1432
; Arithmetic instructions.
1433
 
1434
(dnci add3 "add three registers" ()
1435
     "add3 $rl,$rn,$rm"
1436
     (+ MAJ_9 rn rm rl)
1437
     (set rl (add rn rm))
1438
     ((mep (unit u-use-gpr (in usereg rn))
1439
           (unit u-use-gpr (in usereg rm))
1440
           (unit u-exec))))
1441
 
1442
(dnci add "add" ()
1443
     "add $rn,$simm6"
1444
     (+ MAJ_6 rn simm6 (f-sub2 0))
1445
     (set rn (add rn (ext SI simm6)))
1446
     ((mep (unit u-use-gpr (in usereg rn))
1447
           (unit u-exec))))
1448
 
1449
(dnci add3i "add two registers and immediate" ()
1450
     "add3 $rn,$spr,$uimm7a4"
1451
     (+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0))
1452
     (set rn (add sp (zext SI uimm7a4)))
1453
     ((mep (unit u-use-gpr (in usereg sp))
1454
           (unit u-exec))))
1455
 
1456
(dnci advck3 "add overflow check" ((STALL ADVCK))
1457
     "advck3 \\$0,$rn,$rm"
1458
     (+ MAJ_0 rn rm (f-sub4 7))
1459
     (if (add-oflag rn rm 0)
1460
         (set r0 1)
1461
         (set r0 0))
1462
     ((mep (unit u-use-gpr (in usereg rn))
1463
           (unit u-use-gpr (in usereg rm))
1464
           (unit u-exec))))
1465
 
1466
(dnci sub "subtract" ()
1467
     "sub $rn,$rm"
1468
     (+ MAJ_0 rn rm (f-sub4 4))
1469
     (set rn (sub rn rm))
1470
     ((mep (unit u-use-gpr (in usereg rn))
1471
           (unit u-use-gpr (in usereg rm)))))
1472
 
1473
(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK))
1474
     "sbvck3 \\$0,$rn,$rm"
1475
     (+ MAJ_0 rn rm (f-sub4 5))
1476
     (if (sub-oflag rn rm 0)
1477
         (set r0 1)
1478
         (set r0 0))
1479
     ((mep (unit u-use-gpr (in usereg rn))
1480
           (unit u-use-gpr (in usereg rm))
1481
           (unit u-exec))))
1482
 
1483
(dnci neg "negate" ()
1484
     "neg $rn,$rm"
1485
     (+ MAJ_0 rn rm (f-sub4 1))
1486
     (set rn (neg rm))
1487
     ((mep (unit u-use-gpr (in usereg rm))
1488
           (unit u-exec))))
1489
 
1490
(dnci slt3 "set if less than" ()
1491
     "slt3 \\$0,$rn,$rm"
1492
     (+ MAJ_0 rn rm (f-sub4 2))
1493
     (if (lt rn rm)
1494
         (set r0 1)
1495
         (set r0 0))
1496
     ((mep (unit u-use-gpr (in usereg rn))
1497
           (unit u-use-gpr (in usereg rm))
1498
           (unit u-exec))))
1499
 
1500
(dnci sltu3 "set less than unsigned" ()
1501
     "sltu3 \\$0,$rn,$rm"
1502
     (+ MAJ_0 rn rm (f-sub4 3))
1503
     (if (ltu rn rm)
1504
         (set r0 1)
1505
         (set r0 0))
1506
     ((mep (unit u-use-gpr (in usereg rn))
1507
           (unit u-use-gpr (in usereg rm))
1508
           (unit u-exec))))
1509
 
1510
(dnci slt3i "set if less than immediate" ()
1511
     "slt3 \\$0,$rn,$uimm5"
1512
     (+ MAJ_6 rn uimm5 (f-sub3 1))
1513
     (if (lt rn (zext SI uimm5))
1514
         (set r0 1)
1515
         (set r0 0))
1516
     ((mep (unit u-use-gpr (in usereg rn))
1517
           (unit u-exec))))
1518
 
1519
(dnci sltu3i "set if less than unsigned immediate" ()
1520
     "sltu3 \\$0,$rn,$uimm5"
1521
     (+ MAJ_6 rn uimm5 (f-sub3 5))
1522
     (if (ltu rn (zext SI uimm5))
1523
         (set r0 1)
1524
         (set r0 0))
1525
     ())
1526
 
1527
(dnci sl1ad3 "shift left one and add" ((STALL INT2))
1528
     "sl1ad3 \\$0,$rn,$rm"
1529
     (+ MAJ_2 rn rm (f-sub4 6))
1530
     (set r0 (add (sll rn 1) rm))
1531
     ((mep (unit u-use-gpr (in usereg rn))
1532
           (unit u-use-gpr (in usereg rm))
1533
           (unit u-exec))))
1534
 
1535
(dnci sl2ad3 "shift left two and add" ((STALL INT2))
1536
     "sl2ad3 \\$0,$rn,$rm"
1537
     (+ MAJ_2 rn rm (f-sub4 7))
1538
     (set r0 (add (sll rn 2) rm))
1539
     ((mep (unit u-use-gpr (in usereg rn))
1540
           (unit u-use-gpr (in usereg rm))
1541
           (unit u-exec))))
1542
 
1543
(dnci add3x "three operand add (extended)" ()
1544
     "add3 $rn,$rm,$simm16"
1545
     (+ MAJ_12 rn rm (f-sub4 0) simm16)
1546
     (set rn (add rm (ext SI simm16)))
1547
     ((mep (unit u-use-gpr (in usereg rm))
1548
           (unit u-exec))))
1549
 
1550
(dnci slt3x "set if less than (extended)" ()
1551
     "slt3 $rn,$rm,$simm16"
1552
     (+ MAJ_12 rn rm (f-sub4 2) simm16)
1553
     (if (lt rm (ext SI simm16))
1554
         (set rn 1)
1555
         (set rn 0))
1556
     ((mep (unit u-use-gpr (in usereg rm))
1557
           (unit u-exec))))
1558
 
1559
(dnci sltu3x "set if less than unsigned (extended)" ()
1560
     "sltu3 $rn,$rm,$uimm16"
1561
     (+ MAJ_12 rn rm (f-sub4 3) uimm16)
1562
     (if (ltu rm (zext SI uimm16))
1563
         (set rn 1)
1564
         (set rn 0))
1565
     ((mep (unit u-use-gpr (in usereg rm))
1566
           (unit u-exec))))
1567
 
1568
 
1569
; Logical instructions.
1570
 
1571
(dnci or "bitwise or" ()
1572
     "or $rn,$rm"
1573
     (+ MAJ_1 rn rm (f-sub4 0))
1574
     (set rn (or rn rm))
1575
     ((mep (unit u-use-gpr (in usereg rn))
1576
           (unit u-use-gpr (in usereg rm))
1577
           (unit u-exec))))
1578
 
1579
(dnci and "bitwise and" ()
1580
     "and $rn,$rm"
1581
     (+ MAJ_1 rn rm (f-sub4 1))
1582
     (set rn (and rn rm))
1583
     ((mep (unit u-use-gpr (in usereg rn))
1584
           (unit u-use-gpr (in usereg rm))
1585
           (unit u-exec))))
1586
 
1587
(dnci xor "bitwise exclusive or" ()
1588
     "xor $rn,$rm"
1589
     (+ MAJ_1 rn rm (f-sub4 2))
1590
     (set rn (xor rn rm))
1591
     ((mep (unit u-use-gpr (in usereg rn))
1592
           (unit u-use-gpr (in usereg rm))
1593
           (unit u-exec))))
1594
 
1595
(dnci nor "bitwise negated or" ()
1596
     "nor $rn,$rm"
1597
     (+ MAJ_1 rn rm (f-sub4 3))
1598
     (set rn (inv (or rn rm)))
1599
     ((mep (unit u-use-gpr (in usereg rn))
1600
           (unit u-use-gpr (in usereg rm))
1601
           (unit u-exec))))
1602
 
1603
(dnci or3 "or three operand" ()
1604
     "or3 $rn,$rm,$uimm16"
1605
     (+ MAJ_12 rn rm (f-sub4 4) uimm16)
1606
     (set rn (or rm (zext SI uimm16)))
1607
     ((mep (unit u-use-gpr (in usereg rm))
1608
           (unit u-exec))))
1609
 
1610
(dnci and3 "and three operand" ()
1611
     "and3 $rn,$rm,$uimm16"
1612
     (+ MAJ_12 rn rm (f-sub4 5) uimm16)
1613
     (set rn (and rm (zext SI uimm16)))
1614
     ((mep (unit u-use-gpr (in usereg rm))
1615
           (unit u-exec))))
1616
 
1617
(dnci xor3 "exclusive or three operand" ()
1618
     "xor3 $rn,$rm,$uimm16"
1619
     (+ MAJ_12 rn rm (f-sub4 6) uimm16)
1620
     (set rn (xor rm (zext SI uimm16)))
1621
     ((mep (unit u-use-gpr (in usereg rm))
1622
           (unit u-exec))))
1623
 
1624
 
1625
; Shift instructions.
1626
 
1627
(dnci sra "shift right arithmetic" ((STALL INT2))
1628
     "sra $rn,$rm"
1629
     (+ MAJ_2 rn rm (f-sub4 13))
1630
     (set rn (sra rn (and rm #x1f)))
1631
     ((mep (unit u-use-gpr (in usereg rn))
1632
           (unit u-use-gpr (in usereg rm))
1633
           (unit u-exec))))
1634
 
1635
(dnci srl "shift right logical" ((STALL INT2))
1636
     "srl $rn,$rm"
1637
     (+ MAJ_2 rn rm (f-sub4 12))
1638
     (set rn (srl rn (and rm #x1f)))
1639
     ((mep (unit u-use-gpr (in usereg rn))
1640
           (unit u-use-gpr (in usereg rm))
1641
           (unit u-exec))))
1642
 
1643
(dnci sll "shift left logical" ((STALL INT2))
1644
     "sll $rn,$rm"
1645
     (+ MAJ_2 rn rm (f-sub4 14))
1646
     (set rn (sll rn (and rm #x1f)))
1647
     ((mep (unit u-use-gpr (in usereg rn))
1648
           (unit u-use-gpr (in usereg rm))
1649
           (unit u-exec))))
1650
 
1651
(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI))
1652
     "sra $rn,$uimm5"
1653
     (+ MAJ_6 rn uimm5 (f-sub3 3))
1654
     (set rn (sra rn uimm5))
1655
     ((mep (unit u-use-gpr (in usereg rn))
1656
           (unit u-exec))))
1657
 
1658
(dnci srli "shift right logical (immediate)" ((STALL SHIFTI))
1659
     "srl $rn,$uimm5"
1660
     (+ MAJ_6 rn uimm5 (f-sub3 2))
1661
     (set rn (srl rn uimm5))
1662
     ((mep (unit u-use-gpr (in usereg rn))
1663
           (unit u-exec))))
1664
 
1665
(dnci slli "shift left logical (immediate)" ((STALL SHIFTI))
1666
     "sll $rn,$uimm5"
1667
     (+ MAJ_6 rn uimm5 (f-sub3 6))
1668
     (set rn (sll rn uimm5))
1669
     ((mep (unit u-use-gpr (in usereg rn))
1670
           (unit u-exec))))
1671
 
1672
(dnci sll3 "three-register shift left logical" ((STALL INT2))
1673
     "sll3 \\$0,$rn,$uimm5"
1674
     (+ MAJ_6 rn uimm5 (f-sub3 7))
1675
     (set r0 (sll rn uimm5))
1676
     ((mep (unit u-use-gpr (in usereg rn))
1677
           (unit u-exec))))
1678
 
1679
(dnci fsft "field shift" ((STALL FSFT) VOLATILE)
1680
     "fsft $rn,$rm"
1681
     (+ MAJ_2 rn rm (f-sub4 15))
1682
     (sequence ((DI temp) (QI shamt))
1683
               (set shamt (and sar #x3f))
1684
               (set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt))
1685
               (set rn (subword SI (srl temp 32) 1)))
1686
     ((mep (unit u-use-gpr (in usereg rn))
1687
           (unit u-use-gpr (in usereg rm))
1688
           (unit u-exec))))
1689
 
1690
 
1691
; Branch/jump instructions.
1692
 
1693
(dnci bra "branch" (RELAXABLE)
1694
     "bra $pcrel12a2"
1695
     (+ MAJ_11 pcrel12a2 (f-15 0))
1696
     (set-vliw-alignment-modified pc pcrel12a2)
1697
     ((mep (unit u-branch)
1698
           (unit u-exec))))
1699
 
1700
(dnci beqz "branch if equal zero" (RELAXABLE)
1701
     "beqz $rn,$pcrel8a2"
1702
     (+ MAJ_10 rn pcrel8a2 (f-15 0))
1703
     (if (eq rn 0)
1704
         (set-vliw-alignment-modified pc pcrel8a2))
1705
     ((mep (unit u-use-gpr (in usereg rn))
1706
           (unit u-exec)
1707
           (unit u-branch))))
1708
 
1709
(dnci bnez "branch if not equal zero" (RELAXABLE)
1710
     "bnez $rn,$pcrel8a2"
1711
     (+ MAJ_10 rn pcrel8a2 (f-15 1))
1712
     (if (ne rn 0)
1713
         (set-vliw-alignment-modified pc pcrel8a2))
1714
     ((mep (unit u-use-gpr (in usereg rn))
1715
           (unit u-exec)
1716
           (unit u-branch))))
1717
 
1718
(dnci beqi "branch equal immediate" (RELAXABLE)
1719
     "beqi $rn,$uimm4,$pcrel17a2"
1720
     (+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2)
1721
     (if (eq rn (zext SI uimm4))
1722
         (set-vliw-alignment-modified pc pcrel17a2))
1723
     ((mep (unit u-use-gpr (in usereg rn))
1724
           (unit u-exec)
1725
           (unit u-branch))))
1726
 
1727
(dnci bnei "branch not equal immediate" (RELAXABLE)
1728
     "bnei $rn,$uimm4,$pcrel17a2"
1729
     (+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2)
1730
     (if (ne rn (zext SI uimm4))
1731
         (set-vliw-alignment-modified pc pcrel17a2))
1732
     ((mep (unit u-use-gpr (in usereg rn))
1733
           (unit u-exec)
1734
           (unit u-branch))))
1735
 
1736
(dnci blti "branch less than immediate" (RELAXABLE)
1737
     "blti $rn,$uimm4,$pcrel17a2"
1738
     (+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2)
1739
     (if (lt rn (zext SI uimm4))
1740
         (set-vliw-alignment-modified pc pcrel17a2))
1741
     ((mep (unit u-use-gpr (in usereg rn))
1742
           (unit u-exec)
1743
           (unit u-branch))))
1744
 
1745
(dnci bgei "branch greater than immediate" (RELAXABLE)
1746
     "bgei $rn,$uimm4,$pcrel17a2"
1747
     (+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2)
1748
     (if (ge rn (zext SI uimm4))
1749
         (set-vliw-alignment-modified pc pcrel17a2))
1750
     ((mep (unit u-use-gpr (in usereg rn))
1751
           (unit u-exec)
1752
           (unit u-branch))))
1753
 
1754
(dnci beq "branch equal" ()
1755
     "beq $rn,$rm,$pcrel17a2"
1756
     (+ MAJ_14 rn rm (f-sub4 1) pcrel17a2)
1757
     (if (eq rn rm)
1758
         (set-vliw-alignment-modified pc pcrel17a2))
1759
     ((mep (unit u-use-gpr (in usereg rn))
1760
           (unit u-use-gpr (in usereg rm))
1761
           (unit u-exec)
1762
           (unit u-branch))))
1763
 
1764
(dnci bne "branch not equal" ()
1765
     "bne $rn,$rm,$pcrel17a2"
1766
     (+ MAJ_14 rn rm (f-sub4 5) pcrel17a2)
1767
     (if (ne rn rm)
1768
         (set-vliw-alignment-modified pc pcrel17a2))
1769
     ((mep (unit u-use-gpr (in usereg rn))
1770
           (unit u-use-gpr (in usereg rm))
1771
           (unit u-exec)
1772
           (unit u-branch))))
1773
 
1774
(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE)
1775
     "bsr $pcrel12a2"
1776
     (+ MAJ_11 pcrel12a2 (f-15 1))
1777
     (sequence ()
1778
               (cg-profile pc pcrel12a2)
1779
               (set-vliw-modified-pcrel-offset lp 2 4 8)
1780
               (set-vliw-alignment-modified pc pcrel12a2))
1781
     ((mep (unit u-exec)
1782
           (unit u-branch))))
1783
 
1784
(dnci bsr24 "branch to subroutine (24 bit displacement)" ()
1785
     "bsr $pcrel24a2"
1786
     (+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2)
1787
     (sequence ()
1788
               (cg-profile pc pcrel24a2)
1789
               (set-vliw-modified-pcrel-offset lp 4 4 8)
1790
               (set-vliw-alignment-modified pc pcrel24a2))
1791
     ((mep (unit u-exec)
1792
           (unit u-branch))))
1793
 
1794
(dnci jmp "jump" ()
1795
     "jmp $rm"
1796
     (+ MAJ_1 (f-rn 0) rm (f-sub4 14))
1797
     (sequence ()
1798
               (if (eq (get-psw.om) 0)
1799
                   ;; core mode
1800
                   (if (get-rm.lsb)
1801
                       (sequence ()
1802
                                 (set-psw.om 1) ;; enter VLIW mode
1803
                                 (set-vliw-aliignment-modified-by-option pc rm))
1804
                       (set pc (and rm (inv 1))))
1805
                   ;; VLIW mode
1806
                   (if (get-rm.lsb)
1807
                       (sequence ()
1808
                                 (set-psw.om 0) ;; enter core mode
1809
                                 (set pc (and rm (inv 1))))
1810
                       (set-vliw-aliignment-modified-by-option pc rm)))
1811
               (cg-profile-jump pc rm))
1812
     ((mep (unit u-use-gpr (in usereg rm))
1813
           (unit u-exec)
1814
           (unit u-branch))))
1815
 
1816
(dnci jmp24 "jump (24 bit target)" ()
1817
     "jmp $pcabs24a2"
1818
     (+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2)
1819
     (sequence ()
1820
               (set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2))
1821
               (cg-profile-jump pc pcabs24a2))
1822
     ((mep (unit u-exec)
1823
           (unit u-branch))))
1824
 
1825
(dnci jsr "jump to subroutine" ()
1826
     "jsr $rm"
1827
     (+ MAJ_1 (f-rn 0) rm (f-sub4 15))
1828
     (sequence ()
1829
               (cg-profile pc rm)
1830
               (set-vliw-modified-pcrel-offset lp 2 4 8)
1831
               (set-vliw-alignment-modified pc rm))
1832
     ((mep (unit u-use-gpr (in usereg rm))
1833
           (unit u-exec)
1834
           (unit u-branch))))
1835
 
1836
(dnci ret "return from subroutine" ((STALL RET))
1837
     "ret"
1838
     (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2))
1839
     (sequence ()
1840
               (if (eq (get-psw.om) 0)
1841
                   ;; core mode
1842
                   (if (get-lp.ltom) ;; link-pointer "toggle mode" bit
1843
                       (sequence ()
1844
                                 (set-psw.om 1) ;; enter VLIW mode
1845
                                 (set-vliw-aliignment-modified-by-option pc lp))
1846
                       (set pc (and lp (inv 1))))
1847
                   ;; VLIW mode
1848
                   (if (get-lp.ltom) ;; link-pointer "toggle mode" bit
1849
                       (sequence ()
1850
                                 (set-psw.om 0) ;; enter VLIW mode
1851
                                 (set pc (and lp (inv 1))))
1852
                       (set-vliw-aliignment-modified-by-option pc lp)))
1853
               (c-call VOID "notify_ret" pc))
1854
     ((mep (unit u-exec)
1855
           (unit u-branch))))
1856
 
1857
 
1858
; Repeat instructions.
1859
 
1860
(dnci repeat "repeat specified repeat block" ()
1861
     "repeat $rn,$pcrel17a2"
1862
     (+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2)
1863
     (sequence ()
1864
               (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
1865
               (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
1866
               (set (reg h-csr 6) rn))
1867
     ((mep (unit u-use-gpr (in usereg rn))
1868
           (unit u-exec))))
1869
 
1870
(dnci erepeat "endless repeat" ()
1871
     "erepeat $pcrel17a2"
1872
     (+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2)
1873
     (sequence ()
1874
               (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
1875
               (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
1876
               (set-rpe.elr 1)
1877
               ; rpc may be undefined for erepeat
1878
               ; use 1 to trigger repeat logic in the sim's main loop
1879
               (set (reg h-csr 6) 1))
1880
     ())
1881
 
1882
 
1883
; Control instructions.
1884
 
1885
;; special store variants
1886
 
1887
(dnci stc_lp "store to control register lp" ((STALL STC))
1888
      "stc $rn,\\$lp"
1889
      (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
1890
      (set lp rn)
1891
      ((mep (unit u-use-gpr (in usereg rn))
1892
            (unit u-store-ctrl-reg (out storereg lp))
1893
            (unit u-exec))))
1894
 
1895
(dnci stc_hi "store to control register hi" ((STALL STC))
1896
      "stc $rn,\\$hi"
1897
      (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
1898
      (set hi rn)
1899
      ((mep (unit u-use-gpr (in usereg rn))
1900
            (unit u-store-ctrl-reg (out storereg hi))
1901
            (unit u-exec))))
1902
 
1903
(dnci stc_lo "store to control register lo" ((STALL STC))
1904
      "stc $rn,\\$lo"
1905
      (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
1906
      (set lo rn)
1907
      ((mep (unit u-use-gpr (in usereg rn))
1908
            (unit u-store-ctrl-reg (out storereg lo))
1909
            (unit u-exec))))
1910
 
1911
;; general store
1912
 
1913
(dnci stc "store to control register" (VOLATILE (STALL STC))
1914
     "stc $rn,$csrn"
1915
     (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0))
1916
     (set csrn rn)
1917
     ((mep (unit u-use-gpr (in usereg rn))
1918
           (unit u-store-ctrl-reg (out storereg csrn))
1919
           (unit u-exec))))
1920
 
1921
;; special load variants
1922
 
1923
(dnci ldc_lp "load from control register lp" ((STALL LDC))
1924
      "ldc $rn,\\$lp"
1925
      (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
1926
      (set rn lp)
1927
      ((mep (unit u-use-ctrl-reg (in usereg lp))
1928
            (unit u-exec)
1929
            (unit u-load-gpr (out loadreg rn)))))
1930
 
1931
 
1932
(dnci ldc_hi "load from control register hi" ((STALL LDC))
1933
      "ldc $rn,\\$hi"
1934
      (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
1935
      (set rn hi)
1936
      ((mep (unit u-use-ctrl-reg (in usereg hi))
1937
            (unit u-exec)
1938
            (unit u-load-gpr (out loadreg rn)))))
1939
 
1940
(dnci ldc_lo "load from control register lo" ((STALL LDC))
1941
      "ldc $rn,\\$lo"
1942
      (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
1943
      (set rn lo)
1944
      ((mep (unit u-use-ctrl-reg (in usereg lo))
1945
            (unit u-exec)
1946
            (unit u-load-gpr (out loadreg rn)))))
1947
 
1948
;; general load
1949
 
1950
(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2))
1951
     "ldc $rn,$csrn"
1952
     (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1))
1953
     (if (eq (ifield f-csrn) 0)
1954
         ;; loading from the pc
1955
         (set-vliw-modified-pcrel-offset rn 2 4 8)
1956
         ;; loading from something else
1957
         (set rn csrn))
1958
      ((mep (unit u-use-ctrl-reg (in usereg csrn))
1959
            (unit u-exec)
1960
            (unit u-load-gpr (out loadreg rn)))))
1961
 
1962
(dnci di "disable interrupt" (VOLATILE)
1963
     "di"
1964
     (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0))
1965
     ; clear psw.iec
1966
     (set psw (sll (srl psw 1) 1))
1967
     ())
1968
 
1969
(dnci ei "enable interrupt" (VOLATILE)
1970
     "ei"
1971
     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0))
1972
     ; set psw.iec
1973
     (set psw (or psw 1))
1974
     ())
1975
 
1976
(dnci reti "return from interrupt" ((STALL RET))
1977
     "reti"
1978
     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2))
1979
     (if (eq (get-psw.om) 0)
1980
         ;; core operation mode
1981
         (if (get-psw.nmi)
1982
             ;; return from NMI
1983
             (if (get-npc.ntom)
1984
                 ;; return in VLIW operation mode
1985
                 (sequence ()
1986
                           (set-psw.om 1)
1987
                           (set-vliw-aliignment-modified-by-option pc npc)
1988
                           (set-psw.nmi 0))
1989
                 ;; return in core mode
1990
                 (sequence ()
1991
                           (set pc (and npc (inv 1)))
1992
                           (set-psw.nmi 0)))
1993
             ;; return from non-NMI
1994
             (if (get-epc.etom)
1995
                 ;; return in VLIW mode
1996
                 (sequence ()
1997
                           (set-psw.om 1)
1998
                           (set-vliw-aliignment-modified-by-option pc epc)
1999
                           (set-psw.umc (get-psw.ump))
2000
                           (set-psw.iec (get-psw.iep)))
2001
                 ;; return in core mode
2002
                 (sequence ()
2003
                           (set pc (and epc (inv 1)))
2004
                           (set-psw.umc (get-psw.ump))
2005
                           (set-psw.iec (get-psw.iep)))))
2006
         ;; VLIW operation mode
2007
         ;; xxx undefined
2008
         (nop))
2009
     ((mep (unit u-exec)
2010
           (unit u-branch))))
2011
 
2012
(dnci halt "halt pipeline" (VOLATILE)
2013
     "halt"
2014
     (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2))
2015
     ; set psw.halt
2016
     (set (raw-reg h-csr 16) (or psw (sll 1 11)))
2017
     ())
2018
 
2019
(dnci sleep "sleep pipeline" (VOLATILE)
2020
     "sleep"
2021
     (+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2))
2022
     (c-call VOID "do_sleep")
2023
     ())
2024
 
2025
(dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2026
     "swi $uimm2"
2027
     (+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6))
2028
     (cond
2029
      ((eq uimm2 0) (set exc (or exc (sll 1 4))))
2030
      ((eq uimm2 1) (set exc (or exc (sll 1 5))))
2031
      ((eq uimm2 2) (set exc (or exc (sll 1 6))))
2032
      ((eq uimm2 3) (set exc (or exc (sll 1 7)))))
2033
     ())
2034
 
2035
(dnci break "break exception" (MAY_TRAP VOLATILE)
2036
     "break"
2037
     (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2))
2038
     (set pc (c-call USI "break_exception" pc))
2039
     ((mep (unit u-exec)
2040
           (unit u-branch))))
2041
 
2042
(dnci syncm "synchronise with memory" (VOLATILE)
2043
     "syncm"
2044
     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1))
2045
     (unimp "syncm")
2046
     ())
2047
 
2048
(dnci stcb "store in control bus space" (VOLATILE (STALL STCB))
2049
     "stcb $rn,$uimm16"
2050
     (+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16)
2051
     (c-call VOID "do_stcb" rn uimm16)
2052
     ((mep (unit u-use-gpr (in usereg rn))
2053
           (unit u-exec)
2054
           (unit u-stcb))))
2055
 
2056
(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3))
2057
     "ldcb $rn,$uimm16"
2058
     (+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16)
2059
     (set rn (c-call SI "do_ldcb" uimm16))
2060
      ((mep (unit u-ldcb)
2061
            (unit u-exec)
2062
            (unit u-ldcb-gpr (out loadreg rn)))))
2063
 
2064
 
2065
; Bit manipulation instructions.
2066
; The following instructions become the reserved instruction when the
2067
; bit manipulation option is off.
2068
 
2069
(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN)
2070
     "bsetm ($rma),$uimm3"
2071
     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0))
2072
     (sequence ()
2073
               (c-call "check_option_bit" pc)
2074
               (set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3))))
2075
     ((mep (unit u-use-gpr (in usereg rma))
2076
           (unit u-exec))))
2077
 
2078
(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN)
2079
     "bclrm ($rma),$uimm3"
2080
     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1))
2081
     (sequence ()
2082
               (c-call "check_option_bit" pc)
2083
               (set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3)))))
2084
     ((mep (unit u-use-gpr (in usereg rma))
2085
           (unit u-exec))))
2086
 
2087
(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN)
2088
     "bnotm ($rma),$uimm3"
2089
     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2))
2090
     (sequence ()
2091
               (c-call "check_option_bit" pc)
2092
               (set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3))))
2093
     ((mep (unit u-use-gpr (in usereg rma))
2094
           (unit u-exec))))
2095
 
2096
(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN)
2097
     "btstm \\$0,($rma),$uimm3"
2098
     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3))
2099
     (sequence ()
2100
               (c-call "check_option_bit" pc)
2101
               (set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3)))))
2102
     ((mep (unit u-use-gpr (in usereg rma))
2103
           (unit u-exec))))
2104
 
2105
(dnci tas "test and set" (OPTIONAL_BIT_INSN)
2106
     "tas $rn,($rma)"
2107
     (+ MAJ_2 rn rma (f-sub4 4))
2108
     (sequence ((SI result))
2109
               (c-call "check_option_bit" pc)
2110
               (set result (zext SI (mem UQI rma)))
2111
               (set (mem UQI rma) 1)
2112
               (set rn result))
2113
     ((mep (unit u-use-gpr (in usereg rma))
2114
           (unit u-exec))))
2115
 
2116
 
2117
; Data cache instruction.
2118
 
2119
(dnci cache "cache operations" (VOLATILE)
2120
     "cache $cimm4,($rma)"
2121
     (+ MAJ_7 cimm4 rma (f-sub4 4))
2122
     (c-call VOID "do_cache" cimm4 rma pc)
2123
     ((mep (unit u-use-gpr (in usereg rma))
2124
           (unit u-exec))))
2125
 
2126
 
2127
; Multiply instructions.
2128
; These instructions become the RI when the 32-bit multiply
2129
; instruction option is off.
2130
 
2131
(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL))
2132
     "mul $rn,$rm"
2133
     (+ MAJ_1 rn rm (f-sub4 4))
2134
     (sequence ((DI result))
2135
               (c-call "check_option_mul" pc)
2136
               (set result (mul (ext DI rn) (ext DI rm)))
2137
               (set hi (subword SI result 0))
2138
               (set lo (subword SI result 1)))
2139
     ((mep (unit u-use-gpr (in usereg rn))
2140
           (unit u-use-gpr (in usereg rm))
2141
           (unit u-exec)
2142
           (unit u-multiply))))
2143
 
2144
(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
2145
     "mulu $rn,$rm"
2146
     (+ MAJ_1 rn rm (f-sub4 5))
2147
     (sequence ((DI result))
2148
               (c-call "check_option_mul" pc)
2149
               (set result (mul (zext UDI rn) (zext UDI rm)))
2150
               (set hi (subword SI result 0))
2151
               (set lo (subword SI result 1)))
2152
     ((mep (unit u-use-gpr (in usereg rn))
2153
           (unit u-use-gpr (in usereg rm))
2154
           (unit u-exec)
2155
           (unit u-multiply))))
2156
 
2157
(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2158
     "mulr $rn,$rm"
2159
     (+ MAJ_1 rn rm (f-sub4 6))
2160
     (sequence ((DI result))
2161
               (c-call "check_option_mul" pc)
2162
               (set result (mul (ext DI rn) (ext DI rm)))
2163
               (set hi (subword SI result 0))
2164
               (set lo (subword SI result 1))
2165
               (set rn (subword SI result 1)))
2166
     ((mep (unit u-use-gpr (in usereg rn))
2167
           (unit u-use-gpr (in usereg rm))
2168
           (unit u-exec)
2169
           (unit u-multiply)
2170
           (unit u-mul-gpr (out resultreg rn)))))
2171
 
2172
(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2173
     "mulru $rn,$rm"
2174
     (+ MAJ_1 rn rm (f-sub4 7))
2175
     (sequence ((DI result))
2176
               (c-call "check_option_mul" pc)
2177
               (set result (mul (zext UDI rn) (zext UDI rm)))
2178
               (set hi (subword SI result 0))
2179
               (set lo (subword SI result 1))
2180
               (set rn (subword SI result 1)))
2181
     ((mep (unit u-use-gpr (in usereg rn))
2182
           (unit u-use-gpr (in usereg rm))
2183
           (unit u-exec)
2184
           (unit u-multiply)
2185
           (unit u-mul-gpr (out resultreg rn)))))
2186
 
2187
(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL))
2188
     "madd $rn,$rm"
2189
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004))
2190
     (sequence ((DI result))
2191
               (c-call "check_option_mul" pc)
2192
               (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2193
               (set result (add result (mul (ext DI rn) (ext DI rm))))
2194
               (set hi (subword SI result 0))
2195
               (set lo (subword SI result 1)))
2196
     ((mep (unit u-use-gpr (in usereg rn))
2197
           (unit u-use-gpr (in usereg rm))
2198
           (unit u-exec)
2199
           (unit u-multiply))))
2200
 
2201
(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
2202
     "maddu $rn,$rm"
2203
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005))
2204
     (sequence ((DI result))
2205
               (c-call "check_option_mul" pc)
2206
               (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2207
               (set result (add result (mul (zext UDI rn) (zext UDI rm))))
2208
               (set hi (subword SI result 0))
2209
               (set lo (subword SI result 1)))
2210
     ((mep (unit u-use-gpr (in usereg rn))
2211
           (unit u-use-gpr (in usereg rm))
2212
           (unit u-exec)
2213
           (unit u-multiply))))
2214
 
2215
 
2216
(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2217
     "maddr $rn,$rm"
2218
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006))
2219
     (sequence ((DI result))
2220
               (c-call "check_option_mul" pc)
2221
               (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2222
               (set result (add result (mul (ext DI rn) (ext DI rm))))
2223
               (set hi (subword SI result 0))
2224
               (set lo (subword SI result 1))
2225
               (set rn (subword SI result 1)))
2226
     ((mep (unit u-use-gpr (in usereg rn))
2227
           (unit u-use-gpr (in usereg rm))
2228
           (unit u-exec)
2229
           (unit u-multiply)
2230
           (unit u-mul-gpr (out resultreg rn)))))
2231
 
2232
(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2233
     "maddru $rn,$rm"
2234
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007))
2235
     (sequence ((DI result))
2236
               (c-call "check_option_mul" pc)
2237
               (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2238
               (set result (add result (mul (zext UDI rn) (zext UDI rm))))
2239
               (set hi (subword SI result 0))
2240
               (set lo (subword SI result 1))
2241
               (set rn (subword SI result 1)))
2242
     ((mep (unit u-use-gpr (in usereg rn))
2243
           (unit u-use-gpr (in usereg rm))
2244
           (unit u-exec)
2245
           (unit u-multiply)
2246
           (unit u-mul-gpr (out resultreg rn)))))
2247
 
2248
 
2249
; Divide instructions.
2250
; These instructions become the RI when the 32-bit divide instruction
2251
; option is off.
2252
 
2253
(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
2254
     "div $rn,$rm"
2255
     (+ MAJ_1 rn rm (f-sub4 8))
2256
     (sequence ()
2257
               (c-call "check_option_div" pc)
2258
               (if (eq rm 0)
2259
                   (set pc (c-call USI "zdiv_exception" pc))
2260
                   ; Special case described on p. 76.
2261
                   (if (and (eq rn #x80000000)
2262
                            (eq rm #xffffffff))
2263
                       (sequence ()
2264
                                 (set lo #x80000000)
2265
                                 (set hi 0))
2266
                       (sequence ()
2267
                                 (set lo (div rn rm))
2268
                                 (set hi (mod rn rm))))))
2269
     ((mep (unit u-use-gpr (in usereg rn))
2270
           (unit u-use-gpr (in usereg rm))
2271
           (unit u-exec)
2272
           (unit u-divide)
2273
           (unit u-branch))))
2274
 
2275
(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
2276
     "divu $rn,$rm"
2277
     (+ MAJ_1 rn rm (f-sub4 9))
2278
     (sequence ()
2279
               (c-call "check_option_div" pc)
2280
               (if (eq rm 0)
2281
                   (set pc (c-call USI "zdiv_exception" pc))
2282
                   (sequence ()
2283
                             (set lo (udiv rn rm))
2284
                             (set hi (umod rn rm)))))
2285
     ((mep (unit u-use-gpr (in usereg rn))
2286
           (unit u-use-gpr (in usereg rm))
2287
           (unit u-exec)
2288
           (unit u-divide)
2289
           (unit u-branch))))
2290
 
2291
 
2292
; Debug functions.
2293
; These instructions become the RI when the debug function option is
2294
; off.
2295
 
2296
(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN)
2297
     "dret"
2298
     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3))
2299
     (sequence ()
2300
               (c-call "check_option_debug" pc)
2301
               ; set DBG.DM.
2302
               (set dbg (and dbg (inv (sll SI 1 15))))
2303
               (set pc depc))
2304
     ((mep (unit u-exec)
2305
           (unit u-branch))))
2306
 
2307
(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE)
2308
     "dbreak"
2309
     (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3))
2310
     (sequence ()
2311
               (c-call "check_option_debug" pc)
2312
               ; set DBG.DPB.
2313
               (set dbg (or dbg 1)))
2314
     ())
2315
 
2316
 
2317
; Leading zero instruction.
2318
 
2319
(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2))
2320
     "ldz $rn,$rm"
2321
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0))
2322
     (sequence ()
2323
               (c-call "check_option_ldz" pc)
2324
               (set rn (c-call SI "do_ldz" rm)))
2325
     ((mep (unit u-use-gpr (in usereg rm))
2326
           (unit u-exec))))
2327
 
2328
 
2329
; Absolute difference instruction.
2330
 
2331
(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2))
2332
     "abs $rn,$rm"
2333
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3))
2334
     (sequence ()
2335
               (c-call "check_option_abs" pc)
2336
               (set rn (abs (sub rn rm))))
2337
     ((mep (unit u-use-gpr (in usereg rm))
2338
           (unit u-use-gpr (in usereg rn))
2339
           (unit u-exec))))
2340
 
2341
 
2342
; Average instruction.
2343
 
2344
(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2))
2345
     "ave $rn,$rm"
2346
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2))
2347
     (sequence ()
2348
               (c-call "check_option_ave" pc)
2349
               (set rn (sra (add (add rn rm) 1) 1)))
2350
     ((mep (unit u-use-gpr (in usereg rm))
2351
           (unit u-use-gpr (in usereg rn))
2352
           (unit u-exec))))
2353
 
2354
 
2355
; MIN/MAX instructions.
2356
 
2357
(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2))
2358
     "min $rn,$rm"
2359
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4))
2360
     (sequence ()
2361
               (c-call "check_option_minmax" pc)
2362
               (if (gt rn rm)
2363
                   (set rn rm)))
2364
     ((mep (unit u-use-gpr (in usereg rm))
2365
           (unit u-use-gpr (in usereg rn))
2366
           (unit u-exec))))
2367
 
2368
(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2))
2369
     "max $rn,$rm"
2370
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5))
2371
     (sequence ()
2372
               (c-call "check_option_minmax" pc)
2373
               (if (lt rn rm)
2374
                   (set rn rm)))
2375
     ((mep (unit u-use-gpr (in usereg rm))
2376
           (unit u-use-gpr (in usereg rn))
2377
           (unit u-exec))))
2378
 
2379
(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
2380
     "minu $rn,$rm"
2381
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6))
2382
     (sequence ()
2383
               (c-call "check_option_minmax" pc)
2384
               (if (gtu rn rm)
2385
                   (set rn rm)))
2386
     ((mep (unit u-use-gpr (in usereg rm))
2387
           (unit u-use-gpr (in usereg rn))
2388
           (unit u-exec))))
2389
 
2390
(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
2391
     "maxu $rn,$rm"
2392
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7))
2393
     (sequence ()
2394
               (c-call "check_option_minmax" pc)
2395
               (if (ltu rn rm)
2396
                   (set rn rm)))
2397
     ((mep (unit u-use-gpr (in usereg rm))
2398
           (unit u-use-gpr (in usereg rn))
2399
           (unit u-exec))))
2400
 
2401
 
2402
; Clipping instruction.
2403
 
2404
(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2))
2405
     "clip $rn,$cimm5"
2406
     (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0))
2407
     (sequence ((SI min) (SI max))
2408
               (c-call "check_option_clip" pc)
2409
               (set max (sub (sll 1 (sub cimm5 1)) 1))
2410
               (set min (neg (sll 1 (sub cimm5 1))))
2411
               (cond
2412
                ((eq cimm5 0) (set rn 0))
2413
                ((gt rn max) (set rn max))
2414
                ((lt rn min) (set rn min))))
2415
     ((mep (unit u-use-gpr (in usereg rn))
2416
           (unit u-exec))))
2417
 
2418
(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2))
2419
     "clipu $rn,$cimm5"
2420
     (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1))
2421
     (sequence ((SI max))
2422
               (c-call "check_option_clip" pc)
2423
               (set max (sub (sll 1 cimm5) 1))
2424
               (cond
2425
                ((eq cimm5 0) (set rn 0))
2426
                ((gt rn max) (set rn max))
2427
                ((lt rn 0) (set rn 0))))
2428
     ((mep (unit u-use-gpr (in usereg rn))
2429
           (unit u-exec))))
2430
 
2431
 
2432
; Saturation instructions.
2433
 
2434
(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2))
2435
     "sadd $rn,$rm"
2436
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8))
2437
     (sequence ()
2438
               (c-call "check_option_sat" pc)
2439
               (if (add-oflag rn rm 0)
2440
                   (if (nflag rn)
2441
                       ; underflow
2442
                       (set rn (neg (sll 1 31)))
2443
                       ; overflow
2444
                       (set rn (sub (sll 1 31) 1)))
2445
                   (set rn (add rn rm))))
2446
     ((mep (unit u-use-gpr (in usereg rm))
2447
           (unit u-use-gpr (in usereg rn))
2448
           (unit u-exec))))
2449
 
2450
(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
2451
     "ssub $rn,$rm"
2452
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10))
2453
     (sequence ()
2454
               (c-call "check_option_sat" pc)
2455
               (if (sub-oflag rn rm 0)
2456
                   (if (nflag rn)
2457
                       ; underflow
2458
                       (set rn (neg (sll 1 31)))
2459
                       ; overflow
2460
                       (set rn (sub (sll 1 31) 1)))
2461
                   (set rn (sub rn rm))))
2462
     ((mep (unit u-use-gpr (in usereg rm))
2463
           (unit u-use-gpr (in usereg rn))
2464
           (unit u-exec))))
2465
 
2466
(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2))
2467
     "saddu $rn,$rm"
2468
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9))
2469
     (sequence ()
2470
               (c-call "check_option_sat" pc)
2471
               (if (add-cflag rn rm 0)
2472
                   (set rn (inv 0))
2473
                   (set rn (add rn rm))))
2474
     ((mep (unit u-use-gpr (in usereg rm))
2475
           (unit u-use-gpr (in usereg rn))
2476
           (unit u-exec))))
2477
 
2478
(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
2479
     "ssubu $rn,$rm"
2480
     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11))
2481
     (sequence ()
2482
               (c-call "check_option_sat" pc)
2483
               (if (sub-cflag rn rm 0)
2484
                   (set rn 0)
2485
                   (set rn (sub rn rm))))
2486
     ((mep (unit u-use-gpr (in usereg rm))
2487
           (unit u-use-gpr (in usereg rn))
2488
           (unit u-exec))))
2489
 
2490
 
2491
; UCI and DSP options are defined in an external file.
2492
; See `mep-sample-ucidsp.cpu' for a sample.
2493
 
2494
 
2495
; Coprocessor instructions.
2496
 
2497
(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2498
     "swcp $crn,($rma)"
2499
     (+ MAJ_3 crn rma (f-sub4 8))
2500
     (sequence ()
2501
               (c-call "check_option_cp" pc)
2502
               (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2503
               (set (mem SI (and rma (inv SI 3))) crn))
2504
     ((mep (unit u-use-gpr (in usereg rma))
2505
           (unit u-exec))))
2506
 
2507
(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2508
     "lwcp $crn,($rma)"
2509
     (+ MAJ_3 crn rma (f-sub4 9))
2510
     (sequence ()
2511
               (c-call "check_option_cp" pc)
2512
               (set crn (mem SI (and rma (inv SI 3)))))
2513
     ((mep (unit u-use-gpr (in usereg rma))
2514
           (unit u-exec))))
2515
 
2516
(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2517
     "smcp $crn64,($rma)"
2518
     (+ MAJ_3 crn64 rma (f-sub4 10))
2519
     (sequence ()
2520
               (c-call "check_option_cp" pc)
2521
               (c-call "check_option_cp64" pc)
2522
               (c-call VOID "check_write_to_text" rma)
2523
               (c-call "do_smcp" rma crn64 pc))
2524
     ((mep (unit u-use-gpr (in usereg rma))
2525
           (unit u-exec))))
2526
 
2527
(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2528
     "lmcp $crn64,($rma)"
2529
     (+ MAJ_3 crn64 rma (f-sub4 11))
2530
     (sequence ()
2531
               (c-call "check_option_cp" pc)
2532
               (c-call "check_option_cp64" pc)
2533
               (set crn64 (c-call DI "do_lmcp" rma pc)))
2534
     ((mep (unit u-use-gpr (in usereg rma))
2535
           (unit u-exec))))
2536
 
2537
(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE))
2538
     "swcpi $crn,($rma+)"
2539
     (+ MAJ_3 crn rma (f-sub4 0))
2540
     (sequence ()
2541
               (c-call "check_option_cp" pc)
2542
               (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2543
               (set (mem SI (and rma (inv SI 3))) crn)
2544
               (set rma (add rma 4)))
2545
     ((mep (unit u-use-gpr (in usereg rma))
2546
           (unit u-exec))))
2547
 
2548
(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD))
2549
     "lwcpi $crn,($rma+)"
2550
     (+ MAJ_3 crn rma (f-sub4 1))
2551
     (sequence ()
2552
               (c-call "check_option_cp" pc)
2553
               (set crn (mem SI (and rma (inv SI 3))))
2554
               (set rma (add rma 4)))
2555
     ((mep (unit u-use-gpr (in usereg rma))
2556
           (unit u-exec))))
2557
 
2558
(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2559
     "smcpi $crn64,($rma+)"
2560
     (+ MAJ_3 crn64 rma (f-sub4 2))
2561
     (sequence ()
2562
               (c-call "check_option_cp" pc)
2563
               (c-call "check_option_cp64" pc)
2564
               (c-call VOID "check_write_to_text" rma)
2565
               (c-call "do_smcpi" (index-of rma) crn64 pc)
2566
               (set rma rma)) ; reference as output for intrinsic generation
2567
     ((mep (unit u-use-gpr (in usereg rma))
2568
           (unit u-exec))))
2569
 
2570
(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2571
     "lmcpi $crn64,($rma+)"
2572
     (+ MAJ_3 crn64 rma (f-sub4 3))
2573
     (sequence ()
2574
               (c-call "check_option_cp" pc)
2575
               (c-call "check_option_cp64" pc)
2576
               (set crn64 (c-call DI "do_lmcpi" (index-of rma) pc))
2577
               (set rma rma)) ; reference as output for intrinsic generation
2578
     ((mep (unit u-use-gpr (in usereg rma))
2579
           (unit u-exec))))
2580
 
2581
(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE))
2582
     "swcp $crn,$sdisp16($rma)"
2583
     (+ MAJ_15 crn rma (f-sub4 12) sdisp16)
2584
     (sequence ()
2585
               (c-call "check_option_cp" pc)
2586
               (set (mem SI (and (add rma sdisp16) (inv SI 3))) crn))
2587
     ((mep (unit u-use-gpr (in usereg rma))
2588
           (unit u-exec))))
2589
 
2590
(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD))
2591
     "lwcp $crn,$sdisp16($rma)"
2592
     (+ MAJ_15 crn rma (f-sub4 13) sdisp16)
2593
     (sequence ()
2594
               (c-call "check_option_cp" pc)
2595
               (set crn (mem SI (and (add rma sdisp16) (inv SI 3)))))
2596
     ((mep (unit u-use-gpr (in usereg rma))
2597
           (unit u-exec))))
2598
 
2599
(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2600
     "smcp $crn64,$sdisp16($rma)"
2601
     (+ MAJ_15 crn64 rma (f-sub4 14) sdisp16)
2602
     (sequence ()
2603
               (c-call "check_option_cp" pc)
2604
               (c-call "check_option_cp64" pc)
2605
               (c-call "do_smcp16" rma sdisp16 crn64 pc))
2606
     ((mep (unit u-use-gpr (in usereg rma))
2607
           (unit u-exec))))
2608
 
2609
(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2610
     "lmcp $crn64,$sdisp16($rma)"
2611
     (+ MAJ_15 crn64 rma (f-sub4 15) sdisp16)
2612
     (sequence ()
2613
               (c-call "check_option_cp" pc)
2614
               (c-call "check_option_cp64" pc)
2615
               (set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc)))
2616
     ((mep (unit u-use-gpr (in usereg rma))
2617
           (unit u-exec))))
2618
 
2619
(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2620
     "sbcpa $crn,($rma+),$cdisp10"
2621
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10)
2622
     (sequence ()
2623
               (c-call "check_option_cp" pc)
2624
               (c-call VOID "check_write_to_text" rma)
2625
               (set (mem QI rma) (and crn #xff))
2626
               (set rma (add rma (ext SI cdisp10))))
2627
     ((mep (unit u-use-gpr (in usereg rma))
2628
           (unit u-exec))))
2629
 
2630
(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2631
     "lbcpa $crn,($rma+),$cdisp10"
2632
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10)
2633
     (sequence ()
2634
               (c-call "check_option_cp" pc)
2635
               (set crn (ext SI (mem QI rma)))
2636
               (set rma (add rma (ext SI cdisp10))))
2637
     ((mep (unit u-use-gpr (in usereg rma))
2638
           (unit u-exec))))
2639
 
2640
(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2641
     "shcpa $crn,($rma+),$cdisp10a2"
2642
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2)
2643
     (sequence ()
2644
               (c-call "check_option_cp" pc)
2645
               (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
2646
               (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
2647
               (set rma (add rma (ext SI cdisp10a2))))
2648
     ((mep (unit u-use-gpr (in usereg rma))
2649
           (unit u-exec))))
2650
 
2651
(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2652
     "lhcpa $crn,($rma+),$cdisp10a2"
2653
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2)
2654
     (sequence ()
2655
               (c-call "check_option_cp" pc)
2656
               (set crn (ext SI (mem HI (and rma (inv SI 1)))))
2657
               (set rma (add rma (ext SI cdisp10a2))))
2658
     ((mep (unit u-use-gpr (in usereg rma))
2659
           (unit u-exec))))
2660
 
2661
(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2662
     "swcpa $crn,($rma+),$cdisp10a4"
2663
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4)
2664
     (sequence ()
2665
               (c-call "check_option_cp" pc)
2666
               (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2667
               (set (mem SI (and rma (inv SI 3))) crn)
2668
               (set rma (add rma (ext SI cdisp10a4))))
2669
     ((mep (unit u-use-gpr (in usereg rma))
2670
           (unit u-exec))))
2671
 
2672
(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2673
     "lwcpa $crn,($rma+),$cdisp10a4"
2674
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4)
2675
     (sequence ()
2676
               (c-call "check_option_cp" pc)
2677
               (set crn (mem SI (and rma (inv SI 3))))
2678
               (set rma (add rma (ext SI cdisp10a4))))
2679
     ((mep (unit u-use-gpr (in usereg rma))
2680
           (unit u-exec))))
2681
 
2682
(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2683
     "smcpa $crn64,($rma+),$cdisp10a8"
2684
     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8)
2685
     (sequence ()
2686
               (c-call "check_option_cp" pc)
2687
               (c-call "check_option_cp64" pc)
2688
               (c-call VOID "check_write_to_text" rma)
2689
               (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc)
2690
               (set rma rma)) ; reference as output for intrinsic generation
2691
     ((mep (unit u-use-gpr (in usereg rma))
2692
           (unit u-exec))))
2693
 
2694
(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2695
     "lmcpa $crn64,($rma+),$cdisp10a8"
2696
     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8)
2697
     (sequence ()
2698
               (c-call "check_option_cp" pc)
2699
               (c-call "check_option_cp64" pc)
2700
               (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc))
2701
               (set rma rma)) ; reference as output for intrinsic generation
2702
     ((mep (unit u-use-gpr (in usereg rma))
2703
           (unit u-exec))))
2704
 
2705
 
2706
(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
2707
     "sbcpm0 $crn,($rma+),$cdisp10"
2708
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
2709
     (sequence ()
2710
               (c-call "check_option_cp" pc)
2711
               (c-call VOID "check_write_to_text" rma)
2712
               (set (mem QI rma) (and crn #xff))
2713
               (set rma (mod0 cdisp10)))
2714
     ((mep (unit u-use-gpr (in usereg rma))
2715
           (unit u-exec))))
2716
 
2717
(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
2718
     "lbcpm0 $crn,($rma+),$cdisp10"
2719
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10)
2720
     (sequence ()
2721
               (c-call "check_option_cp" pc)
2722
               (set crn (ext SI (mem QI rma)))
2723
               (set rma (mod0 cdisp10)))
2724
     ((mep (unit u-use-gpr (in usereg rma))
2725
           (unit u-exec))))
2726
 
2727
(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
2728
     "shcpm0 $crn,($rma+),$cdisp10a2"
2729
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2)
2730
     (sequence ()
2731
               (c-call "check_option_cp" pc)
2732
               (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
2733
               (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
2734
               (set rma (mod0 cdisp10a2)))
2735
     ((mep (unit u-use-gpr (in usereg rma))
2736
           (unit u-exec))))
2737
 
2738
(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
2739
     "lhcpm0 $crn,($rma+),$cdisp10a2"
2740
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2)
2741
     (sequence ()
2742
               (c-call "check_option_cp" pc)
2743
               (set crn (ext SI (mem HI (and rma (inv SI 1)))))
2744
               (set rma (mod0 cdisp10a2)))
2745
     ((mep (unit u-use-gpr (in usereg rma))
2746
           (unit u-exec))))
2747
 
2748
(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
2749
     "swcpm0 $crn,($rma+),$cdisp10a4"
2750
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4)
2751
     (sequence ()
2752
               (c-call "check_option_cp" pc)
2753
               (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2754
               (set (mem SI (and rma (inv SI 3))) crn)
2755
               (set rma (mod0 cdisp10a4)))
2756
     ((mep (unit u-use-gpr (in usereg rma))
2757
           (unit u-exec))))
2758
 
2759
(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
2760
     "lwcpm0 $crn,($rma+),$cdisp10a4"
2761
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4)
2762
     (sequence ()
2763
               (c-call "check_option_cp" pc)
2764
               (set crn (mem SI (and rma (inv SI 3))))
2765
               (set rma (mod0 cdisp10a4)))
2766
     ((mep (unit u-use-gpr (in usereg rma))
2767
           (unit u-exec))))
2768
 
2769
(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2770
     "smcpm0 $crn64,($rma+),$cdisp10a8"
2771
     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8)
2772
     (sequence ()
2773
               (c-call "check_option_cp" pc)
2774
               (c-call "check_option_cp64" pc)
2775
               (c-call VOID "check_write_to_text" rma)
2776
               (c-call "do_smcp" rma crn64 pc)
2777
               (set rma (mod0 cdisp10a8)))
2778
     ((mep (unit u-use-gpr (in usereg rma))
2779
           (unit u-exec))))
2780
 
2781
(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2782
     "lmcpm0 $crn64,($rma+),$cdisp10a8"
2783
     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8)
2784
     (sequence ()
2785
               (c-call "check_option_cp" pc)
2786
               (c-call "check_option_cp64" pc)
2787
               (set crn64 (c-call DI "do_lmcp" rma pc))
2788
               (set rma (mod0 cdisp10a8)))
2789
     ((mep (unit u-use-gpr (in usereg rma))
2790
           (unit u-exec))))
2791
 
2792
(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
2793
     "sbcpm1 $crn,($rma+),$cdisp10"
2794
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10)
2795
     (sequence ()
2796
               (c-call "check_option_cp" pc)
2797
               (c-call VOID "check_write_to_text" rma)
2798
               (set (mem QI rma) (and crn #xff))
2799
               (set rma (mod1 cdisp10)))
2800
     ((mep (unit u-use-gpr (in usereg rma))
2801
           (unit u-exec))))
2802
 
2803
(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
2804
     "lbcpm1 $crn,($rma+),$cdisp10"
2805
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10)
2806
     (sequence ()
2807
               (c-call "check_option_cp" pc)
2808
               (set crn (ext SI (mem QI rma)))
2809
               (set rma (mod1 cdisp10)))
2810
     ((mep (unit u-use-gpr (in usereg rma))
2811
           (unit u-exec))))
2812
 
2813
(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
2814
     "shcpm1 $crn,($rma+),$cdisp10a2"
2815
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2)
2816
     (sequence ()
2817
               (c-call "check_option_cp" pc)
2818
               (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
2819
               (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
2820
               (set rma (mod1 cdisp10a2)))
2821
     ((mep (unit u-use-gpr (in usereg rma))
2822
           (unit u-exec))))
2823
 
2824
(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
2825
     "lhcpm1 $crn,($rma+),$cdisp10a2"
2826
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2)
2827
     (sequence ()
2828
               (c-call "check_option_cp" pc)
2829
               (set crn (ext SI (mem HI (and rma (inv SI 1)))))
2830
               (set rma (mod1 cdisp10a2)))
2831
     ((mep (unit u-use-gpr (in usereg rma))
2832
           (unit u-exec))))
2833
 
2834
(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
2835
     "swcpm1 $crn,($rma+),$cdisp10a4"
2836
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4)
2837
     (sequence ()
2838
               (c-call "check_option_cp" pc)
2839
               (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2840
               (set (mem SI (and rma (inv SI 3))) crn)
2841
               (set rma (mod1 cdisp10a4)))
2842
     ((mep (unit u-use-gpr (in usereg rma))
2843
           (unit u-exec))))
2844
 
2845
(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
2846
     "lwcpm1 $crn,($rma+),$cdisp10a4"
2847
     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4)
2848
     (sequence ()
2849
               (c-call "check_option_cp" pc)
2850
               (set crn (ext SI (mem SI (and rma (inv SI 3)))))
2851
               (set rma (mod1 cdisp10a4)))
2852
     ((mep (unit u-use-gpr (in usereg rma))
2853
           (unit u-exec))))
2854
 
2855
(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2856
     "smcpm1 $crn64,($rma+),$cdisp10a8"
2857
     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8)
2858
     (sequence ()
2859
               (c-call "check_option_cp" pc)
2860
               (c-call "check_option_cp64" pc)
2861
               (c-call "do_smcp" rma crn64 pc)
2862
               (c-call VOID "check_write_to_text" rma)
2863
               (set rma (mod1 cdisp10a8)))
2864
     ((mep (unit u-use-gpr (in usereg rma))
2865
           (unit u-exec))))
2866
 
2867
(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2868
     "lmcpm1 $crn64,($rma+),$cdisp10a8"
2869
     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8)
2870
     (sequence ()
2871
               (c-call "check_option_cp" pc)
2872
               (c-call "check_option_cp64" pc)
2873
               (set crn64 (c-call DI "do_lmcp" rma pc))
2874
               (set rma (mod1 cdisp10a8)))
2875
     ((mep (unit u-use-gpr (in usereg rma))
2876
           (unit u-exec))))
2877
 
2878
(dnop cp_flag       "branch condition register"  (all-mep-isas) h-ccr   1)
2879
 
2880
(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE)
2881
     "bcpeq $cccc,$pcrel17a2"
2882
     (+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2)
2883
     (sequence ()
2884
               (c-call "check_option_cp" pc)
2885
               (if (eq (xor cccc cp_flag) 0)
2886
               (set-vliw-alignment-modified pc pcrel17a2)))
2887
     ())
2888
 
2889
(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE)
2890
     "bcpne $cccc,$pcrel17a2"
2891
     (+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2)
2892
     (sequence ()
2893
               (c-call "check_option_cp" pc)
2894
               (if (ne (xor cccc cp_flag) 0)
2895
               (set-vliw-alignment-modified pc pcrel17a2)))
2896
     ())
2897
 
2898
(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE)
2899
     "bcpat $cccc,$pcrel17a2"
2900
     (+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2)
2901
     (sequence ()
2902
               (c-call "check_option_cp" pc)
2903
               (if (ne (and cccc cp_flag) 0)
2904
               (set-vliw-alignment-modified pc pcrel17a2)))
2905
     ())
2906
 
2907
(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE)
2908
     "bcpaf $cccc,$pcrel17a2"
2909
     (+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2)
2910
     (sequence ()
2911
               (c-call "check_option_cp" pc)
2912
               (if (eq (and cccc cp_flag) 0)
2913
               (set-vliw-alignment-modified pc pcrel17a2)))
2914
     ())
2915
 
2916
(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN)
2917
     "synccp"
2918
     (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1))
2919
     (sequence ()
2920
               (c-call "check_option_cp" pc)
2921
               (unimp "synccp"))
2922
     ())
2923
 
2924
(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN)
2925
     "jsrv $rm"
2926
     (+ MAJ_1 (f-rn 8) rm (f-sub4 15))
2927
     (sequence ()
2928
               (cg-profile pc rm)
2929
               (c-call "check_option_cp" pc)
2930
               (core-vliw-switch
2931
 
2932
                ;; in core operating mode
2933
                (sequence ()
2934
                          (set lp (or (add pc 2) 1))
2935
                          (set-vliw-aliignment-modified-by-option pc rm)
2936
                          (set-psw.om 1)) ;; to VLIW operation mode
2937
 
2938
                ;; in VLIW32 operating mode
2939
                (sequence ()
2940
                          (set lp (or (add pc 4) 1))
2941
                          (set pc (and rm (inv 1)))
2942
                          (set-psw.om 0)) ;; to core operation mode
2943
 
2944
                ;; in VLIW64 operating mode
2945
                (sequence ()
2946
                          (set lp (or (add pc 8) 1))
2947
                          (set pc (and rm (inv 1)))
2948
                          (set-psw.om 0)))) ;; to core operation mode
2949
     ((mep (unit u-use-gpr (in usereg rm))
2950
           (unit u-exec)
2951
           (unit u-branch))))
2952
 
2953
(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN)
2954
     "bsrv $pcrel24a2"
2955
     (+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2)
2956
     (sequence ()
2957
               (cg-profile pc pcrel24a2)
2958
               (c-call "check_option_cp" pc)
2959
               (core-vliw-switch
2960
 
2961
                ;; in core operating mode
2962
                (sequence ()
2963
                          (set lp (or (add pc 4) 1))
2964
                          (set-vliw-aliignment-modified-by-option pc pcrel24a2)
2965
                          (set-psw.om 1)) ;; to VLIW operation mode
2966
 
2967
                ;; in VLIW32 operating mode
2968
                (sequence ()
2969
                          (set lp (or (add pc 4) 1))
2970
                          (set pc (and pcrel24a2 (inv 1)))
2971
                          (set-psw.om 0)) ;; to core operation mode
2972
 
2973
                ;; in VLIW64 operating mode
2974
                (sequence ()
2975
                          (set lp (or (add pc 8) 1))
2976
                          (set pc (and pcrel24a2 (inv 1)))
2977
                          (set-psw.om 0)))) ;; to core operation mode
2978
     ((mep (unit u-exec)
2979
           (unit u-branch))))
2980
 
2981
 
2982
; An instruction for test instrumentation.
2983
; Using a reserved opcode.
2984
 
2985
(dnci sim-syscall "simulator system call" ()
2986
     "--syscall--"
2987
     (+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0))
2988
     (c-call "do_syscall" pc callnum)
2989
     ())
2990
 
2991
(define-pmacro (dnri n major minor)
2992
  (dnci (.sym ri- n) "reserved instruction" ()
2993
        "--reserved--"
2994
        (+ major rn rm (f-sub4 minor))
2995
        (set pc (c-call USI "ri_exception" pc))
2996
        ((mep (unit u-exec)
2997
              (unit u-branch)))))
2998
 
2999
(dnri 0  MAJ_0   6)
3000
(dnri 1  MAJ_1  10)
3001
(dnri 2  MAJ_1  11)
3002
(dnri 3  MAJ_2   5)
3003
(dnri 4  MAJ_2   8)
3004
(dnri 5  MAJ_2   9)
3005
(dnri 6  MAJ_2  10)
3006
(dnri 7  MAJ_2  11)
3007
(dnri 8  MAJ_3   4)
3008
(dnri 9  MAJ_3   5)
3009
(dnri 10 MAJ_3   6)
3010
(dnri 11 MAJ_3   7)
3011
(dnri 12 MAJ_3  12)
3012
(dnri 13 MAJ_3  13)
3013
(dnri 14 MAJ_3  14)
3014
(dnri 15 MAJ_3  15)
3015
(dnri 17 MAJ_7   7)
3016
(dnri 20 MAJ_7  14)
3017
(dnri 21 MAJ_7  15)
3018
(dnri 22 MAJ_12  7)
3019
(dnri 23 MAJ_14 13)
3020
;(dnri 24 MAJ_15  3)
3021
(dnri 26 MAJ_15  8)
3022
; begin core-specific reserved insns
3023
; end core-specific reserved insns
3024
 
3025
 
3026
; Macro instructions.
3027
 
3028
(dnmi nop "nop"
3029
      ()
3030
      "nop"
3031
      (emit mov (rn 0) (rm 0)))
3032
 
3033
; Emit the 16 bit form of these 32 bit insns when the displacement is zero.
3034
;
3035
(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS)
3036
     "sb $rnc,$zero($rma)"
3037
     (emit sb rnc rma))
3038
 
3039
(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS)
3040
     "sh $rns,$zero($rma)"
3041
     (emit sh rns rma))
3042
 
3043
(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS)
3044
     "sw $rnl,$zero($rma)"
3045
     (emit sw rnl rma))
3046
 
3047
(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS)
3048
     "lb $rnc,$zero($rma)"
3049
     (emit lb rnc rma))
3050
 
3051
(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS)
3052
     "lh $rns,$zero($rma)"
3053
     (emit lh rns rma))
3054
 
3055
(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS)
3056
     "lw $rnl,$zero($rma)"
3057
     (emit lw rnl rma))
3058
 
3059
(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS)
3060
     "lbu $rnuc,$zero($rma)"
3061
     (emit lbu rnuc rma))
3062
 
3063
(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS)
3064
     "lhu $rnus,$zero($rma)"
3065
     (emit lhu rnus rma))
3066
 
3067
(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
3068
     "swcp $crn,$zero($rma)"
3069
     (emit swcp crn rma))
3070
 
3071
(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
3072
     "lwcp $crn,$zero($rma)"
3073
     (emit lwcp crn rma))
3074
 
3075
(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
3076
     "smcp $crn64,$zero($rma)"
3077
     (emit smcp crn64 rma))
3078
 
3079
(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
3080
     "lmcp $crn64,$zero($rma)"
3081
     (emit lmcp crn64 rma))

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