OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [mep/] [mep.md] - Blame information for rev 282

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn 
;; Toshiba Media Processor Machine description template
2 
;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 Free
3 
;; Software Foundation, Inc.
4 
;; Contributed by Red Hat Inc
5 
;;
6 
;; This file is part of GCC.
7 
;;
8 
;; GCC is free software; you can redistribute it and/or modify it
9 
;; under the terms of the GNU General Public License as published by
10 
;; the Free Software Foundation; either version 3, or (at your option)
11 
;; any later version.
12 
;;
13 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
;; License for more details.
17 
;;
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .  */
21 
 
22 
 
23 
 
24 
;; Constraints:
25 
;;
26 
;;  a   $sp
27 
;;  b   $tp
28 
;;  c   control regs
29 
;;  h   $hi ($23)
30 
;;  l   $lo ($24)
31 
;;  d   $hi/$lo pair (DImode)
32 
;;  j   $rpc ($22)
33 
;;  r   $0..$15
34 
;;  t   $0..$7
35 
;;  v   $gp
36 
;;  x   $c0..$c31
37 
;;  ex  coprocessor registers that can be moved to other coprocessor registers
38 
;;  er  coprocessor registers that can be moved to and from core registers
39 
;;  em  coprocessor registers that can be moves to and from memory
40 
;;  y   $ccr0..$ccr31
41 
;;  z   $0
42 
;;
43 
;;  I   sign imm16      mov/add
44 
;;  J   zero imm16      mov/add
45 
;;  K   zero imm24      mov
46 
;;  L   sign imm6       add
47 
;;  M   zero imm5       slt,shifts
48 
;;  N   zero imm4       bCC
49 
;;  O   high imm16      mov
50 
;;
51 
;;  R   near symbol
52 
;;  S   sign imm8       mov
53 
;;  T   tp or gp relative symbol
54 
;;  U   non-absolute memory
55 
;;  W   %hi(sym)
56 
;;  Y   (Rn)
57 
;;  Z   Control Bus Symbol
58 
;;
59 
;; Modifiers:
60 
;;
61 
;;  b   print unique bit in mask
62 
;;  B   print bits required for value (for clip)
63 
;;  h   print decimal >> 16.
64 
;;  I   print decimal, with hex comment if more than 8 bits
65 
;;  J   print unsigned hex
66 
;;  L   print set, clr or not (for bitops)
67 
;;  P   print memory as a post-inc with no increment
68 
;;  U   print bits required for value (for clipu)
69 
;;  x   print unsigned decimal or hex, depending on where set bits are
70 
 
71 
(define_constants [
72 
                   (REGSAVE_CONTROL_TEMP 11)
73 
                   (FP_REGNO 8)
74 
                   (TP_REGNO 13)
75 
                   (GP_REGNO 14)
76 
                   (SP_REGNO 15)
77 
                   (PSW_REGNO 16)
78 
                   (LP_REGNO 17)
79 
                   (SAR_REGNO 18)
80 
                   (RPB_REGNO 20)
81 
                   (RPE_REGNO 21)
82 
                   (RPC_REGNO 22)
83 
                   (HI_REGNO 23)
84 
                   (LO_REGNO 24)
85 
                   (CBCR_REGNO 81)
86 
                   ])
87 
 
88 
(define_constants [
89 
                   (UNS_BLOCKAGE 0)
90 
                   (UNS_TPREL 2)
91 
                   (UNS_GPREL 3)
92 
                   (UNS_REPEAT_BEG 4)
93 
                   (UNS_REPEAT_END 5)
94 
                   (UNS_EH_EPILOGUE 6)
95 
                   (UNS_EREPEAT_BEG 7)
96 
                   (UNS_EREPEAT_END 8)
97 
                   (UNS_BB_TRACE_RET 9)
98 
                   (UNS_DISABLE_INT 10)
99 
                   (UNS_ENABLE_INT 11)
100 
                   (UNS_RETI 12)
101 
                  ])
102 
 
103 
;; This attribute determines the VLIW packing mechanism.  The IVC2
104 
;; coprocessor has two pipelines (P0 and P1), and a MeP+IVC2 can issue
105 
;; up to three insns at a time.  Most IVC2 insns can run on either
106 
;; pipeline, however, scheduling some insns on P0 precludes packing a
107 
;; core insn with it, and only 16-bit core insns can pack with any P0
108 
;; insn.
109 
(define_attr "vliw" "basic,ivc2"
110 
  (const (symbol_ref "TARGET_IVC2")))
111 
 
112 
;; This attribute describes the kind of memory operand present in the
113 
;; instruction.  This is used to compute the length of the insn based
114 
;; on the addressing mode used.
115 
(define_attr "memop" "none,core0,core1,cop0,cop1"
116 
  (const_string "none"))
117 
 
118 
(define_attr "intrinsic" "none,cmov,cmov1,cmov2,cmovc1,cmovc2,cmovh1,cmovh2"
119 
  (const_string "none"))
120 
 
121 
;; This attribute describes how the instruction may be bundled in a
122 
;; VLIW instruction.  Type MULTI is assumed to use both slots.
123 
(define_attr "slot" "core,cop,multi"
124 
  (cond [(eq_attr "intrinsic" "!none")
125 
           (const_string "cop")]
126 
        (const_string "core")))
127 
 
128 
;; This attribute describes the latency of the opcode (ready delay).
129 
;; The 0 is used to indicate "unspecified".  An instruction that
130 
;; completes immediately with no potential stalls would have a value
131 
;; of 1, a one cycle stall would be 2, etc.
132 
(define_attr "latency" ""
133 
  (const_int 0))
134 
 
135 
(define_attr "shiftop" "none,operand2"
136 
  (const_string "none"))
137 
 
138 
;; This attribute describes the size of the instruction in bytes.
139 
;; This *must* be exact unless the pattern is SLOT_MULTI, as this
140 
;; is used by the VLIW bundling code.
141 
(define_attr "length" ""
142 
  (cond [(eq_attr "memop" "core0")
143 
           (symbol_ref "mep_core_address_length (insn, 0)")
144 
         (eq_attr "memop" "core1")
145 
           (symbol_ref "mep_core_address_length (insn, 1)")
146 
         (eq_attr "memop" "cop0")
147 
           (symbol_ref "mep_cop_address_length (insn, 0)")
148 
         (eq_attr "memop" "cop1")
149 
           (symbol_ref "mep_cop_address_length (insn, 1)")
150 
         ]
151 
         ; Catch patterns that don't define the length properly.
152 
         (symbol_ref "(abort (), 0)")))
153 
 
154 
;; This attribute describes a pipeline hazard seen in the insn.
155 
(define_attr "stall" "none,int2,ssarb,load,store,ldc,stc,ldcb,stcb,ssrab,fsft,ret,advck,mul,mulr,div"
156 
  (cond [(and (eq_attr "shiftop" "operand2")
157 
              (not (match_operand:SI 2 "mep_single_shift_operand" "")))
158 
         (const_string "int2")]
159 
        (const_string "none")))
160 
 
161 
(define_attr "may_trap" "no,yes"
162 
  (const_string "no"))
163 
 
164 
;; Describe a user's asm statement.
165 
(define_asm_attributes
166 
  [(set_attr "length" "4")
167 
   (set_attr "slot" "multi")])
168 
 
169 
;; Each IVC2 instruction uses one of these two pipelines.  P0S insns
170 
;; use P0; C3 insns use P1.
171 
(define_automaton "mep_ivc2")
172 
(define_cpu_unit "ivc2_core,ivc2_p0,ivc2_p1" "mep_ivc2")
173 
 
174 
;; Each core or IVC2 instruction is bundled into one of these slots.
175 
;; Supported bundlings:
176 
;;
177 
;; Core mode:
178 
;;
179 
;;  C1  [-----core-----]
180 
;;  C2  [-------------core-------------]
181 
;;  C3  [--------------c3--------------]
182 
;;
183 
;; VLIW mode:
184 
;;
185 
;;  V1  [-----core-----][--------p0s-------][------------p1------------]
186 
;;  V2  [-------------core-------------]xxxx[------------p1------------]
187 
;;  V3  1111[--p0--]0111[--------p0--------][------------p1------------]
188 
 
189 
(define_attr "slots" "core,c3,p0,p0_p0s,p0_p1,p0s,p0s_p1,p1" (const_string "core"))
190 
 
191 
(define_cpu_unit "ivc2_slot_c16,ivc2_slot_c32,ivc2_slot_c3,ivc2_slot_p0s,ivc2_slot_p0,ivc2_slot_p1" "mep_ivc2")
192 
 
193 
(define_insn_reservation "ivc2_insn_core16" 1
194 
  (and (eq_attr "vliw" "ivc2")
195 
       (and (eq (symbol_ref "get_attr_length(insn)") (const_int 2))
196 
            (and (eq_attr "intrinsic" "none")
197 
                 (eq_attr "slot" "!cop"))))
198 
  "ivc2_core+ivc2_slot_c16")
199 
 
200 
(define_insn_reservation "ivc2_insn_core32" 1
201 
  (and (eq_attr "vliw" "ivc2")
202 
       (and (eq (symbol_ref "get_attr_length(insn)") (const_int 4))
203 
            (and (eq_attr "intrinsic" "none")
204 
                 (eq_attr "slot" "!cop"))))
205 
  "ivc2_core+ivc2_slot_c32")
206 
 
207 
;; These shouldn't happen when in VLIW mode.
208 
(define_insn_reservation "ivc2_insn_c3" 1
209 
  (and (eq_attr "vliw" "ivc2")
210 
       (eq_attr "slots" "c3"))
211 
  "ivc2_p1+ivc2_slot_c3")
212 
 
213 
(define_insn_reservation "ivc2_insn_p0" 1
214 
  (and (eq_attr "vliw" "ivc2")
215 
       (eq_attr "slots" "p0"))
216 
  "ivc2_p0+ivc2_slot_p0")
217 
 
218 
(define_insn_reservation "ivc2_insn_p0_p0s" 1
219 
  (and (eq_attr "vliw" "ivc2")
220 
       (eq_attr "slots" "p0_p0s"))
221 
  "ivc2_p0+ivc2_slot_p0|ivc2_p0+ivc2_slot_p0s")
222 
 
223 
(define_insn_reservation "ivc2_insn_p0_p1" 1
224 
  (and (eq_attr "vliw" "ivc2")
225 
       (eq_attr "slots" "p0_p1"))
226 
  "ivc2_p0+ivc2_slot_p0|ivc2_p1+ivc2_slot_p1")
227 
 
228 
(define_insn_reservation "ivc2_insn_p0s" 1
229 
  (and (eq_attr "vliw" "ivc2")
230 
       (eq_attr "slots" "p0s"))
231 
  "ivc2_p0+ivc2_slot_p0s")
232 
 
233 
(define_insn_reservation "ivc2_insn_p0s_p1" 1
234 
  (and (eq_attr "vliw" "ivc2")
235 
       (eq_attr "slots" "p0s_p1"))
236 
  "ivc2_p0+ivc2_slot_p0s|ivc2_p1+ivc2_slot_p1")
237 
 
238 
(define_insn_reservation "ivc2_insn_p1" 1
239 
  (and (eq_attr "vliw" "ivc2")
240 
       (eq_attr "slots" "p1"))
241 
  "ivc2_p1+ivc2_slot_p1")
242 
 
243 
;; these run in C3 also, but when we're doing VLIW scheduling, they
244 
;; only run in P0.
245 
(define_insn_reservation "ivc2_insn_cmov" 1
246 
  (and (eq_attr "vliw" "ivc2")
247 
       (eq_attr "intrinsic" "!none"))
248 
  "ivc2_p0+ivc2_slot_p0")
249 
 
250 
 
251 
(exclusion_set "ivc2_slot_c32"
252 
               "ivc2_slot_p0,ivc2_slot_p0s")
253 
(exclusion_set "ivc2_slot_p0"
254 
               "ivc2_slot_p0s")
255 
(exclusion_set "ivc2_slot_c16"
256 
               "ivc2_slot_p0")
257 
(exclusion_set "ivc2_slot_c16"
258 
               "ivc2_slot_c32")
259 
 
260 
;; Non-IVC2 scheduling.
261 
(define_automaton "mep")
262 
(define_cpu_unit "core,cop" "mep")
263 
 
264 
;; Latencies are the time between one insn entering the second pipeline
265 
;; stage (E2, LD, A2 or V2) and the next instruction entering the same
266 
;; stage.  When an instruction assigns to general registers, the default
267 
;; latencies are for when the next instruction receives the register
268 
;; through bypass 1.
269 
 
270 
;; Arithmetic instructions that execute in a single stage.
271 
(define_insn_reservation "h1_int1" 2
272 
  (and (eq_attr "slot" "!cop")
273 
       (eq_attr "stall" "none"))
274 
  "core")
275 
(define_bypass 1 "h1_int1" "h1_int1,h1_ssarb")
276 
(define_bypass 1 "h1_int1" "h1_store" "mep_store_data_bypass_p")
277 
 
278 
;; $sar can be read by an immediately following fsft or ldc.
279 
(define_insn_reservation "h1_ssarb" 1
280 
  (eq_attr "stall" "ssarb")
281 
  "core")
282 
 
283 
;; Arithmetic instructions that execute in two stages.
284 
(define_insn_reservation "h1_int2" 2
285 
  (eq_attr "stall" "int2,fsft")
286 
  "core")
287 
(define_bypass 1 "h1_int2" "h1_int1,h1_ssarb")
288 
(define_bypass 1 "h1_int2" "h1_store" "mep_store_data_bypass_p")
289 
 
290 
(define_insn_reservation "h1_load" 4
291 
  (eq_attr "stall" "load")
292 
  "core")
293 
(define_bypass 3 "h1_load" "h1_int1,h1_ssarb")
294 
(define_bypass 3 "h1_load" "h1_store" "mep_store_data_bypass_p")
295 
 
296 
(define_insn_reservation "h1_store" 1
297 
  (eq_attr "stall" "store")
298 
  "core")
299 
 
300 
(define_insn_reservation "h1_ipipe_ldc" 2
301 
  (and (eq_attr "stall" "ldc")
302 
       (ne (symbol_ref "mep_ipipe_ldc_p(insn)") (const_int 0)))
303 
  "core")
304 
(define_bypass 1 "h1_ipipe_ldc" "h1_int1,h1_ssarb")
305 
(define_bypass 1 "h1_ipipe_ldc" "h1_store" "mep_store_data_bypass_p")
306 
 
307 
(define_insn_reservation "h1_apipe_ldc" 2
308 
  (and (eq_attr "stall" "ldc")
309 
       (eq (symbol_ref "mep_ipipe_ldc_p(insn)") (const_int 0)))
310 
  "core")
311 
 
312 
;; 2 is correct for stc->ret and stc->fsft.  The most important remaining
313 
;; case is stc->madd, which induces no stall.
314 
(define_insn_reservation "h1_stc" 2
315 
  (eq_attr "stall" "stc")
316 
  "core")
317 
(define_bypass 1 "h1_stc" "h1_mul")
318 
 
319 
;; ??? Parameterised latency.
320 
(define_insn_reservation "h1_ldcb" 5
321 
  (eq_attr "stall" "ldcb")
322 
  "core")
323 
 
324 
(define_insn_reservation "h1_stcb" 1
325 
  (eq_attr "stall" "stcb")
326 
  "core")
327 
 
328 
(define_insn_reservation "h1_advck" 6
329 
  (eq_attr "stall" "advck")
330 
  "core")
331 
 
332 
(define_insn_reservation "h1_mul" 5
333 
  (eq_attr "stall" "mul,mulr")
334 
  "core")
335 
(define_bypass 4 "h1_mul" "h1_int1,h1_ssarb")
336 
(define_bypass 4 "h1_mul" "h1_store" "mep_store_data_bypass_p")
337 
(define_bypass 1 "h1_mul" "h1_mul" "mep_mul_hilo_bypass_p")
338 
 
339 
(define_insn_reservation "h1_div" 36
340 
  (eq_attr "stall" "div")
341 
  "core")
342 
 
343 
(define_insn_reservation "h1_cop" 1
344 
  (eq_attr "slot" "cop")
345 
  "cop")
346 
 
347 
(include "predicates.md")
348 
(include "constraints.md")
349 
(include "intrinsics.md")
350 
 
351 
;; ::::::::::::::::::::
352 
;; ::
353 
;; :: Moves
354 
;; ::
355 
;; ::::::::::::::::::::
356 
 
357 
(define_expand "movqi"
358 
  [(set (match_operand:QI 0 "general_operand" "")
359 
        (match_operand:QI 1 "general_operand" ""))]
360 
  ""
361 
  "
362 
{
363 
  if (mep_expand_mov (operands, QImode))
364 
    DONE;
365 
}")
366 
 
367 
;; The Idea here is to prefer the 16-bit tp-relative load, but to fall back
368 
;; to the general 32-bit load rather than do silly things with spill regs.
369 
(define_insn "*movqi_tprel_load"
370 
  [(set (match_operand:QI 0 "mep_tprel_operand" "=t,*r")
371 
        (mem:QI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
372 
                         (const:SI (unspec:SI [(match_operand:SI 2
373 
                                                "symbolic_operand" "s,s")]
374 
                                              UNS_TPREL)))))]
375 
  ""
376 
  "lb\\t%0, %%tpoff(%2)(%1)"
377 
  [(set_attr "length" "2,4")
378 
   (set_attr "stall" "load")])
379 
 
380 
(define_insn "*movqi_tprel_store"
381 
  [(set (mem:QI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
382 
                         (const:SI (unspec:SI [(match_operand:SI 1
383 
                                                "symbolic_operand" "s,s")]
384 
                                              UNS_TPREL))))
385 
        (match_operand:QI 2 "mep_tprel_operand" "t,*r"))]
386 
  ""
387 
  "sb\\t%2, %%tpoff(%1)(%0)"
388 
  [(set_attr "length" "2,4")
389 
   (set_attr "stall" "store")])
390 
 
391 
(define_insn "*movqi_internal"
392 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r, r,m,r,c,r,y,r,er,ex,em,Y")
393 
        (match_operand:QI 1 "general_operand" " r,n,rm,r,c,r,y,r,er,r,ex,Y,em"))]
394 
  "mep_mov_ok (operands, QImode)"
395 
  "@
396 
   mov\\t%0, %1
397 
   mov\\t%0, %1
398 
   lb\\t%0, %1
399 
   sb\\t%1, %0
400 
   ldc\\t%0, %1
401 
   stc\\t%1, %0
402 
   cmovc\\t%0, %1
403 
   cmovc\\t%0, %1
404 
   cmov\\t%0, %1
405 
   cmov\\t%0, %1
406 
   %<\\t%0, %M1
407 
   lbcpa\\t%0, %P1
408 
   sbcpa\\t%1, %P0"
409 
  [(set_attr "length" "2,2,*,*,2,2,4,4,4,4,*,4,4")
410 
   (set_attr "intrinsic" "*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
411 
   (set_attr "stall"  "*,*,load,store,ldc,stc,*,*,*,*,*,load,store")
412 
   (set_attr "memop"  "*,*,core1,core0,*,*,*,*,*,*,*,*,*")])
413 
 
414 
(define_expand "movhi"
415 
  [(set (match_operand:HI 0 "general_operand" "")
416 
        (match_operand:HI 1 "general_operand" ""))]
417 
  ""
418 
  "
419 
{
420 
  if (mep_expand_mov (operands, HImode))
421 
    DONE;
422 
}")
423 
 
424 
(define_insn "*movhi_tprel_load"
425 
  [(set (match_operand:HI 0 "mep_tprel_operand" "=t,*r")
426 
        (mem:HI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
427 
                         (const:SI (unspec:SI [(match_operand:SI 2
428 
                                                "symbolic_operand" "s,s")]
429 
                                              UNS_TPREL)))))]
430 
  ""
431 
  "lh\\t%0, %%tpoff(%2)(%1)"
432 
  [(set_attr "length" "2,4")
433 
   (set_attr "stall" "load")])
434 
 
435 
(define_insn "*movhi_tprel_store"
436 
  [(set (mem:HI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
437 
                         (const:SI (unspec:SI [(match_operand:SI 1
438 
                                                "symbolic_operand" "s,s")]
439 
                                              UNS_TPREL))))
440 
        (match_operand:HI 2 "mep_tprel_operand" "t,*r"))]
441 
  ""
442 
  "sh\\t%2, %%tpoff(%1)(%0)"
443 
  [(set_attr "length" "2,4")
444 
   (set_attr "stall" "store")])
445 
 
446 
(define_insn "*movhi_internal"
447 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,m,r,c,r,y,r,er,ex,em,Y")
448 
        (match_operand:HI 1 "general_operand" " r,S,n,m,r,c,r,y,r,er,r,ex,Y,em"))]
449 
  "mep_mov_ok (operands, HImode)"
450 
  "@
451 
   mov\\t%0, %1
452 
   mov\\t%0, %I1
453 
   mov\\t%0, %I1
454 
   lh\\t%0, %1
455 
   sh\\t%1, %0
456 
   ldc\\t%0, %1
457 
   stc\\t%1, %0
458 
   cmovc\\t%0, %1
459 
   cmovc\\t%0, %1
460 
   cmov\\t%0, %1
461 
   cmov\\t%0, %1
462 
   %<\\t%0, %M1
463 
   lhcpa\\t%0, %P1
464 
   shcpa\\t%1, %P0"
465 
  [(set_attr "length" "2,2,4,*,*,2,2,4,4,4,4,*,4,4")
466 
   (set_attr "intrinsic" "*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
467 
   (set_attr "stall"  "*,*,*,load,store,ldc,stc,*,*,*,*,*,load,store")
468 
   (set_attr "memop"  "*,*,*,core1,core0,*,*,*,*,*,*,*,*,*")])
469 
 
470 
(define_expand "movsi"
471 
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
472 
        (match_operand:SI 1 "general_operand" ""))]
473 
  ""
474 
  "
475 
{
476 
  if (mep_expand_mov (operands, SImode))
477 
    DONE;
478 
}")
479 
 
480 
(define_insn "*movsi_tprel_load"
481 
  [(set (match_operand:SI 0 "mep_tprel_operand" "=t,*r")
482 
        (mem:SI (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
483 
                         (const:SI (unspec:SI [(match_operand:SI 2
484 
                                                "symbolic_operand" "s,s")]
485 
                                              UNS_TPREL)))))]
486 
  ""
487 
  "lw\\t%0, %%tpoff(%2)(%1)"
488 
  [(set_attr "length" "2,4")
489 
   (set_attr "stall" "load")])
490 
 
491 
(define_insn "*movsi_tprel_store"
492 
  [(set (mem:SI (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
493 
                         (const:SI (unspec:SI [(match_operand:SI 1
494 
                                                "symbolic_operand" "s,s")]
495 
                                              UNS_TPREL))))
496 
        (match_operand:SI 2 "mep_tprel_operand" "t,*r"))]
497 
  ""
498 
  "sw\\t%2, %%tpoff(%1)(%0)"
499 
  [(set_attr "length" "2,4")
500 
   (set_attr "stall" "store")])
501 
 
502 
(define_insn "movsi_topsym_s"
503 
  [(set (match_operand:SI 0 "register_operand" "=r")
504 
        (high:SI (match_operand:SI 1 "symbolic_operand" "s")))]
505 
  ""
506 
  "movh\\t%0, %%hi(%1)"
507 
  [(set_attr "length" "4")])
508 
 
509 
(define_insn "movsi_botsym_s"
510 
  [(set (match_operand:SI 0 "register_operand" "=r")
511 
        (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
512 
                   (match_operand:SI 2 "symbolic_operand" "s")))]
513 
  ""
514 
  "add3\\t%0, %1, %%lo(%2)"
515 
  [(set_attr "length" "4")])
516 
 
517 
 
518 
 
519 
(define_insn "cmovh_getsub"
520 
  [(set (match_operand:SI 0 "register_operand" "=r")
521 
        (subreg:SI (match_operand:DI 1 "register_operand" "er") 4))]
522 
  "0 && TARGET_64BIT_CR_REGS"
523 
  "cmovh\\t%0, %1"
524 
  [(set_attr "intrinsic" "cmovh2")
525 
   (set_attr "length" "4")])
526 
 
527 
(define_insn "*movsi_internal"
528 
  [(set (match_operand:SI 0 "mep_movdest_operand"
529 
            "=r,r,r,r,r, t,t,r,r,r,Z,m,r,c,r,y,r, er,ex,em,U ")
530 
        (match_operand:SI 1 "general_operand"
531 
            " r,S,I,J,OW,K,s,i,Z,m,r,r,c,r,y,r,er,r, ex,U, em"))]
532 
  "mep_mov_ok (operands, SImode)"
533 
  "@
534 
   mov\\t%0, %1
535 
   mov\\t%0, %I1
536 
   mov\\t%0, %I1
537 
   movu\\t%0, %J1
538 
   movh\\t%0, %h1
539 
   movu\\t%0, %x1
540 
   movu\\t%0, %1
541 
   #
542 
   ldcb\\t%0, %1
543 
   lw\\t%0, %1
544 
   stcb\\t%1, %0
545 
   sw\\t%1, %0
546 
   ldc\\t%0, %1
547 
   stc\\t%1, %0
548 
   cmovc\\t%0, %1
549 
   cmovc\\t%0, %1
550 
   cmov\\t%0, %1
551 
   cmov\\t%0, %1
552 
   %<\\t%0, %M1
553 
   lwcp\\t%0, %1
554 
   swcp\\t%1, %0"
555 
  [(set_attr "length" "2,2,4,4,4,4,4,*,4,*,4,*,2,2,4,4,4,4,4,*,*")
556 
   (set_attr "intrinsic" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
557 
   (set_attr "stall"  "*,*,*,*,*,*,*,*,ldcb,load,stcb,store,ldc,stc,*,*,*,*,*,load,store")
558 
   (set_attr "memop"  "*,*,*,*,*,*,*,*,*,core1,*,core0,*,*,*,*,*,*,*,cop1,cop0")
559 
   (set_attr "slot"   "*,*,*,*,*,*,*,multi,*,*,*,*,*,*,*,*,*,*,*,*,*")])
560 
 
561 
(define_split
562 
  [(set (match_operand:SI 0 "register_operand" "")
563 
        (match_operand:SI 1 "const_int_operand" ""))]
564 
  "mep_split_mov (operands, 0)"
565 
  [(set (match_dup 0) (match_dup 2))
566 
   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
567 
  "
568 
{
569 
  HOST_WIDE_INT value;
570 
  int lo, hi;
571 
 
572 
  value = INTVAL (operands[1]);
573 
 
574 
  lo = value & 0xffff;
575 
  hi = trunc_int_for_mode (value & 0xffff0000, SImode);
576 
 
577 
  operands[2] = GEN_INT (hi);
578 
  operands[3] = GEN_INT (lo);
579 
}")
580 
 
581 
(define_split
582 
  [(set (match_operand:SI 0 "register_operand" "")
583 
        (match_operand:SI 1 "immediate_operand" ""))]
584 
  "mep_split_mov (operands, 1)"
585 
  [(set (match_dup 0) (high:SI (match_dup 1)))
586 
   (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
587 
  "")
588 
 
589 
;; ??? What purpose do these two serve that high+lo_sum do not?
590 
(define_insn "movsi_topsym_u"
591 
  [(set (match_operand:SI 0 "register_operand" "=r")
592 
        (and:SI (match_operand:SI 1 "symbolic_operand" "s")
593 
                (const_int -65536)))]
594 
  ""
595 
  "movh\\t%0, %%uhi(%1)"
596 
  [(set_attr "length" "4")])
597 
 
598 
(define_insn "movsi_botsym_u"
599 
  [(set (match_operand:SI 0 "register_operand" "=r")
600 
        (ior:SI (match_operand:SI 1 "register_operand" "0")
601 
                (and:SI (match_operand:SI 2 "symbolic_operand" "s")
602 
                        (const_int 65535))))]
603 
  ""
604 
  "or3\\t%0, %1, %%lo(%2)"
605 
  [(set_attr "length" "4")])
606 
 
607 
(define_expand "movdi"
608 
  [(set (match_operand:DI 0 "" "")
609 
        (match_operand:DI 1 "" ""))]
610 
  ""
611 
  "
612 
{
613 
  if (mep_expand_mov (operands, DImode))
614 
    DONE;
615 
}")
616 
 
617 
(define_insn "*movdi_internal_32"
618 
  [(set (match_operand:DI 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
619 
        (match_operand:DI 1 "general_operand"     "rim,r,c,r,er,r,ex,U,em"))]
620 
  "TARGET_32BIT_CR_REGS && mep_mov_ok (operands, DImode)"
621 
  "#"
622 
  [(set_attr "slot" "multi")])
623 
 
624 
(define_insn "*movdi_internal_64"
625 
  [(set (match_operand:DI 0 "mep_movdest_operand" "=r,r,m,r,c,r,er,ex,em,U")
626 
        (match_operand:DI 1 "general_operand"     "r,im,r,c,r,er,r,ex,U,em"))]
627 
  "TARGET_64BIT_CR_REGS && mep_mov_ok (operands, DImode)"
628 
  "@
629 
   #
630 
   #
631 
   #
632 
   #
633 
   #
634 
   #
635 
   #
636 
   %<\\t%0, %M1
637 
   lmcp\\t%0, %1
638 
   smcp\\t%1, %0"
639 
  [(set_attr "slot"  "multi,multi,multi,multi,multi,multi,multi,*,*,*")
640 
   (set_attr "intrinsic" "*,*,*,*,*,*,*,cmov,*,*")
641 
   (set_attr "memop" "*,*,*,*,*,*,*,cop0,cop1,cop0")
642 
   (set_attr "stall" "*,*,*,*,*,*,*,*,load,store")])
643 
 
644 
(define_insn "*movdi_cop_postinc"
645 
  [(parallel [(set (match_operand:DI 0 "register_operand" "=em")
646 
                   (mem:DI (reg:SI SP_REGNO)))
647 
              (set (reg:SI SP_REGNO)
648 
                   (plus:SI (reg:SI SP_REGNO)
649 
                            (const_int 8)))
650 
              ]
651 
             )]
652 
  "TARGET_COP"
653 
  "lmcpi\\t%0,($sp+)"
654 
  [(set_attr "length" "2")])
655 
 
656 
(define_insn "*movdi_cop_postinc"
657 
  [(parallel [(set (match_operand:DI 0 "register_operand" "=em")
658 
                   (mem:DI (match_operand:SI 2 "register_operand" "r")))
659 
              (set (match_operand:SI 1 "register_operand" "=0")
660 
                   (plus:SI (match_operand:SI 3 "register_operand" "0")
661 
                            (const_int 8)))
662 
              ]
663 
             )]
664 
  "TARGET_COP"
665 
  "lmcpi\\t%0,(%1+)"
666 
  [(set_attr "length" "2")])
667 
 
668 
(define_insn "*cmovh_set"
669 
  [(set (zero_extract:SI (match_operand:DI 0 "register_operand" "+er")
670 
                         (const_int 32)
671 
                         (const_int 32))
672 
        (match_operand:SI 1 "register_operand" "r"))]
673 
  "TARGET_64BIT_CR_REGS"
674 
  "cmovh\\t%0, %1"
675 
  [(set_attr "intrinsic" "cmovh1")
676 
   (set_attr "length" "4")])
677 
 
678 
(define_insn "cmovh_get"
679 
  [(set (match_operand:SI 0 "register_operand" "=r")
680 
        (zero_extract:SI (match_operand:DI 1 "register_operand" "er")
681 
                         (const_int 32)
682 
                         (const_int 32)))]
683 
  "TARGET_64BIT_CR_REGS"
684 
  "cmovh\\t%0, %1"
685 
  [(set_attr "intrinsic" "cmovh2")
686 
   (set_attr "length" "4")])
687 
 
688 
(define_split
689 
  [(set (match_operand:DI 0 "mep_movdest_operand" "")
690 
        (match_operand:DI 1 "general_operand" ""))]
691 
  "reload_completed && mep_multi_slot (insn)"
692 
  [(set (match_dup 2) (match_dup 3))
693 
   (set (match_dup 4) (match_dup 5))]
694 
  "mep_split_wide_move (operands, DImode);")
695 
 
696 
;; Floating Point Moves
697 
 
698 
(define_expand "movsf"
699 
  [(set (match_operand:SF 0 "nonimmediate_operand" "")
700 
        (match_operand:SF 1 "general_operand" ""))]
701 
  ""
702 
  "
703 
{
704 
  if (mep_expand_mov (operands, SFmode))
705 
    DONE;
706 
}")
707 
 
708 
(define_insn "*movsf_tprel_load"
709 
  [(set (match_operand:SF 0 "mep_tprel_operand" "=t,*r")
710 
        (mem:SF (plus:SI (match_operand:SI 1 "mep_tp_operand" "b,*r")
711 
                         (const:SI (unspec:SI [(match_operand:SI 2
712 
                                                "symbolic_operand" "s,s")]
713 
                                              UNS_TPREL)))))]
714 
  ""
715 
  "lw\\t%0, %%tpoff(%2)(%1)"
716 
  [(set_attr "length" "2,4")
717 
   (set_attr "stall" "load")])
718 
 
719 
(define_insn "*movsf_tprel_store"
720 
  [(set (mem:SF (plus:SI (match_operand:SI 0 "mep_tp_operand" "b,*r")
721 
                         (const:SI (unspec:SI [(match_operand:SI 1
722 
                                                "symbolic_operand" "s,s")]
723 
                                              UNS_TPREL))))
724 
        (match_operand:SF 2 "mep_tprel_operand" "t,*r"))]
725 
  ""
726 
  "sw\\t%2, %%tpoff(%1)(%0)"
727 
  [(set_attr "length" "2,4")
728 
   (set_attr "stall" "store")])
729 
 
730 
(define_insn "*movsf_internal"
731 
  [(set (match_operand:SF 0 "mep_movdest_operand"
732 
            "=r,r,r,r,Z,m,r,c,r,y,r,er,ex,em,U")
733 
        (match_operand:SF 1 "general_operand"
734 
            " r,F,Z,m,r,r,c,r,y,r,er,r,ex,U,em"))]
735 
  "mep_mov_ok (operands, SFmode)"
736 
  "@
737 
   mov\\t%0, %1
738 
   #
739 
   ldcb\\t%0, %1
740 
   lw\\t%0, %1
741 
   stcb\\t%1, %0
742 
   sw\\t%1, %0
743 
   ldc\\t%0, %1
744 
   stc\\t%1, %0
745 
   cmovc\\t%0, %1
746 
   cmovc\\t%0, %1
747 
   cmov\\t%0, %1
748 
   cmov\\t%0, %1
749 
   %<\\t%0, %M1
750 
   lwcp\\t%0, %1
751 
   swcp\\t%1, %0"
752 
  [(set_attr "length" "2,*,2,*,2,*,2,2,*,*,4,4,*,*,*")
753 
   (set_attr "intrinsic" "*,*,*,*,*,*,*,*,cmovc2,cmovc1,cmov2,cmov1,cmov,*,*")
754 
   (set_attr "stall"  "*,*,ldcb,load,stcb,store,ldc,stc,*,*,*,*,*,load,store")
755 
   (set_attr "memop"  "*,*,*,core1,*,core0,*,*,*,*,*,*,*,cop1,cop0")])
756 
 
757 
(define_split
758 
  [(set (match_operand:SF 0 "register_operand" "")
759 
        (match_operand:SF 1 "const_double_operand" ""))]
760 
  "reload_completed"
761 
  [(const_int 0)]
762 
  "
763 
{
764 
  REAL_VALUE_TYPE rv;
765 
  HOST_WIDE_INT value;
766 
  HOST_WIDE_INT lo, hi;
767 
  rtx out;
768 
 
769 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
770 
  REAL_VALUE_TO_TARGET_SINGLE (rv, value);
771 
 
772 
  lo = value & 0xffff;
773 
  hi = trunc_int_for_mode (value & 0xffff0000, SImode);
774 
 
775 
  out = gen_rtx_REG (SImode, REGNO (operands[0]));
776 
  emit_move_insn (out, GEN_INT (hi));
777 
  if (lo != 0)
778 
    emit_insn (gen_iorsi3 (out, out, GEN_INT (lo)));
779 
  DONE;
780 
}")
781 
 
782 
(define_expand "movdf"
783 
  [(set (match_operand:DF 0 "" "")
784 
        (match_operand:DF 1 "" ""))]
785 
  ""
786 
  "
787 
{
788 
  if (mep_expand_mov (operands, DFmode))
789 
    DONE;
790 
}")
791 
 
792 
(define_insn "*movdf_internal_32"
793 
  [(set (match_operand:DF 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
794 
        (match_operand:DF 1 "general_operand"     "rFm,r,c,r,er,r,ex,U,em"))]
795 
  "TARGET_32BIT_CR_REGS && mep_mov_ok (operands, DFmode)"
796 
  "#"
797 
  [(set_attr "slot" "multi")])
798 
 
799 
(define_insn "*movdf_internal_64"
800 
  [(set (match_operand:DF 0 "mep_movdest_operand" "= r,m,r,c,r,er,ex,em,U")
801 
        (match_operand:DF 1 "general_operand"     "rFm,r,c,r,er,r,ex,U,em"))]
802 
  "TARGET_64BIT_CR_REGS && mep_mov_ok (operands, DFmode)"
803 
  "@
804 
   #
805 
   #
806 
   #
807 
   #
808 
   #
809 
   #
810 
   %<\\t%0, %M1
811 
   lmcp\\t%0, %1
812 
   smcp\\t%1, %0"
813 
  [(set_attr "slot"  "multi,multi,multi,multi,multi,multi,*,*,*")
814 
   (set_attr "intrinsic" "*,*,*,*,*,*,cmov,*,*")
815 
   (set_attr "memop" "*,*,*,*,*,*,*,cop1,cop0")
816 
   (set_attr "stall" "*,*,*,*,*,*,*,load,store")])
817 
 
818 
(define_split
819 
  [(set (match_operand:DF 0 "mep_movdest_operand" "")
820 
        (match_operand:DF 1 "general_operand" ""))]
821 
  "reload_completed && mep_multi_slot (insn)"
822 
  [(set (match_dup 2) (match_dup 3))
823 
   (set (match_dup 4) (match_dup 5))]
824 
  "mep_split_wide_move (operands, DFmode);")
825 
 
826 
 
827 
(define_insn "*lbcpa"
828 
  [(set (match_operand:SI 0 "register_operand" "=em")
829 
        (sign_extend:SI (mem:QI (match_operand:SI 2 "register_operand" "1"))))
830 
   (set (match_operand:SI 1 "register_operand" "=r")
831 
        (plus:SI (match_dup 2)
832 
                 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")))]
833 
  "TARGET_COP && reload_completed"
834 
  "lbcpa\t%0, (%1+), %3"
835 
  [(set_attr "length" "4")
836 
   (set_attr "stall" "load")])
837 
 
838 
(define_insn "*sbcpa"
839 
  [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
840 
        (match_operand:QI 2 "register_operand" "em"))
841 
   (set (match_operand:SI 0 "register_operand" "=r")
842 
        (plus:SI (match_dup 1)
843 
                 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")))]
844 
  "TARGET_COP && reload_completed"
845 
  "sbcpa\t%2, (%0+), %3"
846 
  [(set_attr "length" "4")
847 
   (set_attr "stall" "store")])
848 
 
849 
(define_insn "*lhcpa"
850 
  [(set (match_operand:SI 0 "register_operand" "=em")
851 
        (sign_extend:SI (mem:HI (match_operand:SI 2 "register_operand" "1"))))
852 
   (set (match_operand:SI 1 "register_operand" "=r")
853 
        (plus:SI (match_dup 2)
854 
                 (match_operand:SI 3 "cgen_h_sint_7a2_immediate" "")))]
855 
  "TARGET_COP && reload_completed"
856 
  "lhcpa\t%0, (%1+), %3"
857 
  [(set_attr "length" "4")
858 
   (set_attr "stall" "load")])
859 
 
860 
(define_insn "*shcpa"
861 
  [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
862 
        (match_operand:HI 2 "register_operand" "em"))
863 
   (set (match_operand:SI 0 "register_operand" "=r")
864 
        (plus:SI (match_dup 1)
865 
                 (match_operand:SI 3 "cgen_h_sint_7a2_immediate" "")))]
866 
  "TARGET_COP && reload_completed"
867 
  "shcpa\t%2, (%0+), %3"
868 
  [(set_attr "length" "4")
869 
   (set_attr "stall" "store")])
870 
 
871 
(define_insn "*lwcpi"
872 
  [(set (match_operand:SI 0 "register_operand" "=em")
873 
        (mem:SI (match_operand:SI 2 "register_operand" "1")))
874 
   (set (match_operand:SI 1 "register_operand" "=r")
875 
        (plus:SI (match_dup 2)
876 
                 (const_int 4)))]
877 
  "TARGET_COP && reload_completed"
878 
  "lwcpi\t%0, (%1+)"
879 
  [(set_attr "length" "2")
880 
   (set_attr "stall" "load")])
881 
 
882 
(define_insn "*lwcpa"
883 
  [(set (match_operand:SI 0 "register_operand" "=em")
884 
        (mem:SI (match_operand:SI 2 "register_operand" "1")))
885 
   (set (match_operand:SI 1 "register_operand" "=r")
886 
        (plus:SI (match_dup 2)
887 
                 (match_operand:SI 3 "cgen_h_sint_6a4_immediate" "")))]
888 
  "TARGET_COP && reload_completed"
889 
  "lwcpa\t%0, (%1+), %3"
890 
  [(set_attr "length" "4")
891 
   (set_attr "stall" "load")])
892 
 
893 
(define_insn "*swcpi"
894 
  [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
895 
        (match_operand:SI 2 "register_operand" "em"))
896 
   (set (match_operand:SI 0 "register_operand" "=r")
897 
        (plus:SI (match_dup 1)
898 
                 (const_int 4)))]
899 
  "TARGET_COP && reload_completed"
900 
  "swcpi\t%2, (%0+)"
901 
  [(set_attr "length" "2")
902 
   (set_attr "stall" "store")])
903 
 
904 
(define_insn "*swcpa"
905 
  [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
906 
        (match_operand:SI 2 "register_operand" "em"))
907 
   (set (match_operand:SI 0 "register_operand" "=r")
908 
        (plus:SI (match_dup 1)
909 
                 (match_operand:SI 3 "cgen_h_sint_6a4_immediate" "")))]
910 
  "TARGET_COP && reload_completed"
911 
  "swcpa\t%2, (%0+), %3"
912 
  [(set_attr "length" "4")
913 
   (set_attr "stall" "store")])
914 
 
915 
(define_peephole2
916 
  [(set (match_operand:SI 0 "register_operand" "")
917 
        (plus:SI (match_dup 0)
918 
                 (match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")))]
919 
  "TARGET_COP && mep_use_post_modify_p (insn, operands[0], operands[1])"
920 
  [(const_int 0)]
921 
{
922 
  emit_note (NOTE_INSN_DELETED);
923 
  DONE;
924 
})
925 
 
926 
;; ::::::::::::::::::::
927 
;; ::
928 
;; :: Reloads
929 
;; ::
930 
;; ::::::::::::::::::::
931 
 
932 
(define_expand "reload_insi"
933 
  [(set (match_operand:SI 0 "mep_reload_operand" "")
934 
        (match_operand:SI 1 "mep_reload_operand" "r"))
935 
   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
936 
  ""
937 
  "
938 
{
939 
  mep_expand_reload (operands, SImode);
940 
  DONE;
941 
}")
942 
 
943 
(define_expand "reload_outsi"
944 
  [(set (match_operand:SI 0 "mep_reload_operand" "=r")
945 
        (match_operand:SI 1 "mep_reload_operand" ""))
946 
   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
947 
  ""
948 
  "
949 
{
950 
  mep_expand_reload (operands, SImode);
951 
  DONE;
952 
}")
953 
 
954 
 
955 
;; ::::::::::::::::::::
956 
;; ::
957 
;; :: Conversions
958 
;; ::
959 
;; ::::::::::::::::::::
960 
 
961 
(define_insn "extendqisi2"
962 
  [(set (match_operand:SI 0 "register_operand" "=r,r,em")
963 
        (sign_extend:SI
964 
          (match_operand:QI 1 "nonimmediate_operand" "0,m,Y")))]
965 
  ""
966 
  "@
967 
   extb\\t%0
968 
   lb\\t%0, %1
969 
   lbcpa\\t%0, %P1"
970 
  [(set_attr "length" "2,*,*")
971 
   (set_attr "stall"  "*,load,load")
972 
   (set_attr "memop"  "*,core1,cop1")])
973 
 
974 
(define_insn "extendhisi2"
975 
  [(set (match_operand:SI 0 "register_operand" "=r,r,em")
976 
        (sign_extend:SI
977 
          (match_operand:HI 1 "nonimmediate_operand" "0,m,Y")))]
978 
  ""
979 
  "@
980 
   exth\\t%0
981 
   lh\\t%0, %1
982 
   lhcpa\\t%0, %P1"
983 
  [(set_attr "length" "2,*,*")
984 
   (set_attr "stall"  "*,load,load")
985 
   (set_attr "memop"  "*,core1,cop1")])
986 
 
987 
(define_insn "zero_extendqisi2"
988 
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
989 
        (zero_extend:SI
990 
          (match_operand:QI 1 "nonimmediate_operand" "0,r,m")))]
991 
  ""
992 
  "@
993 
   extub\\t%0
994 
   and3\\t%0, %1, 255
995 
   lbu\\t%0, %1"
996 
  [(set_attr "length" "2,4,*")
997 
   (set_attr "stall" "*,*,load")
998 
   (set_attr "memop"  "*,*,core1")])
999 
 
1000 
(define_insn "zero_extendhisi2"
1001 
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1002 
        (zero_extend:SI
1003 
          (match_operand:HI 1 "nonimmediate_operand" "0,r,m")))]
1004 
  ""
1005 
  "@
1006 
   extuh\\t%0
1007 
   and3\\t%0, %1, 65535
1008 
   lhu\\t%0, %1"
1009 
  [(set_attr "length" "2,4,*")
1010 
   (set_attr "stall" "*,*,load")
1011 
   (set_attr "memop"  "*,*,core1")])
1012 
 
1013 
;; ::::::::::::::::::::
1014 
;; ::
1015 
;; :: 32 bit Integer arithmetic
1016 
;; ::
1017 
;; ::::::::::::::::::::
1018 
 
1019 
(define_insn "addsi3"
1020 
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1021 
        (plus:SI (match_operand:SI 1 "register_operand" "%r,0,r")
1022 
                 (match_operand:SI 2 "mep_add_operand" "r,L,IT")))]
1023 
  ""
1024 
  "@
1025 
   add3\\t%0, %1, %2
1026 
   add\\t%0, %2
1027 
   add3\\t%0, %1, %I2"
1028 
  [(set (attr "length")
1029 
        (if_then_else (eq_attr "alternative" "2")
1030 
          (if_then_else (and (match_operand:SI 1 "mep_sp_operand" "")
1031 
                             (match_operand:SI 2 "mep_imm7a4_operand" ""))
1032 
            (const_int 2)
1033 
            (const_int 4))
1034 
          (const_int 2)))])
1035 
 
1036 
;; The intention here is to combine the 16-bit add with the 16-bit
1037 
;; move to create a 32-bit add.  It's the same size, but takes one
1038 
;; less machine cycle.  It will happen to match a 32-bit add with a
1039 
;; 16-bit move also, but gcc shouldn't be doing that ;)
1040 
(define_peephole2
1041 
  [(set (match_operand:SI 0 "register_operand" "")
1042 
        (plus:SI (match_operand:SI 1 "register_operand" "")
1043 
                 (match_operand:SI 2 "immediate_operand" "")))
1044 
   (set (match_operand:SI 3 "register_operand" "")
1045 
        (match_operand:SI 4 "register_operand" ""))]
1046 
  "REGNO (operands[0]) == REGNO (operands[1])
1047 
   && REGNO (operands[0]) == REGNO (operands[4])
1048 
   && GR_REGNO_P (REGNO (operands[3]))
1049 
   && dead_or_set_p (peep2_next_insn (1), operands[4])"
1050 
  [(set (match_dup 3)
1051 
        (plus:SI (match_dup 1)
1052 
                 (match_dup 2)))]
1053 
  "")
1054 
 
1055 
(define_insn "subsi3"
1056 
  [(set (match_operand:SI 0 "register_operand" "=r")
1057 
        (minus:SI (match_operand:SI 1 "register_operand" "0")
1058 
                  (match_operand:SI 2 "register_operand" "r")))]
1059 
  ""
1060 
  "sub\\t%0, %2"
1061 
  [(set_attr "length" "2")])
1062 
 
1063 
(define_expand "mulsi3"
1064 
  [(set (match_operand:SI 0 "register_operand" "")
1065 
        (mult:SI (match_operand:SI 1 "register_operand" "")
1066 
                 (match_operand:SI 2 "register_operand" "")))]
1067 
  "TARGET_OPT_MULT || TARGET_COPRO_MULT"
1068 
{
1069 
  emit_insn (gen_mulsi3_1 (operands[0], operands[1], operands[2]));
1070 
  DONE;
1071 
})
1072 
 
1073 
;; Generated by mep_reuse_lo_p when no GPR destination is needed.
1074 
(define_insn "mulsi3_lo"
1075 
  [(set (match_operand:SI 0 "mep_lo_operand" "=l")
1076 
        (mult:SI (match_operand:SI 1 "register_operand" "r")
1077 
                 (match_operand:SI 2 "register_operand" "r")))
1078 
   (clobber (match_scratch:SI 3 "=h"))]
1079 
  "TARGET_OPT_MULT && reload_completed"
1080 
  "mul\\t%1, %2"
1081 
  [(set_attr "length" "2")
1082 
   (set_attr "stall" "mul")])
1083 
 
1084 
;; Generated by mep_reuse_lo_p when both destinations of a mulr
1085 
;; are needed.
1086 
(define_insn "mulsi3r"
1087 
  [(set (match_operand:SI 0 "mep_lo_operand" "=l")
1088 
        (mult:SI (match_operand:SI 2 "register_operand" "1")
1089 
                 (match_operand:SI 3 "register_operand" "r")))
1090 
   (set (match_operand:SI 1 "register_operand" "=r")
1091 
        (mult:SI (match_dup 2)
1092 
                 (match_dup 3)))
1093 
   (clobber (match_scratch:SI 4 "=h"))]
1094 
  "TARGET_OPT_MULT && reload_completed"
1095 
  "mulr\\t%2, %3"
1096 
  [(set_attr "length" "2")
1097 
   (set_attr "stall" "mulr")])
1098 
 
1099 
(define_insn "mulsi3_1"
1100 
  [(set (match_operand:SI 0 "register_operand" "=r")
1101 
        (mult:SI (match_operand:SI 1 "register_operand" "%0")
1102 
                 (match_operand:SI 2 "register_operand" "r")))
1103 
   (clobber (match_scratch:SI 3 "=l"))
1104 
   (clobber (match_scratch:SI 4 "=h"))]
1105 
  "TARGET_OPT_MULT"
1106 
  "mulr\\t%1, %2"
1107 
  [(set_attr "length" "2")
1108 
   (set_attr "stall" "mulr")])
1109 
 
1110 
(define_expand "mulsidi3"
1111 
  [(set (match_operand:DI 0 "register_operand" "")
1112 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
1113 
                 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
1114 
  "TARGET_OPT_MULT"
1115 
  "
1116 
{
1117 
  rtx hi = gen_reg_rtx (SImode);
1118 
  rtx lo = gen_reg_rtx (SImode);
1119 
 
1120 
  emit_insn (gen_mulsidi3_i (hi, lo, operands[1], operands[2]));
1121 
  emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
1122 
  emit_move_insn (gen_highpart (SImode, operands[0]), hi);
1123 
  DONE;
1124 
}")
1125 
 
1126 
(define_insn "mulsidi3_i"
1127 
  [(set (match_operand:SI 0 "mep_hi_operand" "=h")
1128 
        (truncate:SI
1129 
         (lshiftrt:DI
1130 
          (mult:DI (sign_extend:DI
1131 
                    (match_operand:SI 2 "register_operand" "r"))
1132 
                   (sign_extend:DI
1133 
                    (match_operand:SI 3 "register_operand" "r")))
1134 
          (const_int 32))))
1135 
   (set (match_operand:SI 1 "mep_lo_operand" "=l")
1136 
        (mult:SI (match_dup 2)
1137 
                 (match_dup 3)))]
1138 
  "TARGET_OPT_MULT"
1139 
  "mul\\t%2, %3"
1140 
  [(set_attr "length" "2")
1141 
   (set_attr "stall" "mul")])
1142 
 
1143 
(define_insn "smulsi3_highpart"
1144 
  [(set (match_operand:SI 0 "mep_hi_operand" "=h")
1145 
        (truncate:SI
1146 
         (lshiftrt:DI
1147 
          (mult:DI (sign_extend:DI
1148 
                    (match_operand:SI 1 "register_operand" "r"))
1149 
                   (sign_extend:DI
1150 
                    (match_operand:SI 2 "register_operand" "r")))
1151 
          (const_int 32))))
1152 
   (clobber (reg:SI LO_REGNO))]
1153 
  "TARGET_OPT_MULT"
1154 
  "mul\\t%1, %2"
1155 
  [(set_attr "length" "2")
1156 
   (set_attr "stall" "mul")])
1157 
 
1158 
(define_expand "umulsidi3"
1159 
  [(set (match_operand:DI 0 "mep_hi_operand" "")
1160 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
1161 
                 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))]
1162 
  "TARGET_OPT_MULT"
1163 
  "
1164 
{
1165 
  rtx hi = gen_reg_rtx (SImode);
1166 
  rtx lo = gen_reg_rtx (SImode);
1167 
 
1168 
  emit_insn (gen_umulsidi3_i (hi, lo, operands[1], operands[2]));
1169 
  emit_move_insn (gen_lowpart (SImode, operands[0]), lo);
1170 
  emit_move_insn (gen_highpart (SImode, operands[0]), hi);
1171 
  DONE;
1172 
}")
1173 
 
1174 
(define_insn "umulsidi3_i"
1175 
  [(set (match_operand:SI 0 "mep_hi_operand" "=h")
1176 
        (truncate:SI
1177 
         (lshiftrt:DI
1178 
          (mult:DI (zero_extend:DI
1179 
                    (match_operand:SI 2 "register_operand" "r"))
1180 
                   (zero_extend:DI
1181 
                    (match_operand:SI 3 "register_operand" "r")))
1182 
          (const_int 32))))
1183 
   (set (match_operand:SI 1 "mep_lo_operand" "=l")
1184 
        (mult:SI (match_dup 2)
1185 
                 (match_dup 3)))]
1186 
  "TARGET_OPT_MULT"
1187 
  "mulu\\t%2, %3"
1188 
  [(set_attr "length" "2")
1189 
   (set_attr "stall" "mul")])
1190 
 
1191 
(define_insn "umulsi3_highpart"
1192 
  [(set (match_operand:SI 0 "mep_hi_operand" "=h")
1193 
        (truncate:SI
1194 
         (lshiftrt:DI
1195 
          (mult:DI (zero_extend:DI
1196 
                    (match_operand:SI 1 "register_operand" "r"))
1197 
                   (zero_extend:DI
1198 
                    (match_operand:SI 2 "register_operand" "r")))
1199 
          (const_int 32))))
1200 
   (clobber (reg:SI LO_REGNO))]
1201 
  "TARGET_OPT_MULT"
1202 
  "mulu %1, %2"
1203 
  [(set_attr "length" "2")
1204 
   (set_attr "stall" "mul")])
1205 
 
1206 
;; These two don't currently match because we don't have an adddi3 pattern.
1207 
(define_insn "*smultdi_and_add"
1208 
  [(set (match_operand:DI 0 "mep_hi_operand" "=d")
1209 
        (plus:DI (mult:DI (zero_extend:DI
1210 
                           (match_operand:SI 1 "register_operand" "r"))
1211 
                          (zero_extend:DI
1212 
                           (match_operand:SI 2 "register_operand" "r")))
1213 
                 (match_operand:DI 3 "mep_hi_operand" "0")))]
1214 
  "TARGET_OPT_MULT && TARGET_BIG_ENDIAN"
1215 
  "maddu\\t%1, %2"
1216 
  [(set_attr "length" "4")
1217 
   (set_attr "stall" "mul")])
1218 
 
1219 
(define_insn "*umultdi_and_add"
1220 
  [(set (match_operand:DI 0 "mep_hi_operand" "=d")
1221 
        (plus:DI (mult:DI (sign_extend:DI
1222 
                           (match_operand:SI 1 "register_operand" "r"))
1223 
                          (sign_extend:DI
1224 
                           (match_operand:SI 2 "register_operand" "r")))
1225 
                 (match_operand:DI 3 "mep_hi_operand" "0")))]
1226 
  "TARGET_OPT_MULT && TARGET_BIG_ENDIAN"
1227 
  "madd\\t%1, %2"
1228 
  [(set_attr "length" "4")
1229 
   (set_attr "stall" "mul")])
1230 
 
1231 
;; A pattern for 'r1 = r2 * r3 + r4'.  There are three possible
1232 
;; implementations:
1233 
;;
1234 
;;    (1) 'mulr;add3'.  This is usually the best choice if the instruction
1235 
;;        is not part of a natural multiply-accumulate chain.  It has the
1236 
;;        same latency as 'stc;maddr' but doesn't tie up $lo for as long.
1237 
;;
1238 
;;    (2) 'madd'.  This is the best choice if the instruction is in the
1239 
;;        middle of a natural multiply-accumulate chain.  r4 will already
1240 
;;        be in $lo and r1 will also be needed in $lo.
1241 
;;
1242 
;;    (3) 'maddr'.  This is the best choice if the instruction is at the
1243 
;;        end of a natural multiply-accumulate chain.  r4 will be in $lo
1244 
;;        but r1 will be needed in a GPR.
1245 
;;
1246 
;; In theory, we could put all the alternatives into a single pattern and
1247 
;; leave the register allocator to choose between them.  However, this can
1248 
;; sometimes produce poor results in practice.
1249 
;;
1250 
;; This pattern therefore describes a general GPR-to-GPR operation that
1251 
;; has a slight preference for cases in which operands 0 and 1 are tied.
1252 
;; After reload, we try to rewrite the patterns using peephole2s (if
1253 
;; enabled), falling back on define_splits if that fails.  See also
1254 
;; mep_reuse_lo_p.
1255 
(define_insn "maddsi3"
1256 
  [(set (match_operand:SI 0 "register_operand" "=r,r")
1257 
        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%0,r")
1258 
                          (match_operand:SI 2 "register_operand" "r,r"))
1259 
                 (match_operand:SI 3 "register_operand" "r,r")))
1260 
   (clobber (match_scratch:SI 4 "=l,l"))
1261 
   (clobber (match_scratch:SI 5 "=h,h"))]
1262 
  "TARGET_OPT_MULT"
1263 
  "#"
1264 
  [(set_attr "length" "8")
1265 
   (set_attr "stall" "mulr")])
1266 
 
1267 
;; Implement maddsi3s using maddr if operand 3 is already available in $lo.
1268 
(define_peephole2
1269 
  [(parallel
1270 
        [(set (match_operand:SI 0 "register_operand" "")
1271 
              (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1272 
                                (match_operand:SI 2 "register_operand" ""))
1273 
                       (match_operand:SI 3 "register_operand" "")))
1274 
         (clobber (match_scratch:SI 4 ""))
1275 
         (clobber (match_scratch:SI 5 ""))])]
1276 
  "TARGET_OPT_MULT
1277 
   && reload_completed
1278 
   && mep_reuse_lo_p (operands[4], operands[3], insn,
1279 
                      !rtx_equal_p (operands[1], operands[3])
1280 
                      && !rtx_equal_p (operands[2], operands[3])
1281 
                      && (rtx_equal_p (operands[0], operands[3])
1282 
                          || peep2_reg_dead_p (1, operands[3])))"
1283 
  [(parallel
1284 
        [(set (match_dup 4)
1285 
              (plus:SI (mult:SI (match_dup 0)
1286 
                                (match_dup 2))
1287 
                       (match_dup 4)))
1288 
         (set (match_dup 0)
1289 
              (plus:SI (mult:SI (match_dup 0)
1290 
                                (match_dup 2))
1291 
                       (match_dup 4)))
1292 
         (clobber (match_dup 5))])]
1293 
  "operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);")
1294 
 
1295 
;; This splitter implements maddsi3 as "mulr;add3".  It only works if
1296 
;; operands 0 and 3 are distinct, since operand 0 is clobbered before
1297 
;; operand 3 is used.
1298 
(define_split
1299 
  [(set (match_operand:SI 0 "register_operand" "")
1300 
        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1301 
                          (match_operand:SI 2 "register_operand" ""))
1302 
                 (match_operand:SI 3 "register_operand" "")))
1303 
   (clobber (match_scratch:SI 4 ""))
1304 
   (clobber (match_scratch:SI 5 ""))]
1305 
  "TARGET_OPT_MULT
1306 
   && reload_completed
1307 
   && !rtx_equal_p (operands[0], operands[3])"
1308 
  [(parallel [(set (match_dup 0)
1309 
                   (mult:SI (match_dup 0)
1310 
                            (match_dup 2)))
1311 
              (clobber (match_dup 4))
1312 
              (clobber (match_dup 5))])
1313 
   (set (match_dup 0)
1314 
        (plus:SI (match_dup 0)
1315 
                 (match_dup 3)))]
1316 
  "operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);")
1317 
 
1318 
;; This is the fallback splitter for maddsi3.  It moves operand 3 into
1319 
;; $lo and then uses maddr.
1320 
(define_split
1321 
  [(set (match_operand:SI 0 "register_operand" "")
1322 
        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1323 
                          (match_operand:SI 2 "register_operand" ""))
1324 
                 (match_operand:SI 3 "register_operand" "")))
1325 
   (clobber (match_scratch:SI 4 ""))
1326 
   (clobber (match_scratch:SI 5 ""))]
1327 
  "TARGET_OPT_MULT
1328 
   && reload_completed"
1329 
  [(parallel [(set (match_dup 4)
1330 
                   (plus:SI (mult:SI (match_dup 0)
1331 
                                     (match_dup 2))
1332 
                            (match_dup 4)))
1333 
              (set (match_dup 0)
1334 
                   (plus:SI (mult:SI (match_dup 0)
1335 
                                     (match_dup 2))
1336 
                            (match_dup 4)))
1337 
              (clobber (match_dup 5))])]
1338 
{
1339 
  emit_move_insn (operands[4], operands[3]);
1340 
  operands[2] = mep_mulr_source (0, operands[0], operands[1], operands[2]);
1341 
})
1342 
 
1343 
;; Remove unnecessary stcs to $lo.  This cleans up the moves generated
1344 
;; by earlier calls to mep_reuse_lo_p.
1345 
(define_peephole2
1346 
  [(set (match_operand:SI 0 "mep_lo_operand" "")
1347 
        (match_operand:SI 1 "register_operand" ""))]
1348 
  "TARGET_OPT_MULT
1349 
   && mep_reuse_lo_p (operands[0], operands[1], insn,
1350 
                      peep2_reg_dead_p (1, operands[1]))"
1351 
  [(const_int 0)]
1352 
{
1353 
  emit_note (NOTE_INSN_DELETED);
1354 
  DONE;
1355 
})
1356 
 
1357 
(define_insn "maddsi3_lo"
1358 
  [(set (match_operand:SI 0 "mep_lo_operand" "=l")
1359 
        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
1360 
                          (match_operand:SI 2 "register_operand" "r"))
1361 
                 (match_operand:SI 3 "mep_lo_operand" "0")))
1362 
   (clobber (match_scratch:SI 4 "=h"))]
1363 
  "TARGET_OPT_MULT && reload_completed"
1364 
  "madd\\t%1, %2"
1365 
  [(set_attr "length" "4")
1366 
   (set_attr "stall" "mul")])
1367 
 
1368 
(define_insn "maddsi3r"
1369 
  [(set (match_operand:SI 0 "mep_lo_operand" "=l")
1370 
        (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "1")
1371 
                          (match_operand:SI 3 "register_operand" "r"))
1372 
                 (match_operand:SI 4 "register_operand" "0")))
1373 
   (set (match_operand:SI 1 "register_operand" "=r")
1374 
        (plus:SI (mult:SI (match_dup 2)
1375 
                          (match_dup 3))
1376 
                 (match_dup 4)))
1377 
   (clobber (match_scratch:SI 5 "=h"))]
1378 
  "TARGET_OPT_MULT && reload_completed"
1379 
  "maddr\\t%2, %3"
1380 
  [(set_attr "length" "4")
1381 
   (set_attr "stall" "mulr")])
1382 
 
1383 
(define_insn "*shift_1_or_2_and_add"
1384 
  [(set (match_operand:SI 0 "mep_r0_operand" "=z")
1385 
        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
1386 
                          (match_operand:SI 2 "mep_slad_operand" "n"))
1387 
                 (match_operand:SI 3 "register_operand" "r")))]
1388 
  ""
1389 
  "sl%b2ad3\\t%0, %1, %3"
1390 
  [(set_attr "length" "2")
1391 
   (set_attr "stall" "int2")])
1392 
 
1393 
(define_insn "divmodsi4"
1394 
  [(set (match_operand:SI 0 "mep_lo_operand" "=l")
1395 
        (div:SI (match_operand:SI 1 "register_operand" "r")
1396 
                (match_operand:SI 2 "register_operand" "r")))
1397 
   (set (match_operand:SI 3 "mep_hi_operand" "=h")
1398 
        (mod:SI (match_dup 1)
1399 
                (match_dup 2)))]
1400 
  "TARGET_OPT_DIV"
1401 
  "div\\t%1, %2"
1402 
  [(set_attr "length" "2")
1403 
   (set_attr "stall" "div")
1404 
   (set_attr "may_trap" "yes")])
1405 
 
1406 
(define_insn "udivmodsi4"
1407 
  [(set (match_operand:SI 0 "mep_lo_operand" "=l")
1408 
        (udiv:SI (match_operand:SI 1 "register_operand" "r")
1409 
                 (match_operand:SI 2 "register_operand" "r")))
1410 
   (set (match_operand:SI 3 "mep_hi_operand" "=h")
1411 
        (umod:SI (match_dup 1)
1412 
                (match_dup 2)))]
1413 
  "TARGET_OPT_DIV"
1414 
  "divu\\t%1, %2"
1415 
  [(set_attr "length" "2")
1416 
   (set_attr "stall" "div")
1417 
   (set_attr "may_trap" "yes")])
1418 
 
1419 
(define_insn "negsi2"
1420 
  [(set (match_operand:SI 0 "register_operand" "=r")
1421 
        (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1422 
  ""
1423 
  "neg\\t%0, %1"
1424 
  [(set_attr "length" "2")])
1425 
 
1426 
;; We have "absolute difference between two regs" which isn't quite
1427 
;; what gcc is expecting.
1428 
(define_expand "abssi2"
1429 
  [(set (match_dup 2) (const_int 0))
1430 
   (set (match_operand:SI 0 "register_operand" "")
1431 
        (abs:SI (minus:SI (match_operand:SI 1 "register_operand" "")
1432 
                          (match_dup 2))
1433 
                ))]
1434 
  "TARGET_OPT_ABSDIFF"
1435 
  "operands[2] = gen_reg_rtx (SImode);")
1436 
 
1437 
(define_insn "*absdiff"
1438 
  [(set (match_operand:SI 0 "register_operand" "=r")
1439 
        (abs:SI (minus:SI (match_operand:SI 1 "register_operand" "0")
1440 
                          (match_operand:SI 2 "register_operand" "r"))))]
1441 
  "TARGET_OPT_ABSDIFF"
1442 
  "abs\\t%0, %2"
1443 
  [(set_attr "length" "4")])
1444 
 
1445 
(define_split
1446 
  [(set (match_operand:SI 0 "register_operand" "")
1447 
        (abs:SI (plus:SI (match_operand:SI 1 "register_operand" "")
1448 
                         (match_operand:SI 2 "immediate_operand" ""))))
1449 
   (clobber (match_operand:SI 3 "register_operand" ""))]
1450 
  "!reload_completed"
1451 
  [(set (match_dup 3)
1452 
        (match_dup 4))
1453 
   (set (match_operand:SI 0 "register_operand" "")
1454 
        (abs:SI (minus:SI (match_operand:SI 1 "register_operand" "")
1455 
                          (match_dup 3))))]
1456 
  "operands[4] = GEN_INT (-INTVAL (operands[2]));")
1457 
 
1458 
(define_insn "sminsi3"
1459 
  [(set (match_operand:SI 0 "register_operand" "=r")
1460 
        (smin:SI (match_operand:SI 1 "register_operand" "0")
1461 
                 (match_operand:SI 2 "nonmemory_operand" "r")))]
1462 
  "TARGET_OPT_MINMAX"
1463 
  "min\\t%0, %2"
1464 
  [(set_attr "length" "4")])
1465 
 
1466 
(define_insn "smaxsi3"
1467 
  [(set (match_operand:SI 0 "register_operand" "=r")
1468 
        (smax:SI (match_operand:SI 1 "register_operand" "0")
1469 
                 (match_operand:SI 2 "nonmemory_operand" "r")))]
1470 
  "TARGET_OPT_MINMAX"
1471 
  "max\\t%0, %2"
1472 
  [(set_attr "length" "4")])
1473 
 
1474 
(define_insn "uminsi3"
1475 
  [(set (match_operand:SI 0 "register_operand" "=r")
1476 
        (umin:SI (match_operand:SI 1 "register_operand" "0")
1477 
                 (match_operand:SI 2 "nonmemory_operand" "r")))]
1478 
  "TARGET_OPT_MINMAX"
1479 
  "minu\\t%0, %2"
1480 
  [(set_attr "length" "4")])
1481 
 
1482 
(define_insn "umaxsi3"
1483 
  [(set (match_operand:SI 0 "register_operand" "=r")
1484 
        (umax:SI (match_operand:SI 1 "register_operand" "0")
1485 
                 (match_operand:SI 2 "nonmemory_operand" "r")))]
1486 
  "TARGET_OPT_MINMAX"
1487 
  "maxu\\t%0, %2"
1488 
  [(set_attr "length" "4")])
1489 
 
1490 
;; Average:  a = (b+c+1)>>1
1491 
(define_insn "*averagesi3"
1492 
  [(set (match_operand:SI 0 "register_operand" "=r")
1493 
        (ashiftrt:SI (plus:SI (plus:SI
1494 
                                (match_operand:SI 1 "register_operand" "0")
1495 
                                (match_operand:SI 2 "register_operand" "r"))
1496 
                              (const_int 1))
1497 
                     (const_int 1)))]
1498 
  "TARGET_OPT_AVERAGE"
1499 
  "ave\\t%0, %2"
1500 
  [(set_attr "length" "4")])
1501 
 
1502 
;; clip support
1503 
 
1504 
(define_insn "clip_maxmin"
1505 
  [(set (match_operand:SI 0 "register_operand" "=r")
1506 
        (smax:SI (smin:SI (match_operand:SI 1 "register_operand" "0")
1507 
                          (match_operand:SI 2 "immediate_operand" "n"))
1508 
                 (match_operand:SI 3 "immediate_operand" "n")))]
1509 
  "mep_allow_clip (operands[2], operands[3], 1)"
1510 
  "clip\\t%0, %B2"
1511 
  [(set_attr "length" "4")])
1512 
 
1513 
(define_insn "clip_minmax"
1514 
  [(set (match_operand:SI 0 "register_operand" "=r")
1515 
        (smin:SI (smax:SI (match_operand:SI 1 "register_operand" "0")
1516 
                          (match_operand:SI 2 "immediate_operand" "n"))
1517 
                 (match_operand:SI 3 "immediate_operand" "n")))]
1518 
  "mep_allow_clip (operands[3], operands[2], 1)"
1519 
  "clip\\t%0, %B3"
1520 
  [(set_attr "length" "4")])
1521 
 
1522 
(define_insn "clipu_maxmin"
1523 
  [(set (match_operand:SI 0 "register_operand" "=r")
1524 
        (smax:SI (smin:SI (match_operand:SI 1 "register_operand" "0")
1525 
                          (match_operand:SI 2 "immediate_operand" "n"))
1526 
                 (match_operand:SI 3 "immediate_operand" "n")))]
1527 
  "mep_allow_clip (operands[2], operands[3], 0)"
1528 
  "clipu\\t%0, %U2"
1529 
  [(set_attr "length" "4")])
1530 
 
1531 
(define_insn "clipu_minmax"
1532 
  [(set (match_operand:SI 0 "register_operand" "=r")
1533 
        (smin:SI (smax:SI (match_operand:SI 1 "register_operand" "0")
1534 
                          (match_operand:SI 2 "immediate_operand" "n"))
1535 
                 (match_operand:SI 3 "immediate_operand" "n")))]
1536 
  "mep_allow_clip (operands[3], operands[2], 0)"
1537 
  "clipu\\t%0, %U3"
1538 
  [(set_attr "length" "4")])
1539 
 
1540 
;; ::::::::::::::::::::
1541 
;; ::
1542 
;; :: 32 bit Integer Shifts and Rotates
1543 
;; ::
1544 
;; ::::::::::::::::::::
1545 
 
1546 
(define_insn "ashlsi3"
1547 
  [(set (match_operand:SI 0 "register_operand" "=r,z")
1548 
        (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
1549 
                   (match_operand:SI 2 "nonmemory_operand" "rM,M")))]
1550 
  ""
1551 
  "@
1552 
   sll\\t%0, %2
1553 
   sll3\\t%0, %1, %2"
1554 
  [(set_attr "length" "2,2")
1555 
   (set_attr "shiftop" "operand2")])
1556 
 
1557 
(define_insn "ashrsi3"
1558 
  [(set (match_operand:SI 0 "register_operand" "=r")
1559 
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
1560 
                     (match_operand:SI 2 "nonmemory_operand" "rM")))]
1561 
  ""
1562 
  "sra\\t%0, %2"
1563 
  [(set_attr "length" "2")
1564 
   (set_attr "shiftop" "operand2")])
1565 
 
1566 
(define_insn "lshrsi3"
1567 
  [(set (match_operand:SI 0 "register_operand" "=r")
1568 
        (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
1569 
                     (match_operand:SI 2 "nonmemory_operand" "rM")))]
1570 
  ""
1571 
  "srl\\t%0, %2"
1572 
  [(set_attr "length" "2")
1573 
   (set_attr "shiftop" "operand2")])
1574 
 
1575 
;; ::::::::::::::::::::
1576 
;; ::
1577 
;; :: 32 Bit Integer Logical operations
1578 
;; ::
1579 
;; ::::::::::::::::::::
1580 
 
1581 
(define_insn "andsi3"
1582 
  [(set (match_operand:SI 0 "register_operand" "=r,r")
1583 
        (and:SI (match_operand:SI 1 "register_operand" "%0,r")
1584 
                (match_operand:SI 2 "nonmemory_operand" "r,J")))]
1585 
  ""
1586 
  "@
1587 
   and\\t%0, %2
1588 
   and3\\t%0, %1, %J2"
1589 
  [(set_attr "length" "2,4")])
1590 
 
1591 
(define_insn "iorsi3"
1592 
  [(set (match_operand:SI 0 "register_operand" "=r,r")
1593 
        (ior:SI (match_operand:SI 1 "register_operand" "%0,r")
1594 
                (match_operand:SI 2 "nonmemory_operand" "r,J")))]
1595 
  ""
1596 
  "@
1597 
   or\\t%0, %2
1598 
   or3\\t%0, %1, %J2"
1599 
  [(set_attr "length" "2,4")])
1600 
 
1601 
(define_insn "xorsi3"
1602 
  [(set (match_operand:SI 0 "register_operand" "=r,r")
1603 
        (xor:SI (match_operand:SI 1 "register_operand" "%0,r")
1604 
                (match_operand:SI 2 "nonmemory_operand" "r,J")))]
1605 
  ""
1606 
  "@
1607 
   xor\\t%0, %2
1608 
   xor3\\t%0, %1, %J2"
1609 
  [(set_attr "length" "2,4")])
1610 
 
1611 
(define_expand "one_cmplsi2"
1612 
  [(set (match_operand:SI 0 "register_operand" "")
1613 
        (not:SI (match_operand:SI 1 "register_operand" "")))]
1614 
  ""
1615 
  "operands[2] = operands[1];
1616 
   ")
1617 
 
1618 
;; No separate insn for this; use NOR
1619 
(define_insn "*one_cmplsi3_internal"
1620 
  [(set (match_operand:SI 0 "register_operand" "=r")
1621 
        (not:SI (match_operand:SI 1 "register_operand" "0")))]
1622 
  ""
1623 
  "nor\\t%0, %0"
1624 
  [(set_attr "length" "2")])
1625 
 
1626 
;; ::::::::::::::::::::
1627 
;; ::
1628 
;; :: Bit Manipulation
1629 
;; ::
1630 
;; ::::::::::::::::::::
1631 
 
1632 
(define_insn "*bitop_be"
1633 
  [(set (match_operand:QI 0 "mep_Y_operand" "=Y")
1634 
        (subreg:QI (match_operator:SI 3 "mep_bit_operator"
1635 
                        [(subreg:SI (match_operand:QI 1 "mep_Y_operand" "0") 0)
1636 
                         (match_operand 2 "immediate_operand" "n")])
1637 
                   3)
1638 
        )]
1639 
  "TARGET_BIG_ENDIAN && TARGET_OPT_BITOPS
1640 
   && rtx_equal_p (operands[0], operands[1])"
1641 
  "b%L3m\\t%0, %b2"
1642 
  [(set_attr "length" "2")])
1643 
 
1644 
(define_insn "*bitop_le"
1645 
  [(set (match_operand:QI 0 "mep_Y_operand" "=Y")
1646 
        (subreg:QI (match_operator:SI 3 "mep_bit_operator"
1647 
                        [(subreg:SI (match_operand:QI 1 "mep_Y_operand" "0") 0)
1648 
                         (match_operand 2 "immediate_operand" "n")])
1649 
                   0)
1650 
        )]
1651 
  "!TARGET_BIG_ENDIAN && TARGET_OPT_BITOPS
1652 
   && rtx_equal_p (operands[0], operands[1])"
1653 
  "b%L3m\\t%0, %b2"
1654 
  [(set_attr "length" "2")])
1655 
 
1656 
(define_insn "btstm"
1657 
  [(set (match_operand:SI 0 "mep_r0_operand" "=z")
1658 
        (and:SI (subreg:SI (match_operand:QI 1 "mep_Y_operand" "Y") 0)
1659 
                (match_operand 2 "immediate_operand" "n"))
1660 
        )]
1661 
  "TARGET_OPT_BITOPS && mep_bit_position_p (operands[2], 1)"
1662 
  "btstm\\t%0, %1, %b2"
1663 
  [(set_attr "length" "2")])
1664 
 
1665 
(define_insn "tas"
1666 
  [(parallel [(set (match_operand:SI 0 "mep_r0_operand" "=z")
1667 
                   (zero_extend:SI (match_operand:QI 1 "mep_Y_operand" "+Y")))
1668 
              (set (match_dup 1)
1669 
                   (const_int 1))
1670 
              ]
1671 
             )]
1672 
  "TARGET_OPT_BITOPS"
1673 
  "tas\\t%0, %1"
1674 
  [(set_attr "length" "2")])
1675 
 
1676 
(define_peephole2
1677 
  [(set (match_operand:SI 0 "mep_r0_operand" "")
1678 
        (zero_extend:SI (match_operand:QI 1 "mep_Y_operand" "")))
1679 
   (set (match_operand:QI 2 "register_operand" "")
1680 
        (const_int 1))
1681 
   (set (match_dup 1)
1682 
        (match_dup 2))
1683 
   ]
1684 
  "TARGET_OPT_BITOPS"
1685 
  [(parallel [(set (match_dup 0)
1686 
                   (zero_extend:SI (match_dup 1)))
1687 
              (set (match_dup 1)
1688 
                   (const_int 1))
1689 
              ])]
1690 
  "")
1691 
 
1692 
(define_peephole2
1693 
  [(set (match_operand:SI 0 "mep_r0_operand" "")
1694 
        (sign_extend:SI (match_operand:QI 1 "mep_Y_operand" "")))
1695 
   (set (match_operand:QI 2 "register_operand" "")
1696 
        (const_int 1))
1697 
   (set (match_dup 1)
1698 
        (match_dup 2))
1699 
   ]
1700 
  "TARGET_OPT_BITOPS"
1701 
  [(parallel [(set (match_dup 0)
1702 
                   (zero_extend:SI (match_dup 1)))
1703 
              (set (match_dup 1)
1704 
                   (const_int 1))
1705 
              ])
1706 
   (set (match_dup 0)
1707 
        (sign_extend:SI (match_dup 3)))]
1708 
  "operands[3] = gen_lowpart (QImode, operands[0]);")
1709 
 
1710 
 
1711 
;; ::::::::::::::::::::
1712 
;; ::
1713 
;; :: Conditional branches and stores
1714 
;; ::
1715 
;; ::::::::::::::::::::
1716 
 
1717 
(define_expand "cbranchsi4"
1718 
  [(set (pc)
1719 
        (if_then_else (match_operator 0 "ordered_comparison_operator"
1720 
                                      [(match_operand:SI 1 "register_operand" "")
1721 
                                       (match_operand:SI 2 "nonmemory_operand" "")])
1722 
                      (label_ref (match_operand 3 "" ""))
1723 
                      (pc)))]
1724 
  ""
1725 
  "emit_jump_insn (gen_branch_true (operands[3],
1726 
                               mep_expand_cbranch (operands)));
1727 
   DONE;")
1728 
 
1729 
(define_expand "branch_true"
1730 
  [(set (pc)
1731 
        (if_then_else (match_operand 1 "" "")
1732 
                      (label_ref (match_operand 0 "" ""))
1733 
                      (pc)))]
1734 
  ""
1735 
  "")
1736 
 
1737 
(define_expand "cstoresi4"
1738 
  [(set (match_operand:SI 0 "register_operand" "")
1739 
        (match_operator:SI 1 "ordered_comparison_operator"
1740 
                           [(match_operand:SI 2 "register_operand" "")
1741 
                            (match_operand:SI 3 "nonmemory_operand" "")]))]
1742 
  ""
1743 
  "if (mep_expand_setcc (operands)) DONE; else FAIL;")
1744 
 
1745 
;; ------------------------------------------------------------
1746 
 
1747 
(define_insn "*slt"
1748 
  [(set (match_operand:SI 0 "register_operand" "=z,z,r")
1749 
        (lt:SI (match_operand:SI 1 "register_operand" "r,r,r")
1750 
            (match_operand:SI 2 "nonmemory_operand" "r,M,I")))]
1751 
  ""
1752 
  "slt3\\t%0, %1, %2"
1753 
  [(set_attr "length" "2,2,4")])
1754 
 
1755 
(define_insn "*sltu"
1756 
  [(set (match_operand:SI 0 "register_operand" "=z,z,r")
1757 
        (ltu:SI (match_operand:SI 1 "register_operand" "r,r,r")
1758 
             (match_operand:SI 2 "nonmemory_operand" "r,M,J")))]
1759 
  ""
1760 
  "sltu3\\t%0, %1, %2"
1761 
  [(set_attr "length" "2,2,4")])
1762 
 
1763 
(define_insn "*bcpeq_true"
1764 
  [(set (pc)
1765 
        (if_then_else (eq:SI (reg:SI CBCR_REGNO)
1766 
                             (const_int 0))
1767 
                      (label_ref (match_operand 0 "" ""))
1768 
                      (pc)))]
1769 
  ""
1770 
  "bcpeq\t0, %l0"
1771 
  [(set_attr "length" "4")])
1772 
 
1773 
(define_insn "*bcpeq_false"
1774 
  [(set (pc)
1775 
        (if_then_else (eq:SI (reg:SI CBCR_REGNO)
1776 
                             (const_int 0))
1777 
                      (pc)
1778 
                      (label_ref (match_operand 0 "" ""))))]
1779 
  ""
1780 
  "bcpne\t0, %l0"
1781 
  [(set_attr "length" "4")])
1782 
 
1783 
(define_insn "*bcpne_true"
1784 
  [(set (pc)
1785 
        (if_then_else (ne:SI (reg:SI CBCR_REGNO)
1786 
                             (const_int 0))
1787 
                      (label_ref (match_operand 0 "" ""))
1788 
                      (pc)))]
1789 
  ""
1790 
  "bcpne\t0, %l0"
1791 
  [(set_attr "length" "4")])
1792 
 
1793 
(define_insn "*bcpne_false"
1794 
  [(set (pc)
1795 
        (if_then_else (ne:SI (reg:SI CBCR_REGNO)
1796 
                             (const_int 0))
1797 
                      (pc)
1798 
                      (label_ref (match_operand 0 "" ""))))]
1799 
  ""
1800 
  "bcpeq\t0, %l0"
1801 
  [(set_attr "length" "4")])
1802 
 
1803 
;; ??? The lengths here aren't correct, since no attempt it made to
1804 
;; find "beqz" in the 256-byte range.  However, this should not affect
1805 
;; bundling, since we never run core branches in parallel.
1806 
 
1807 
(define_insn "mep_beq_true"
1808 
  [(set (pc)
1809 
        (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
1810 
                          (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
1811 
                      (label_ref (match_operand 2 "" ""))
1812 
                      (pc)))]
1813 
  ""
1814 
  "* return mep_emit_cbranch (operands, 0);"
1815 
  [(set_attr "length" "4")]  )
1816 
 
1817 
(define_insn "*beq_false"
1818 
  [(set (pc)
1819 
        (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
1820 
                          (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
1821 
                      (pc)
1822 
                      (label_ref (match_operand 2 "" ""))))]
1823 
  ""
1824 
  "* return mep_emit_cbranch (operands, 1);"
1825 
  [(set_attr "length" "4")])
1826 
 
1827 
(define_insn "mep_bne_true"
1828 
  [(set (pc)
1829 
        (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
1830 
                          (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
1831 
                      (label_ref (match_operand 2 "" ""))
1832 
                      (pc)))]
1833 
  ""
1834 
  "* return mep_emit_cbranch (operands, 1); "
1835 
  [(set_attr "length" "4")])
1836 
 
1837 
(define_insn "*bne_false"
1838 
  [(set (pc)
1839 
        (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
1840 
                          (match_operand:SI 1 "mep_reg_or_imm4_operand" "rN"))
1841 
                      (pc)
1842 
                      (label_ref (match_operand 2 "" ""))))]
1843 
  ""
1844 
  "* return mep_emit_cbranch (operands, 0); "
1845 
  [(set_attr "length" "4")])
1846 
 
1847 
(define_insn "mep_blti"
1848 
  [(set (pc)
1849 
        (if_then_else (lt (match_operand:SI 0 "register_operand" "r")
1850 
                          (match_operand:SI 1 "mep_imm4_operand" "N"))
1851 
                      (label_ref (match_operand 2 "" ""))
1852 
                      (pc)))]
1853 
  ""
1854 
  "blti\\t%0, %1, %l2"
1855 
  [(set_attr "length" "4")])
1856 
 
1857 
(define_insn "*bgei"
1858 
  [(set (pc)
1859 
        (if_then_else (ge (match_operand:SI 0 "register_operand" "r")
1860 
                          (match_operand:SI 1 "mep_imm4_operand" "N"))
1861 
                      (label_ref (match_operand 2 "" ""))
1862 
                      (pc)))]
1863 
  ""
1864 
  "bgei\\t%0, %1, %l2"
1865 
  [(set_attr "length" "4")])
1866 
 
1867 
;; ::::::::::::::::::::
1868 
;; ::
1869 
;; :: Call and branch instructions
1870 
;; ::
1871 
;; ::::::::::::::::::::
1872 
 
1873 
(define_expand "call"
1874 
  [(parallel [(call (match_operand:QI 0 "" "")
1875 
                    (match_operand:SI 1 "" ""))
1876 
              (use (match_operand:SI 2 "" ""))
1877 
              (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1878 
              ])]
1879 
  ""
1880 
  "
1881 
{
1882 
  mep_expand_call (operands, 0);
1883 
  DONE;
1884 
}")
1885 
 
1886 
(define_insn "call_internal"
1887 
  [(call (mem (match_operand:SI 0 "mep_call_address_operand" "R,r"))
1888 
         (match_operand:SI 1 "" ""))
1889 
   (use (match_operand:SI 2 "const_int_operand" ""))
1890 
   (use (match_operand:SI 3 "mep_tp_operand" "b,b"))
1891 
   (use (match_operand:SI 4 "mep_gp_operand" "v,v"))
1892 
   (clobber (reg:SI LP_REGNO))
1893 
   (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1894 
  ]
1895 
  ""
1896 
{
1897 
  static char const pattern[2][2][8] =
1898 
  {
1899 
    { "bsrv\t%0", "jsrv\t%0" },
1900 
    { "bsr\t%0", "jsr\t%0" }
1901 
  };
1902 
 
1903 
  return pattern[mep_vliw_mode_match (operands[2])][which_alternative];
1904 
}
1905 
  [(set_attr "length" "4,2")])
1906 
 
1907 
(define_expand "sibcall"
1908 
  [(parallel [(call (match_operand:QI 0 "" "")
1909 
                    (match_operand:SI 1 "" ""))
1910 
              (use (match_operand:SI 2 "" ""))
1911 
              (use (reg:SI LP_REGNO))
1912 
              (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1913 
              ])]
1914 
  ""
1915 
  "")
1916 
 
1917 
(define_insn "*sibcall_internal"
1918 
  [(call (mem (match_operand:SI 0 "mep_nearsym_operand" "s"))
1919 
         (match_operand:SI 1 "" ""))
1920 
   (use (match_operand:SI 2 "const_int_operand" ""))
1921 
   (use (reg:SI LP_REGNO))
1922 
   (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1923 
  ]
1924 
  "SIBLING_CALL_P (insn)"
1925 
{
1926 
  if (mep_vliw_jmp_match (operands[2]))
1927 
    return "jmp\t%0";
1928 
  else if (mep_vliw_mode_match (operands[2]))
1929 
    return
1930 
        "movu   $0, %0\n\
1931 
        jmp     $0";
1932 
  else
1933 
    return
1934 
        "ldc    $12, $lp\n\
1935 
        movh    $11, %%hi(%0)\n\
1936 
        xor3    $12, $12, 1\n\
1937 
        add3    $11, $11, %%lo(%0+1)\n\
1938 
        stc     $12, $lp\n\
1939 
        jmp     $11";
1940 
}
1941 
  [(set_attr "length" "48")
1942 
   (set_attr "slot" "multi")])
1943 
 
1944 
(define_expand "call_value"
1945 
  [(parallel [(set (match_operand 0 "" "")
1946 
                   (call (match_operand:QI 1 "" "")
1947 
                         (match_operand:SI 2 "" "")))
1948 
              (use (match_operand:SI 3 "" ""))
1949 
              (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1950 
              ])]
1951 
  ""
1952 
  "
1953 
{
1954 
  mep_expand_call (operands, 1);
1955 
  DONE;
1956 
}")
1957 
 
1958 
(define_insn "call_value_internal"
1959 
  [(set (match_operand 0 "register_operand" "=rx,rx")
1960 
        (call (mem:SI (match_operand:SI 1 "mep_call_address_operand" "R,r"))
1961 
              (match_operand:SI 2 "" "")))
1962 
   (use (match_operand:SI 3 "const_int_operand" ""))
1963 
   (use (match_operand:SI 4 "mep_tp_operand" "b,b"))
1964 
   (use (match_operand:SI 5 "mep_gp_operand" "v,v"))
1965 
   (clobber (reg:SI LP_REGNO))
1966 
   (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1967 
  ]
1968 
  ""
1969 
{
1970 
  static char const pattern[2][2][8] =
1971 
  {
1972 
    { "bsrv\t%1", "jsrv\t%1" },
1973 
    { "bsr\t%1", "jsr\t%1" }
1974 
  };
1975 
 
1976 
  return pattern[mep_vliw_mode_match (operands[3])][which_alternative];
1977 
}
1978 
  [(set_attr "length" "4,2")])
1979 
 
1980 
(define_expand "sibcall_value"
1981 
  [(parallel [(set (match_operand 0 "" "")
1982 
                   (call (match_operand:QI 1 "" "")
1983 
                         (match_operand:SI 2 "" "")))
1984 
              (use (match_operand:SI 3 "" ""))
1985 
              (use (reg:SI LP_REGNO))
1986 
              (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1987 
              ])]
1988 
  ""
1989 
  "")
1990 
 
1991 
(define_insn "*sibcall_value_internal"
1992 
  [(set (match_operand 0 "register_operand" "=rx")
1993 
        (call (mem (match_operand:SI 1 "mep_nearsym_operand" "s"))
1994 
              (match_operand:SI 2 "" "")))
1995 
   (use (match_operand:SI 3 "const_int_operand" ""))
1996 
   (use (reg:SI LP_REGNO))
1997 
   (clobber (reg:SI REGSAVE_CONTROL_TEMP))
1998 
  ]
1999 
  "SIBLING_CALL_P (insn)"
2000 
{
2001 
  if (mep_vliw_jmp_match (operands[3]))
2002 
    return "jmp\t%1";
2003 
  else if (mep_vliw_mode_match (operands[3]))
2004 
    return
2005 
        "movu   $0, %1\n\
2006 
        jmp     $0";
2007 
  else
2008 
    return
2009 
        "ldc    $12, $lp\n\
2010 
        movh    $11, %%hi(%1)\n\
2011 
        xor3    $12, $12, 1\n\
2012 
        add3    $11, $11, %%lo(%1+1)\n\
2013 
        stc     $12, $lp\n\
2014 
        jmp     $11";
2015 
}
2016 
  [(set_attr "length" "48")
2017 
   (set_attr "slot" "multi")])
2018 
 
2019 
(define_insn "return_internal"
2020 
  [(return)
2021 
   (use (match_operand:SI 0 "register_operand" ""))]
2022 
  ""
2023 
  "* return (REGNO (operands[0]) == LP_REGNO) ? \"ret\" : \"jmp\\t%0\";"
2024 
  [(set_attr "length" "2")
2025 
   (set_attr "stall" "ret")])
2026 
 
2027 
(define_insn "eh_return_internal"
2028 
  [(return)
2029 
   (use (reg:SI 10))
2030 
   (use (reg:SI 11))
2031 
   (use (reg:SI LP_REGNO))
2032 
   (clobber (reg:SI REGSAVE_CONTROL_TEMP))
2033 
  ]
2034 
  ""
2035 
  "ret"
2036 
  [(set_attr "length" "2")
2037 
   (set_attr "stall" "ret")])
2038 
 
2039 
;; The assembler replaces short jumps with long jumps as needed.
2040 
(define_insn "jump"
2041 
  [(set (pc) (label_ref (match_operand 0 "" "")))]
2042 
  ""
2043 
  "bra\\t%l0"
2044 
  [(set_attr "length" "4")])
2045 
 
2046 
(define_insn "indirect_jump"
2047 
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2048 
  ""
2049 
  "jmp\\t%0"
2050 
  [(set_attr "length" "2")])
2051 
 
2052 
(define_insn "tablejump"
2053 
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2054 
   (use (label_ref (match_operand 1 "" "")))]
2055 
  ""
2056 
  "jmp\\t%0"
2057 
  [(set_attr "length" "2")])
2058 
 
2059 
 
2060 
;; ::::::::::::::::::::
2061 
;; ::
2062 
;; :: Low Overhead Looping
2063 
;; ::
2064 
;; ::::::::::::::::::::
2065 
 
2066 
;; This insn is volatile because we'd like it to stay in its original
2067 
;; position, just before the loop header.  If it stays there, we might
2068 
;; be able to convert it into a "repeat" insn.
2069 
(define_insn "doloop_begin_internal"
2070 
  [(set (match_operand:SI 0 "register_operand" "=r")
2071 
        (unspec_volatile:SI
2072 
         [(match_operand:SI 1 "register_operand" "0")
2073 
          (match_operand 2 "const_int_operand" "")] UNS_REPEAT_BEG))]
2074 
  ""
2075 
  { gcc_unreachable (); }
2076 
  [(set_attr "length" "4")])
2077 
 
2078 
(define_expand "doloop_begin"
2079 
  [(use (match_operand 0 "register_operand" ""))
2080 
   (use (match_operand:QI 1 "const_int_operand" ""))
2081 
   (use (match_operand:QI 2 "const_int_operand" ""))
2082 
   (use (match_operand:QI 3 "const_int_operand" ""))]
2083 
  "!profile_arc_flag && TARGET_OPT_REPEAT"
2084 
  "if (INTVAL (operands[3]) > 1)
2085 
     FAIL;
2086 
   mep_emit_doloop (operands, 0);
2087 
   DONE;
2088 
  ")
2089 
 
2090 
(define_insn "doloop_end_internal"
2091 
  [(set (pc)
2092 
        (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,cxy,*m")
2093 
                          (const_int 0))
2094 
                      (label_ref (match_operand 1 "" ""))
2095 
                      (pc)))
2096 
   (set (match_dup 0)
2097 
        (plus:SI (match_dup 0)
2098 
                 (const_int -1)))
2099 
   (unspec [(match_operand 2 "const_int_operand" "")] UNS_REPEAT_END)
2100 
   (clobber (match_scratch:SI 3 "=X,&r,&r"))]
2101 
  ""
2102 
  { gcc_unreachable (); }
2103 
  ;; Worst case length:
2104 
  ;;
2105 
  ;;      lw ,  4
2106 
  ;;      add ,-1               2
2107 
  ;;      sw ,  4
2108 
  ;;      jmp           4
2109 
  ;; 1f:
2110 
  [(set_attr "length" "14")
2111 
   (set_attr "slot" "multi")])
2112 
 
2113 
(define_expand "doloop_end"
2114 
  [(use (match_operand 0 "nonimmediate_operand" ""))
2115 
   (use (match_operand:QI 1 "const_int_operand" ""))
2116 
   (use (match_operand:QI 2 "const_int_operand" ""))
2117 
   (use (match_operand:QI 3 "const_int_operand" ""))
2118 
   (use (label_ref (match_operand 4 "" "")))]
2119 
  "!profile_arc_flag && TARGET_OPT_REPEAT"
2120 
  "if (INTVAL (operands[3]) > 1)
2121 
     FAIL;
2122 
   if (GET_CODE (operands[0]) == REG && GET_MODE (operands[0]) != SImode)
2123 
     FAIL;
2124 
   mep_emit_doloop (operands, 1);
2125 
   DONE;
2126 
  ")
2127 
 
2128 
(define_insn "repeat"
2129 
  [(set (reg:SI RPC_REGNO)
2130 
        (unspec:SI [(match_operand:SI 0 "mep_r0_15_operand" "r")
2131 
                    (match_operand:SI 1 "" "")]
2132 
                   UNS_REPEAT_BEG))]
2133 
  ""
2134 
  "repeat\\t%0,%l1"
2135 
  [(set_attr "length" "4")])
2136 
 
2137 
(define_insn "repeat_end"
2138 
  [(unspec [(const_int 0)] UNS_REPEAT_END)]
2139 
  ""
2140 
  "# repeat end"
2141 
  [(set_attr "length" "0")])
2142 
 
2143 
(define_insn "erepeat"
2144 
  [(unspec [(match_operand 0 "" "")] UNS_EREPEAT_BEG)]
2145 
  ""
2146 
  "erepeat\\t%l0"
2147 
  [(set_attr "length" "4")])
2148 
 
2149 
(define_insn "erepeat_end"
2150 
  [(unspec [(const_int 0)] UNS_EREPEAT_END)]
2151 
  ""
2152 
  "# erepeat end"
2153 
  [(set_attr "length" "0")
2154 
   (set_attr "slot" "multi")])
2155 
 
2156 
 
2157 
;; ::::::::::::::::::::
2158 
;; ::
2159 
;; :: Prologue and Epilogue instructions
2160 
;; ::
2161 
;; ::::::::::::::::::::
2162 
 
2163 
(define_expand "prologue"
2164 
  [(const_int 1)]
2165 
  ""
2166 
  "
2167 
{
2168 
  mep_expand_prologue ();
2169 
  DONE;
2170 
}")
2171 
 
2172 
(define_expand "epilogue"
2173 
  [(return)]
2174 
  ""
2175 
  "
2176 
{
2177 
  mep_expand_epilogue ();
2178 
  DONE;
2179 
}")
2180 
 
2181 
(define_expand "eh_return"
2182 
  [(use (match_operand:SI 0 "register_operand" "r"))]
2183 
  ""
2184 
  "
2185 
{
2186 
  mep_expand_eh_return (operands);
2187 
  DONE;
2188 
}")
2189 
 
2190 
(define_insn_and_split "eh_epilogue"
2191 
  [(unspec [(match_operand:SI 0 "register_operand" "r")] UNS_EH_EPILOGUE)
2192 
   (use (reg:SI LP_REGNO))]
2193 
  ""
2194 
  "#"
2195 
  "epilogue_completed"
2196 
  [(const_int 1)]
2197 
  "mep_emit_eh_epilogue (operands); DONE;"
2198 
  [(set_attr "slot" "multi")])
2199 
 
2200 
(define_expand "sibcall_epilogue"
2201 
  [(const_int 0)]
2202 
  ""
2203 
  "
2204 
{
2205 
  mep_expand_sibcall_epilogue ();
2206 
  DONE;
2207 
}")
2208 
 
2209 
(define_insn "mep_bb_trace_ret"
2210 
  [(unspec_volatile [(const_int 0)] UNS_BB_TRACE_RET)]
2211 
  ""
2212 
  "* return mep_emit_bb_trace_ret ();"
2213 
  [(set_attr "slot" "multi")])
2214 
 
2215 
(define_insn "mep_disable_int"
2216 
  [(unspec_volatile [(const_int 0)] UNS_DISABLE_INT)]
2217 
  ""
2218 
  "di"
2219 
  [(set_attr "length" "2")])
2220 
 
2221 
(define_insn "mep_enable_int"
2222 
  [(unspec_volatile [(const_int 0)] UNS_ENABLE_INT)]
2223 
  ""
2224 
  "ei"
2225 
  [(set_attr "length" "2")])
2226 
 
2227 
(define_insn "mep_reti"
2228 
  [(return)
2229 
   (unspec_volatile [(const_int 0)] UNS_RETI)]
2230 
  ""
2231 
  "reti"
2232 
  [(set_attr "length" "2")])
2233 
 
2234 
;; ::::::::::::::::::::
2235 
;; ::
2236 
;; :: Miscellaneous instructions
2237 
;; ::
2238 
;; ::::::::::::::::::::
2239 
 
2240 
(define_insn "nop"
2241 
  [(const_int 0)]
2242 
  ""
2243 
  "nop"
2244 
  [(set_attr "length" "2")])
2245 
 
2246 
(define_insn "nop32"
2247 
  [(const_int 1)]
2248 
  ""
2249 
  "or3\\t$0, $0, 0"
2250 
  [(set_attr "length" "4")])
2251 
 
2252 
(define_insn "blockage"
2253 
  [(unspec_volatile [(const_int 0)] UNS_BLOCKAGE)]
2254 
  ""
2255 
  ""
2256 
  [(set_attr "length" "0")
2257 
   (set_attr "slot" "multi")])
2258 
 
2259 
 
2260 
(define_insn "djmark"
2261 
  [(unspec_volatile [(const_int 0)] 999)]
2262 
  ""
2263 
  "# dj"
2264 
  [(set_attr "length" "0")
2265 
   (set_attr "slot" "multi")])
2266 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.