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jeremybenn |
;; DFA-based pipeline description for MIPS32 model 74k.
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;; Contributed by MIPS Technologies and CodeSourcery.
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;;
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;; Reference:
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;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006"
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;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006"
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;;
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu")
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(define_cpu_unit "r74k_mul" "r74k_mdu_pipe")
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(define_cpu_unit "r74k_alu" "r74k_alu_pipe")
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(define_cpu_unit "r74k_agen" "r74k_agen_pipe")
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(define_cpu_unit "r74k_fpu_arith" "r74k_fpu")
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(define_cpu_unit "r74k_fpu_ldst" "r74k_fpu")
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;; --------------------------------------------------------------
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;; Producers
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;; --------------------------------------------------------------
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;; ALU: Logicals/Arithmetics
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;; - Logicals, move (addu/addiu with rt = 0), Set less than,
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;; sign extend - 1 cycle
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(define_insn_reservation "r74k_int_logical" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "logical,move,signext,slt"))
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"r74k_alu")
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;; - Arithmetics - 2 cycles
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(define_insn_reservation "r74k_int_arith" 2
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "arith,const,shift,clz"))
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"r74k_alu")
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(define_insn_reservation "r74k_int_nop" 0
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "nop"))
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"nothing")
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(define_insn_reservation "r74k_int_cmove" 4
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "condmove"))
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"r74k_agen*2")
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;; MDU: fully pipelined multiplier
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;; mult - delivers result to hi/lo in 4 cycle (pipelined)
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(define_insn_reservation "r74k_int_mult" 4
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "imul"))
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"r74k_alu+r74k_mul")
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;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
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(define_insn_reservation "r74k_int_madd" 4
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "imadd"))
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"r74k_alu+r74k_mul")
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;; mul - delivers result to general register in 7 cycles
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(define_insn_reservation "r74k_int_mul3" 7
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "imul3"))
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"r74k_alu+r74k_mul")
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;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
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(define_insn_reservation "r74k_int_mfhilo" 7
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "mfhilo"))
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"r74k_alu+r74k_mul")
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;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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(define_insn_reservation "r74k_int_mthilo" 7
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "mthilo"))
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"r74k_alu+r74k_mul")
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;; div - default to 50 cycles for 32bit operands. Faster for 8 bit,
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;; but is tricky to identify.
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(define_insn_reservation "r74k_int_div" 50
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "idiv"))
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"r74k_alu+r74k_mul*50")
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;; call
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(define_insn_reservation "r74k_int_call" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "call"))
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"r74k_agen")
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;; branch/jump
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(define_insn_reservation "r74k_int_jump" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "branch,jump"))
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"r74k_agen")
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;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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;; prefetch: prefetch, prefetchx
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(define_insn_reservation "r74k_int_load" 3
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "load,prefetch,prefetchx"))
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"r74k_agen")
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;; stores
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(define_insn_reservation "r74k_int_store" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(and (eq_attr "type" "store")
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(eq_attr "mode" "!unknown")))
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"r74k_agen")
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;; Unknowns - Currently these include blockage, consttable and alignment
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;; rtls. They do not really affect scheduling latency, (blockage
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;; affects scheduling via log links, but not used here).
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;;
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(define_insn_reservation "r74k_unknown" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "unknown"))
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"r74k_alu")
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(define_insn_reservation "r74k_multi" 10
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(eq_attr "type" "multi"))
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"(r74k_alu+r74k_agen)*10")
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;; --------------------------------------------------------------
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;; Bypass to Consumer
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;; --------------------------------------------------------------
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;; load->next use : 3 cycles (Default)
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;; load->load base: 4 cycles
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;; load->store base: 4 cycles
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(define_bypass 4 "r74k_int_load" "r74k_int_load")
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(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
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;; logical/move/slt/signext->next use : 1 cycles (Default)
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;; logical/move/slt/signext->load base: 2 cycles
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;; logical/move/slt/signext->store base: 2 cycles
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(define_bypass 2 "r74k_int_logical" "r74k_int_load")
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(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
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;; arith->next use : 2 cycles (Default)
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;; arith->load base: 3 cycles
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;; arith->store base: 3 cycles
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(define_bypass 3 "r74k_int_arith" "r74k_int_load")
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(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")
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;; cmove->next use : 4 cycles (Default)
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;; cmove->load base: 5 cycles
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;; cmove->store base: 5 cycles
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(define_bypass 5 "r74k_int_cmove" "r74k_int_load")
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(define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p")
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;; mult/madd/msub->int_mfhilo : 4 cycles (default)
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;; mult->madd/msub : 1 cycles
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;; madd/msub->madd/msub : 1 cycles
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(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
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"mips_linked_madd_p")
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(define_bypass 1 "r74k_int_madd" "r74k_int_madd"
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"mips_linked_madd_p")
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;; --------------------------------------------------------------
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;; Floating Point Instructions
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;; --------------------------------------------------------------
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;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio.
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;; fadd, fabs, fneg,
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(define_insn_reservation "r74kf1_1_fadd" 4
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(and (eq_attr "cpu" "74kf1_1")
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(eq_attr "type" "fadd,fabs,fneg"))
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"r74k_fpu_arith")
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(define_insn_reservation "r74kf2_1_fadd" 8
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(and (eq_attr "cpu" "74kf2_1")
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(eq_attr "type" "fadd,fabs,fneg"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fadd" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fadd,fabs,fneg"))
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"r74k_fpu_arith")
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;; fmove, fcmove
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(define_insn_reservation "r74kf1_1_fmove" 4
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(and (eq_attr "cpu" "74kf1_1")
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(eq_attr "type" "fmove"))
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"r74k_fpu_arith")
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(define_insn_reservation "r74kf2_1_fmove" 8
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(and (eq_attr "cpu" "74kf2_1")
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(eq_attr "type" "fmove"))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fmove" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fmove"))
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"r74k_fpu_arith")
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;; fload
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(define_insn_reservation "r74kf1_1_fload" 4
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(and (eq_attr "cpu" "74kf1_1")
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(eq_attr "type" "fpload,fpidxload"))
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"r74k_agen+r74k_fpu_ldst")
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(define_insn_reservation "r74kf2_1_fload" 8
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(and (eq_attr "cpu" "74kf2_1")
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(eq_attr "type" "fpload,fpidxload"))
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"r74k_agen+(r74k_fpu_ldst*2)")
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(define_insn_reservation "r74kf3_2_fload" 6
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fpload,fpidxload"))
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"r74k_agen+r74k_fpu_ldst")
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;; fstore
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(define_insn_reservation "r74kf1_1_fstore" 1
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(and (eq_attr "cpu" "74kf1_1")
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(eq_attr "type" "fpstore,fpidxstore"))
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"r74k_agen+r74k_fpu_ldst")
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(define_insn_reservation "r74kf2_1_fstore" 2
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(and (eq_attr "cpu" "74kf2_1")
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(eq_attr "type" "fpstore,fpidxstore"))
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"r74k_agen+(r74k_fpu_ldst*2)")
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(define_insn_reservation "r74kf3_2_fstore" 1
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(and (eq_attr "cpu" "74kf3_2")
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(eq_attr "type" "fpstore,fpidxstore"))
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"r74k_agen+r74k_fpu_ldst")
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;; fmul, fmadd
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(define_insn_reservation "r74kf1_1_fmul_sf" 4
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(and (eq_attr "cpu" "74kf1_1")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith")
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(define_insn_reservation "r74kf2_1_fmul_sf" 8
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(and (eq_attr "cpu" "74kf2_1")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf3_2_fmul_sf" 6
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"r74k_fpu_arith")
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(define_insn_reservation "r74kf1_1_fmul_df" 5
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(and (eq_attr "cpu" "74kf1_1")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*2")
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(define_insn_reservation "r74kf2_1_fmul_df" 10
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(and (eq_attr "cpu" "74kf2_1")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*4")
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(define_insn_reservation "r74kf3_2_fmul_df" 7
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(and (eq_attr "cpu" "74kf3_2")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"r74k_fpu_arith*2")
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;; fdiv, fsqrt
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| 284 |
|
|
(define_insn_reservation "r74kf1_1_fdiv_sf" 17
|
| 285 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 286 |
|
|
(and (eq_attr "type" "fdiv,fsqrt")
|
| 287 |
|
|
(eq_attr "mode" "SF")))
|
| 288 |
|
|
"r74k_fpu_arith*14")
|
| 289 |
|
|
|
| 290 |
|
|
(define_insn_reservation "r74kf2_1_fdiv_sf" 34
|
| 291 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 292 |
|
|
(and (eq_attr "type" "fdiv,fsqrt")
|
| 293 |
|
|
(eq_attr "mode" "SF")))
|
| 294 |
|
|
"r74k_fpu_arith*28")
|
| 295 |
|
|
|
| 296 |
|
|
(define_insn_reservation "r74kf3_2_fdiv_sf" 25
|
| 297 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 298 |
|
|
(and (eq_attr "type" "fdiv,fsqrt")
|
| 299 |
|
|
(eq_attr "mode" "SF")))
|
| 300 |
|
|
"r74k_fpu_arith*14")
|
| 301 |
|
|
|
| 302 |
|
|
(define_insn_reservation "r74kf1_1_fdiv_df" 32
|
| 303 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 304 |
|
|
(and (eq_attr "type" "fdiv,fsqrt")
|
| 305 |
|
|
(eq_attr "mode" "DF")))
|
| 306 |
|
|
"r74k_fpu_arith*29")
|
| 307 |
|
|
|
| 308 |
|
|
(define_insn_reservation "r74kf2_1_fdiv_df" 64
|
| 309 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 310 |
|
|
(and (eq_attr "type" "fdiv,fsqrt")
|
| 311 |
|
|
(eq_attr "mode" "DF")))
|
| 312 |
|
|
"r74k_fpu_arith*58")
|
| 313 |
|
|
|
| 314 |
|
|
(define_insn_reservation "r74kf3_2_fdiv_df" 48
|
| 315 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 316 |
|
|
(and (eq_attr "type" "fdiv,fsqrt")
|
| 317 |
|
|
(eq_attr "mode" "DF")))
|
| 318 |
|
|
"r74k_fpu_arith*29")
|
| 319 |
|
|
|
| 320 |
|
|
;; frsqrt
|
| 321 |
|
|
(define_insn_reservation "r74kf1_1_frsqrt_sf" 17
|
| 322 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 323 |
|
|
(and (eq_attr "type" "frsqrt")
|
| 324 |
|
|
(eq_attr "mode" "SF")))
|
| 325 |
|
|
"r74k_fpu_arith*14")
|
| 326 |
|
|
|
| 327 |
|
|
(define_insn_reservation "r74kf2_1_frsqrt_sf" 34
|
| 328 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 329 |
|
|
(and (eq_attr "type" "frsqrt")
|
| 330 |
|
|
(eq_attr "mode" "SF")))
|
| 331 |
|
|
"r74k_fpu_arith*28")
|
| 332 |
|
|
|
| 333 |
|
|
(define_insn_reservation "r74kf3_2_frsqrt_sf" 25
|
| 334 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 335 |
|
|
(and (eq_attr "type" "frsqrt")
|
| 336 |
|
|
(eq_attr "mode" "SF")))
|
| 337 |
|
|
"r74k_fpu_arith*14")
|
| 338 |
|
|
|
| 339 |
|
|
(define_insn_reservation "r74kf1_1_frsqrt_df" 36
|
| 340 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 341 |
|
|
(and (eq_attr "type" "frsqrt")
|
| 342 |
|
|
(eq_attr "mode" "DF")))
|
| 343 |
|
|
"r74k_fpu_arith*31")
|
| 344 |
|
|
|
| 345 |
|
|
(define_insn_reservation "r74kf2_1_frsqrt_df" 72
|
| 346 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 347 |
|
|
(and (eq_attr "type" "frsqrt")
|
| 348 |
|
|
(eq_attr "mode" "DF")))
|
| 349 |
|
|
"r74k_fpu_arith*62")
|
| 350 |
|
|
|
| 351 |
|
|
(define_insn_reservation "r74kf3_2_frsqrt_df" 54
|
| 352 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 353 |
|
|
(and (eq_attr "type" "frsqrt")
|
| 354 |
|
|
(eq_attr "mode" "DF")))
|
| 355 |
|
|
"r74k_fpu_arith*31")
|
| 356 |
|
|
|
| 357 |
|
|
;; fcmp
|
| 358 |
|
|
(define_insn_reservation "r74kf1_1_fcmp" 4
|
| 359 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 360 |
|
|
(eq_attr "type" "fcmp"))
|
| 361 |
|
|
"r74k_fpu_arith")
|
| 362 |
|
|
|
| 363 |
|
|
(define_insn_reservation "r74kf2_1_fcmp" 8
|
| 364 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 365 |
|
|
(eq_attr "type" "fcmp"))
|
| 366 |
|
|
"r74k_fpu_arith*2")
|
| 367 |
|
|
|
| 368 |
|
|
(define_insn_reservation "r74kf3_2_fcmp" 6
|
| 369 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 370 |
|
|
(eq_attr "type" "fcmp"))
|
| 371 |
|
|
"r74k_fpu_arith")
|
| 372 |
|
|
|
| 373 |
|
|
;; fcvt
|
| 374 |
|
|
(define_insn_reservation "r74kf1_1_fcvt" 4
|
| 375 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 376 |
|
|
(eq_attr "type" "fcvt"))
|
| 377 |
|
|
"r74k_fpu_arith")
|
| 378 |
|
|
|
| 379 |
|
|
(define_insn_reservation "r74kf2_1_fcvt" 8
|
| 380 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 381 |
|
|
(eq_attr "type" "fcvt"))
|
| 382 |
|
|
"r74k_fpu_arith*2")
|
| 383 |
|
|
|
| 384 |
|
|
(define_insn_reservation "r74kf3_2_fcvt" 6
|
| 385 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 386 |
|
|
(eq_attr "type" "fcvt"))
|
| 387 |
|
|
"r74k_fpu_arith")
|
| 388 |
|
|
|
| 389 |
|
|
;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
|
| 390 |
|
|
(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
|
| 391 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 392 |
|
|
(eq_attr "type" "mtc"))
|
| 393 |
|
|
"r74k_fpu_arith")
|
| 394 |
|
|
|
| 395 |
|
|
(define_insn_reservation "r74kf2_1_fxfer_to_c1" 8
|
| 396 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 397 |
|
|
(eq_attr "type" "mtc"))
|
| 398 |
|
|
"r74k_fpu_arith*2")
|
| 399 |
|
|
|
| 400 |
|
|
(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
|
| 401 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 402 |
|
|
(eq_attr "type" "mtc"))
|
| 403 |
|
|
"r74k_fpu_arith")
|
| 404 |
|
|
|
| 405 |
|
|
(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
|
| 406 |
|
|
(and (eq_attr "cpu" "74kf1_1")
|
| 407 |
|
|
(eq_attr "type" "mfc"))
|
| 408 |
|
|
"r74k_fpu_arith")
|
| 409 |
|
|
|
| 410 |
|
|
(define_insn_reservation "r74kf2_1_fxfer_from_c1" 2
|
| 411 |
|
|
(and (eq_attr "cpu" "74kf2_1")
|
| 412 |
|
|
(eq_attr "type" "mfc"))
|
| 413 |
|
|
"r74k_fpu_arith*2")
|
| 414 |
|
|
|
| 415 |
|
|
(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
|
| 416 |
|
|
(and (eq_attr "cpu" "74kf3_2")
|
| 417 |
|
|
(eq_attr "type" "mfc"))
|
| 418 |
|
|
"r74k_fpu_arith")
|
