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jeremybenn |
;; Copyright (C) 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;
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;; This file contains MIPS instructions that support fixed-point operations.
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;; All supported fixed-point modes
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(define_mode_iterator FIXED [(QQ "") (HQ "") (SQ "") (DQ "TARGET_64BIT")
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(UQQ "") (UHQ "") (USQ "") (UDQ "TARGET_64BIT")
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(HA "") (SA "") (DA "TARGET_64BIT")
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(UHA "") (USA "") (UDA "TARGET_64BIT")])
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;; For signed add/sub with saturation
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(define_mode_iterator ADDSUB [(HQ "") (SQ "") (HA "") (SA "") (V2HQ "")
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(V2HA "")])
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(define_mode_attr addsubfmt [(HQ "ph") (SQ "w") (HA "ph") (SA "w")
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(V2HQ "ph") (V2HA "ph")])
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;; For unsigned add/sub with saturation
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(define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2")
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(UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP")
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(V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")])
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(define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph")
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(V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")])
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;; For signed multiplication with saturation
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(define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP")
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(SQ "ISA_HAS_DSPR2")])
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(define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")])
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(define_insn "add3"
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[(set (match_operand:FIXED 0 "register_operand" "=d")
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(plus:FIXED (match_operand:FIXED 1 "register_operand" "d")
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(match_operand:FIXED 2 "register_operand" "d")))]
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""
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"addu\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "")])
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(define_insn "usadd3"
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[(parallel
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[(set (match_operand:UADDSUB 0 "register_operand" "=d")
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(us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
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(match_operand:UADDSUB 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
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""
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"addu_s.\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "")])
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(define_insn "ssadd3"
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[(parallel
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[(set (match_operand:ADDSUB 0 "register_operand" "=d")
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(ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
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(match_operand:ADDSUB 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
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"ISA_HAS_DSP"
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"addq_s.\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "")])
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(define_insn "sub3"
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[(set (match_operand:FIXED 0 "register_operand" "=d")
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(minus:FIXED (match_operand:FIXED 1 "register_operand" "d")
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(match_operand:FIXED 2 "register_operand" "d")))]
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""
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"subu\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "")])
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(define_insn "ussub3"
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[(parallel
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[(set (match_operand:UADDSUB 0 "register_operand" "=d")
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(us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
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(match_operand:UADDSUB 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
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""
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"subu_s.\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "")])
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(define_insn "sssub3"
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[(parallel
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[(set (match_operand:ADDSUB 0 "register_operand" "=d")
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(ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
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(match_operand:ADDSUB 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
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"ISA_HAS_DSP"
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"subq_s.\t%0,%1,%2"
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[(set_attr "type" "arith")
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(set_attr "mode" "")])
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(define_insn "ssmul3"
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[(parallel
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[(set (match_operand:MULQ 0 "register_operand" "=d")
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(ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
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(match_operand:MULQ 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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""
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"mulq_rs.\t%0,%1,%2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "")])
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(define_insn "ssmaddsqdq4"
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[(parallel
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[(set (match_operand:DQ 0 "register_operand" "=a")
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(ss_plus:DQ
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(ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
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"register_operand" "d"))
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(sat_fract:DQ (match_operand:SQ 2
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"register_operand" "d")))
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(match_operand:DQ 3 "register_operand" "0")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
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UNSPEC_DPAQ_SA_L_W))])]
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"ISA_HAS_DSP && !TARGET_64BIT"
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"dpaq_sa.l.w\t%q0,%1,%2"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "ssmsubsqdq4"
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[(parallel
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[(set (match_operand:DQ 0 "register_operand" "=a")
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(ss_minus:DQ
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(match_operand:DQ 3 "register_operand" "0")
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(ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
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"register_operand" "d"))
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(sat_fract:DQ (match_operand:SQ 2
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"register_operand" "d")))))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
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UNSPEC_DPSQ_SA_L_W))])]
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"ISA_HAS_DSP && !TARGET_64BIT"
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"dpsq_sa.l.w\t%q0,%1,%2"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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