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jeremybenn |
;; MIPS Paired-Single Floating and MIPS-3D Instructions.
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;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_insn "*movcc_v2sf_"
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[(set (match_operand:V2SF 0 "register_operand" "=f,f")
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(if_then_else:V2SF
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(match_operator:GPR 4 "equality_operator"
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[(match_operand:GPR 1 "register_operand" "d,d")
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(const_int 0)])
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(match_operand:V2SF 2 "register_operand" "f,0")
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(match_operand:V2SF 3 "register_operand" "0,f")))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"@
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mov%T4.ps\t%0,%2,%1
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mov%t4.ps\t%0,%3,%1"
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[(set_attr "type" "condmove")
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(set_attr "mode" "SF")])
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(define_insn "mips_cond_move_tf_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f,f")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0")
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(match_operand:V2SF 2 "register_operand" "0,f")
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(match_operand:CCV2 3 "register_operand" "z,z")]
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UNSPEC_MOVE_TF_PS))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"@
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movt.ps\t%0,%1,%3
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movf.ps\t%0,%2,%3"
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[(set_attr "type" "condmove")
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(set_attr "mode" "SF")])
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(define_expand "movv2sfcc"
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[(set (match_dup 4) (match_operand 1 "comparison_operator"))
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(set (match_operand:V2SF 0 "register_operand")
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(if_then_else:V2SF (match_dup 5)
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(match_operand:V2SF 2 "register_operand")
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(match_operand:V2SF 3 "register_operand")))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{
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/* We can only support MOVN.PS and MOVZ.PS.
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NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
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MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move
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each item independently. */
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if (GET_MODE_CLASS (GET_MODE (XEXP (operands[1], 0))) != MODE_INT)
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FAIL;
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mips_expand_conditional_move (operands);
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DONE;
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})
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; pul.ps - Pair Upper Lower
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(define_insn "mips_pul_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(vec_merge:V2SF
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(match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f")
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(const_int 2)))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"pul.ps\t%0,%1,%2"
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[(set_attr "type" "fmove")
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(set_attr "mode" "SF")])
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; puu.ps - Pair upper upper
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(define_insn "mips_puu_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(vec_merge:V2SF
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(match_operand:V2SF 1 "register_operand" "f")
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(vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
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(parallel [(const_int 1)
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(const_int 0)]))
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(const_int 2)))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"puu.ps\t%0,%1,%2"
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[(set_attr "type" "fmove")
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(set_attr "mode" "SF")])
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; pll.ps - Pair Lower Lower
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(define_insn "mips_pll_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(vec_merge:V2SF
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(vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
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(parallel [(const_int 1)
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(const_int 0)]))
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(match_operand:V2SF 2 "register_operand" "f")
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(const_int 2)))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"pll.ps\t%0,%1,%2"
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[(set_attr "type" "fmove")
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(set_attr "mode" "SF")])
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; plu.ps - Pair Lower Upper
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(define_insn "mips_plu_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(vec_merge:V2SF
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(vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
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(parallel [(const_int 1)
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(const_int 0)]))
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(vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
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(parallel [(const_int 1)
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(const_int 0)]))
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(const_int 2)))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"plu.ps\t%0,%1,%2"
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[(set_attr "type" "fmove")
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(set_attr "mode" "SF")])
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; vec_init
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(define_expand "vec_initv2sf"
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[(match_operand:V2SF 0 "register_operand")
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(match_operand:V2SF 1 "")]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{
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rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0));
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rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1));
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emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1));
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DONE;
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})
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(define_insn "vec_initv2sf_internal"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(vec_concat:V2SF
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(match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{
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if (BYTES_BIG_ENDIAN)
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return "cvt.ps.s\t%0,%1,%2";
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else
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return "cvt.ps.s\t%0,%2,%1";
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}
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[(set_attr "type" "fcvt")
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(set_attr "mode" "SF")])
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;; ??? This is only generated if we perform a vector operation that has to be
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;; emulated. There is no other way to get a vector mode bitfield extract
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;; currently.
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(define_insn "vec_extractv2sf"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
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(parallel
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[(match_operand 2 "const_0_or_1_operand" "")])))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{
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if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
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return "cvt.s.pu\t%0,%1";
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else
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return "cvt.s.pl\t%0,%1";
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}
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[(set_attr "type" "fcvt")
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(set_attr "mode" "SF")])
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;; ??? This is only generated if we disable the vec_init pattern. There is
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;; no other way to get a vector mode bitfield store currently.
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(define_expand "vec_setv2sf"
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[(match_operand:V2SF 0 "register_operand")
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(match_operand:SF 1 "register_operand")
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(match_operand 2 "const_0_or_1_operand")]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{
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rtx temp;
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/* We don't have an insert instruction, so we duplicate the float, and
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then use a PUL instruction. */
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temp = gen_reg_rtx (V2SFmode);
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emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1]));
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if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
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emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0]));
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else
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emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp));
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DONE;
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})
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; cvt.ps.s - Floating Point Convert Pair to Paired Single
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(define_expand "mips_cvt_ps_s"
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[(match_operand:V2SF 0 "register_operand")
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(match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "register_operand")]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1],
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operands[2]));
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else
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emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2],
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operands[1]));
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DONE;
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})
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; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point
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(define_expand "mips_cvt_s_pl"
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[(set (match_operand:SF 0 "register_operand")
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(vec_select:SF (match_operand:V2SF 1 "register_operand")
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(parallel [(match_dup 2)])))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{ operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })
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; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
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(define_expand "mips_cvt_s_pu"
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[(set (match_operand:SF 0 "register_operand")
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(vec_select:SF (match_operand:V2SF 1 "register_operand")
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(parallel [(match_dup 2)])))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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{ operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })
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; alnv.ps - Floating Point Align Variable
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(define_insn "mips_alnv_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f")
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(match_operand:SI 3 "register_operand" "d")]
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UNSPEC_ALNV_PS))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"alnv.ps\t%0,%1,%2,%3"
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[(set_attr "type" "fmove")
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(set_attr "mode" "SF")])
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; addr.ps - Floating Point Reduction Add
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(define_insn "mips_addr_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f")]
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UNSPEC_ADDR_PS))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"addr.ps\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "SF")])
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; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
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(define_insn "mips_cvt_pw_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
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UNSPEC_CVT_PW_PS))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"cvt.pw.ps\t%0,%1"
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[(set_attr "type" "fcvt")
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(set_attr "mode" "SF")])
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; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single
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(define_insn "mips_cvt_ps_pw"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
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UNSPEC_CVT_PS_PW))]
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"cvt.ps.pw\t%0,%1"
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[(set_attr "type" "fcvt")
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(set_attr "mode" "SF")])
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; mulr.ps - Floating Point Reduction Multiply
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| 268 |
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(define_insn "mips_mulr_ps"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f")]
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UNSPEC_MULR_PS))]
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| 273 |
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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"mulr.ps\t%0,%1,%2"
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[(set_attr "type" "fmul")
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(set_attr "mode" "SF")])
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; abs.ps
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| 279 |
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(define_expand "mips_abs_ps"
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[(set (match_operand:V2SF 0 "register_operand")
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(unspec:V2SF [(match_operand:V2SF 1 "register_operand")]
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| 282 |
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UNSPEC_ABS_PS))]
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| 283 |
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"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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| 284 |
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{
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| 285 |
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/* If we can ignore NaNs, this operation is equivalent to the
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| 286 |
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rtl ABS code. */
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| 287 |
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if (!HONOR_NANS (V2SFmode))
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| 288 |
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{
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|
|
emit_insn (gen_absv2sf2 (operands[0], operands[1]));
|
| 290 |
|
|
DONE;
|
| 291 |
|
|
}
|
| 292 |
|
|
})
|
| 293 |
|
|
|
| 294 |
|
|
(define_insn "*mips_abs_ps"
|
| 295 |
|
|
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
| 296 |
|
|
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
|
| 297 |
|
|
UNSPEC_ABS_PS))]
|
| 298 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 299 |
|
|
"abs.ps\t%0,%1"
|
| 300 |
|
|
[(set_attr "type" "fabs")
|
| 301 |
|
|
(set_attr "mode" "SF")])
|
| 302 |
|
|
|
| 303 |
|
|
;----------------------------------------------------------------------------
|
| 304 |
|
|
; Floating Point Comparisons for Scalars
|
| 305 |
|
|
;----------------------------------------------------------------------------
|
| 306 |
|
|
|
| 307 |
|
|
(define_insn "mips_cabs_cond_"
|
| 308 |
|
|
[(set (match_operand:CC 0 "register_operand" "=z")
|
| 309 |
|
|
(unspec:CC [(match_operand:SCALARF 1 "register_operand" "f")
|
| 310 |
|
|
(match_operand:SCALARF 2 "register_operand" "f")
|
| 311 |
|
|
(match_operand 3 "const_int_operand" "")]
|
| 312 |
|
|
UNSPEC_CABS))]
|
| 313 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 314 |
|
|
"cabs.%Y3.\t%0,%1,%2"
|
| 315 |
|
|
[(set_attr "type" "fcmp")
|
| 316 |
|
|
(set_attr "mode" "FPSW")])
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
;----------------------------------------------------------------------------
|
| 320 |
|
|
; Floating Point Comparisons for Four Singles
|
| 321 |
|
|
;----------------------------------------------------------------------------
|
| 322 |
|
|
|
| 323 |
|
|
(define_insn_and_split "mips_c_cond_4s"
|
| 324 |
|
|
[(set (match_operand:CCV4 0 "register_operand" "=z")
|
| 325 |
|
|
(unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
|
| 326 |
|
|
(match_operand:V2SF 2 "register_operand" "f")
|
| 327 |
|
|
(match_operand:V2SF 3 "register_operand" "f")
|
| 328 |
|
|
(match_operand:V2SF 4 "register_operand" "f")
|
| 329 |
|
|
(match_operand 5 "const_int_operand" "")]
|
| 330 |
|
|
UNSPEC_C))]
|
| 331 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 332 |
|
|
"#"
|
| 333 |
|
|
"&& reload_completed"
|
| 334 |
|
|
[(set (match_dup 6)
|
| 335 |
|
|
(unspec:CCV2 [(match_dup 1)
|
| 336 |
|
|
(match_dup 2)
|
| 337 |
|
|
(match_dup 5)]
|
| 338 |
|
|
UNSPEC_C))
|
| 339 |
|
|
(set (match_dup 7)
|
| 340 |
|
|
(unspec:CCV2 [(match_dup 3)
|
| 341 |
|
|
(match_dup 4)
|
| 342 |
|
|
(match_dup 5)]
|
| 343 |
|
|
UNSPEC_C))]
|
| 344 |
|
|
{
|
| 345 |
|
|
operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
|
| 346 |
|
|
operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
|
| 347 |
|
|
}
|
| 348 |
|
|
[(set_attr "type" "fcmp")
|
| 349 |
|
|
(set_attr "length" "8")
|
| 350 |
|
|
(set_attr "mode" "FPSW")])
|
| 351 |
|
|
|
| 352 |
|
|
(define_insn_and_split "mips_cabs_cond_4s"
|
| 353 |
|
|
[(set (match_operand:CCV4 0 "register_operand" "=z")
|
| 354 |
|
|
(unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
|
| 355 |
|
|
(match_operand:V2SF 2 "register_operand" "f")
|
| 356 |
|
|
(match_operand:V2SF 3 "register_operand" "f")
|
| 357 |
|
|
(match_operand:V2SF 4 "register_operand" "f")
|
| 358 |
|
|
(match_operand 5 "const_int_operand" "")]
|
| 359 |
|
|
UNSPEC_CABS))]
|
| 360 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 361 |
|
|
"#"
|
| 362 |
|
|
"&& reload_completed"
|
| 363 |
|
|
[(set (match_dup 6)
|
| 364 |
|
|
(unspec:CCV2 [(match_dup 1)
|
| 365 |
|
|
(match_dup 2)
|
| 366 |
|
|
(match_dup 5)]
|
| 367 |
|
|
UNSPEC_CABS))
|
| 368 |
|
|
(set (match_dup 7)
|
| 369 |
|
|
(unspec:CCV2 [(match_dup 3)
|
| 370 |
|
|
(match_dup 4)
|
| 371 |
|
|
(match_dup 5)]
|
| 372 |
|
|
UNSPEC_CABS))]
|
| 373 |
|
|
{
|
| 374 |
|
|
operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
|
| 375 |
|
|
operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
|
| 376 |
|
|
}
|
| 377 |
|
|
[(set_attr "type" "fcmp")
|
| 378 |
|
|
(set_attr "length" "8")
|
| 379 |
|
|
(set_attr "mode" "FPSW")])
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
;----------------------------------------------------------------------------
|
| 383 |
|
|
; Floating Point Comparisons for Paired Singles
|
| 384 |
|
|
;----------------------------------------------------------------------------
|
| 385 |
|
|
|
| 386 |
|
|
(define_insn "mips_c_cond_ps"
|
| 387 |
|
|
[(set (match_operand:CCV2 0 "register_operand" "=z")
|
| 388 |
|
|
(unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
|
| 389 |
|
|
(match_operand:V2SF 2 "register_operand" "f")
|
| 390 |
|
|
(match_operand 3 "const_int_operand" "")]
|
| 391 |
|
|
UNSPEC_C))]
|
| 392 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 393 |
|
|
"c.%Y3.ps\t%0,%1,%2"
|
| 394 |
|
|
[(set_attr "type" "fcmp")
|
| 395 |
|
|
(set_attr "mode" "FPSW")])
|
| 396 |
|
|
|
| 397 |
|
|
(define_insn "mips_cabs_cond_ps"
|
| 398 |
|
|
[(set (match_operand:CCV2 0 "register_operand" "=z")
|
| 399 |
|
|
(unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
|
| 400 |
|
|
(match_operand:V2SF 2 "register_operand" "f")
|
| 401 |
|
|
(match_operand 3 "const_int_operand" "")]
|
| 402 |
|
|
UNSPEC_CABS))]
|
| 403 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 404 |
|
|
"cabs.%Y3.ps\t%0,%1,%2"
|
| 405 |
|
|
[(set_attr "type" "fcmp")
|
| 406 |
|
|
(set_attr "mode" "FPSW")])
|
| 407 |
|
|
|
| 408 |
|
|
;; An expander for generating an scc operation.
|
| 409 |
|
|
(define_expand "scc_ps"
|
| 410 |
|
|
[(set (match_operand:CCV2 0)
|
| 411 |
|
|
(unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
|
| 412 |
|
|
|
| 413 |
|
|
(define_insn "s_ps"
|
| 414 |
|
|
[(set (match_operand:CCV2 0 "register_operand" "=z")
|
| 415 |
|
|
(unspec:CCV2
|
| 416 |
|
|
[(fcond (match_operand:V2SF 1 "register_operand" "f")
|
| 417 |
|
|
(match_operand:V2SF 2 "register_operand" "f"))]
|
| 418 |
|
|
UNSPEC_SCC))]
|
| 419 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 420 |
|
|
"c..ps\t%0,%1,%2"
|
| 421 |
|
|
[(set_attr "type" "fcmp")
|
| 422 |
|
|
(set_attr "mode" "FPSW")])
|
| 423 |
|
|
|
| 424 |
|
|
(define_insn "s_ps"
|
| 425 |
|
|
[(set (match_operand:CCV2 0 "register_operand" "=z")
|
| 426 |
|
|
(unspec:CCV2
|
| 427 |
|
|
[(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
|
| 428 |
|
|
(match_operand:V2SF 2 "register_operand" "f"))]
|
| 429 |
|
|
UNSPEC_SCC))]
|
| 430 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 431 |
|
|
"c..ps\t%0,%2,%1"
|
| 432 |
|
|
[(set_attr "type" "fcmp")
|
| 433 |
|
|
(set_attr "mode" "FPSW")])
|
| 434 |
|
|
|
| 435 |
|
|
;----------------------------------------------------------------------------
|
| 436 |
|
|
; Floating Point Branch Instructions.
|
| 437 |
|
|
;----------------------------------------------------------------------------
|
| 438 |
|
|
|
| 439 |
|
|
; Branch on Any of Four Floating Point Condition Codes True
|
| 440 |
|
|
(define_insn "bc1any4t"
|
| 441 |
|
|
[(set (pc)
|
| 442 |
|
|
(if_then_else (ne (match_operand:CCV4 1 "register_operand" "z")
|
| 443 |
|
|
(const_int 0))
|
| 444 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 445 |
|
|
(pc)))]
|
| 446 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 447 |
|
|
"%*bc1any4t\t%1,%0%/"
|
| 448 |
|
|
[(set_attr "type" "branch")])
|
| 449 |
|
|
|
| 450 |
|
|
; Branch on Any of Four Floating Point Condition Codes False
|
| 451 |
|
|
(define_insn "bc1any4f"
|
| 452 |
|
|
[(set (pc)
|
| 453 |
|
|
(if_then_else (ne (match_operand:CCV4 1 "register_operand" "z")
|
| 454 |
|
|
(const_int -1))
|
| 455 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 456 |
|
|
(pc)))]
|
| 457 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 458 |
|
|
"%*bc1any4f\t%1,%0%/"
|
| 459 |
|
|
[(set_attr "type" "branch")])
|
| 460 |
|
|
|
| 461 |
|
|
; Branch on Any of Two Floating Point Condition Codes True
|
| 462 |
|
|
(define_insn "bc1any2t"
|
| 463 |
|
|
[(set (pc)
|
| 464 |
|
|
(if_then_else (ne (match_operand:CCV2 1 "register_operand" "z")
|
| 465 |
|
|
(const_int 0))
|
| 466 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 467 |
|
|
(pc)))]
|
| 468 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 469 |
|
|
"%*bc1any2t\t%1,%0%/"
|
| 470 |
|
|
[(set_attr "type" "branch")])
|
| 471 |
|
|
|
| 472 |
|
|
; Branch on Any of Two Floating Point Condition Codes False
|
| 473 |
|
|
(define_insn "bc1any2f"
|
| 474 |
|
|
[(set (pc)
|
| 475 |
|
|
(if_then_else (ne (match_operand:CCV2 1 "register_operand" "z")
|
| 476 |
|
|
(const_int -1))
|
| 477 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 478 |
|
|
(pc)))]
|
| 479 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 480 |
|
|
"%*bc1any2f\t%1,%0%/"
|
| 481 |
|
|
[(set_attr "type" "branch")])
|
| 482 |
|
|
|
| 483 |
|
|
; Used to access one register in a CCV2 pair. Operand 0 is the register
|
| 484 |
|
|
; pair and operand 1 is the index of the register we want (a CONST_INT).
|
| 485 |
|
|
(define_expand "single_cc"
|
| 486 |
|
|
[(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
|
| 487 |
|
|
(const_int 0))])
|
| 488 |
|
|
|
| 489 |
|
|
; This is a normal floating-point branch pattern, but rather than check
|
| 490 |
|
|
; a single CCmode register, it checks one register in a CCV2 pair.
|
| 491 |
|
|
; Operand 2 is the register pair and operand 3 is the index of the
|
| 492 |
|
|
; register we want.
|
| 493 |
|
|
(define_insn "*branch_upper_lower"
|
| 494 |
|
|
[(set (pc)
|
| 495 |
|
|
(if_then_else
|
| 496 |
|
|
(match_operator 1 "equality_operator"
|
| 497 |
|
|
[(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
|
| 498 |
|
|
(match_operand 3 "const_int_operand")]
|
| 499 |
|
|
UNSPEC_SINGLE_CC)
|
| 500 |
|
|
(const_int 0)])
|
| 501 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 502 |
|
|
(pc)))]
|
| 503 |
|
|
"TARGET_HARD_FLOAT"
|
| 504 |
|
|
{
|
| 505 |
|
|
operands[2]
|
| 506 |
|
|
= gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
|
| 507 |
|
|
return mips_output_conditional_branch (insn, operands,
|
| 508 |
|
|
MIPS_BRANCH ("b%F1", "%2,%0"),
|
| 509 |
|
|
MIPS_BRANCH ("b%W1", "%2,%0"));
|
| 510 |
|
|
}
|
| 511 |
|
|
[(set_attr "type" "branch")])
|
| 512 |
|
|
|
| 513 |
|
|
; As above, but with the sense of the condition reversed.
|
| 514 |
|
|
(define_insn "*branch_upper_lower_inverted"
|
| 515 |
|
|
[(set (pc)
|
| 516 |
|
|
(if_then_else
|
| 517 |
|
|
(match_operator 1 "equality_operator"
|
| 518 |
|
|
[(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
|
| 519 |
|
|
(match_operand 3 "const_int_operand")]
|
| 520 |
|
|
UNSPEC_SINGLE_CC)
|
| 521 |
|
|
(const_int 0)])
|
| 522 |
|
|
(pc)
|
| 523 |
|
|
(label_ref (match_operand 0 "" ""))))]
|
| 524 |
|
|
"TARGET_HARD_FLOAT"
|
| 525 |
|
|
{
|
| 526 |
|
|
operands[2]
|
| 527 |
|
|
= gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
|
| 528 |
|
|
return mips_output_conditional_branch (insn, operands,
|
| 529 |
|
|
MIPS_BRANCH ("b%W1", "%2,%0"),
|
| 530 |
|
|
MIPS_BRANCH ("b%F1", "%2,%0"));
|
| 531 |
|
|
}
|
| 532 |
|
|
[(set_attr "type" "branch")])
|
| 533 |
|
|
|
| 534 |
|
|
;----------------------------------------------------------------------------
|
| 535 |
|
|
; Floating Point Reduced Precision Reciprocal Square Root Instructions.
|
| 536 |
|
|
;----------------------------------------------------------------------------
|
| 537 |
|
|
|
| 538 |
|
|
(define_insn "mips_rsqrt1_"
|
| 539 |
|
|
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
| 540 |
|
|
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
|
| 541 |
|
|
UNSPEC_RSQRT1))]
|
| 542 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 543 |
|
|
"rsqrt1.\t%0,%1"
|
| 544 |
|
|
[(set_attr "type" "frsqrt1")
|
| 545 |
|
|
(set_attr "mode" "")])
|
| 546 |
|
|
|
| 547 |
|
|
(define_insn "mips_rsqrt2_"
|
| 548 |
|
|
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
| 549 |
|
|
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
|
| 550 |
|
|
(match_operand:ANYF 2 "register_operand" "f")]
|
| 551 |
|
|
UNSPEC_RSQRT2))]
|
| 552 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 553 |
|
|
"rsqrt2.\t%0,%1,%2"
|
| 554 |
|
|
[(set_attr "type" "frsqrt2")
|
| 555 |
|
|
(set_attr "mode" "")])
|
| 556 |
|
|
|
| 557 |
|
|
(define_insn "mips_recip1_"
|
| 558 |
|
|
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
| 559 |
|
|
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
|
| 560 |
|
|
UNSPEC_RECIP1))]
|
| 561 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 562 |
|
|
"recip1.\t%0,%1"
|
| 563 |
|
|
[(set_attr "type" "frdiv1")
|
| 564 |
|
|
(set_attr "mode" "")])
|
| 565 |
|
|
|
| 566 |
|
|
(define_insn "mips_recip2_"
|
| 567 |
|
|
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
| 568 |
|
|
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
|
| 569 |
|
|
(match_operand:ANYF 2 "register_operand" "f")]
|
| 570 |
|
|
UNSPEC_RECIP2))]
|
| 571 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 572 |
|
|
"recip2.\t%0,%1,%2"
|
| 573 |
|
|
[(set_attr "type" "frdiv2")
|
| 574 |
|
|
(set_attr "mode" "")])
|
| 575 |
|
|
|
| 576 |
|
|
(define_expand "vcondv2sf"
|
| 577 |
|
|
[(set (match_operand:V2SF 0 "register_operand")
|
| 578 |
|
|
(if_then_else:V2SF
|
| 579 |
|
|
(match_operator 3 ""
|
| 580 |
|
|
[(match_operand:V2SF 4 "register_operand")
|
| 581 |
|
|
(match_operand:V2SF 5 "register_operand")])
|
| 582 |
|
|
(match_operand:V2SF 1 "register_operand")
|
| 583 |
|
|
(match_operand:V2SF 2 "register_operand")))]
|
| 584 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 585 |
|
|
{
|
| 586 |
|
|
mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
|
| 587 |
|
|
GET_CODE (operands[3]), operands[4], operands[5]);
|
| 588 |
|
|
DONE;
|
| 589 |
|
|
})
|
| 590 |
|
|
|
| 591 |
|
|
(define_expand "sminv2sf3"
|
| 592 |
|
|
[(set (match_operand:V2SF 0 "register_operand")
|
| 593 |
|
|
(smin:V2SF (match_operand:V2SF 1 "register_operand")
|
| 594 |
|
|
(match_operand:V2SF 2 "register_operand")))]
|
| 595 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 596 |
|
|
{
|
| 597 |
|
|
mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
|
| 598 |
|
|
LE, operands[1], operands[2]);
|
| 599 |
|
|
DONE;
|
| 600 |
|
|
})
|
| 601 |
|
|
|
| 602 |
|
|
(define_expand "smaxv2sf3"
|
| 603 |
|
|
[(set (match_operand:V2SF 0 "register_operand")
|
| 604 |
|
|
(smax:V2SF (match_operand:V2SF 1 "register_operand")
|
| 605 |
|
|
(match_operand:V2SF 2 "register_operand")))]
|
| 606 |
|
|
"TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
| 607 |
|
|
{
|
| 608 |
|
|
mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
|
| 609 |
|
|
LE, operands[2], operands[1]);
|
| 610 |
|
|
DONE;
|
| 611 |
|
|
})
|
