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/* Subroutines used for MIPS code generation.

   Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,

   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009

   Free Software Foundation, Inc.

   Contributed by A. Lichnewsky, lich@inria.inria.fr.

   Changes by Michael Meissner, meissner@osf.org.

   64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and

   Brendan Eich, brendan@microunity.com.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

any later version.

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include <signal.h>

#include "rtl.h"

#include "regs.h"

#include "hard-reg-set.h"

#include "real.h"

#include "insn-config.h"

#include "conditions.h"

#include "insn-attr.h"

#include "recog.h"

#include "toplev.h"

#include "output.h"

#include "tree.h"

#include "function.h"

#include "expr.h"

#include "optabs.h"

#include "libfuncs.h"

#include "flags.h"

#include "reload.h"

#include "tm_p.h"

#include "ggc.h"

#include "gstab.h"

#include "hashtab.h"

#include "debug.h"

#include "target.h"

#include "target-def.h"

#include "integrate.h"

#include "langhooks.h"

#include "cfglayout.h"

#include "sched-int.h"

#include "gimple.h"

#include "bitmap.h"

#include "diagnostic.h"

/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF.  */

#define UNSPEC_ADDRESS_P(X)                                     \

  (GET_CODE (X) == UNSPEC                                       \

   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                       \

   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)

/* Extract the symbol or label from UNSPEC wrapper X.  */

#define UNSPEC_ADDRESS(X) \

  XVECEXP (X, 0, 0)

/* Extract the symbol type from UNSPEC wrapper X.  */

#define UNSPEC_ADDRESS_TYPE(X) \

  ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))

/* The maximum distance between the top of the stack frame and the

   value $sp has when we save and restore registers.

   The value for normal-mode code must be a SMALL_OPERAND and must

   preserve the maximum stack alignment.  We therefore use a value

   of 0x7ff0 in this case.

   MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by

   up to 0x7f8 bytes and can usually save or restore all the registers

   that we need to save or restore.  (Note that we can only use these

   instructions for o32, for which the stack alignment is 8 bytes.)

   We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and

   RESTORE are not available.  We can then use unextended instructions

   to save and restore registers, and to allocate and deallocate the top

   part of the frame.  */

#define MIPS_MAX_FIRST_STACK_STEP                                       \

  (!TARGET_MIPS16 ? 0x7ff0                                              \

   : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8                              \

   : TARGET_64BIT ? 0x100 : 0x400)

/* True if INSN is a mips.md pattern or asm statement.  */

#define USEFUL_INSN_P(INSN)                                             \

  (NONDEBUG_INSN_P (INSN)                                               \

   && GET_CODE (PATTERN (INSN)) != USE                                  \

   && GET_CODE (PATTERN (INSN)) != CLOBBER                              \

   && GET_CODE (PATTERN (INSN)) != ADDR_VEC                             \

   && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)

/* If INSN is a delayed branch sequence, return the first instruction

   in the sequence, otherwise return INSN itself.  */

#define SEQ_BEGIN(INSN)                                                 \

  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \

   ? XVECEXP (PATTERN (INSN), 0, 0)                                       \

   : (INSN))

/* Likewise for the last instruction in a delayed branch sequence.  */

#define SEQ_END(INSN)                                                   \

  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \

   ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \

   : (INSN))

/* Execute the following loop body with SUBINSN set to each instruction

   between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive.  */

#define FOR_EACH_SUBINSN(SUBINSN, INSN)                                 \

  for ((SUBINSN) = SEQ_BEGIN (INSN);                                    \

       (SUBINSN) != NEXT_INSN (SEQ_END (INSN));                         \

       (SUBINSN) = NEXT_INSN (SUBINSN))

/* True if bit BIT is set in VALUE.  */

#define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)

/* Return the opcode for a ptr_mode load of the form:

       l[wd]    DEST, OFFSET(BASE).  */

#define MIPS_LOAD_PTR(DEST, OFFSET, BASE)       \

  (((ptr_mode == DImode ? 0x37 : 0x23) << 26)   \

   | ((BASE) << 21)                             \

   | ((DEST) << 16)                             \

   | (OFFSET))

/* Return the opcode to move register SRC into register DEST.  */

#define MIPS_MOVE(DEST, SRC)            \

  ((TARGET_64BIT ? 0x2d : 0x21)         \

   | ((DEST) << 11)                     \

   | ((SRC) << 21))

/* Return the opcode for:

       lui      DEST, VALUE.  */

#define MIPS_LUI(DEST, VALUE) \

  ((0xf << 26) | ((DEST) << 16) | (VALUE))

/* Return the opcode to jump to register DEST.  */

#define MIPS_JR(DEST) \

  (((DEST) << 21) | 0x8)

/* Return the opcode for:

       bal     . + (1 + OFFSET) * 4.  */

#define MIPS_BAL(OFFSET) \

  ((0x1 << 26) | (0x11 << 16) | (OFFSET))

/* Return the usual opcode for a nop.  */

#define MIPS_NOP 0

/* Classifies an address.

   ADDRESS_REG

       A natural register + offset address.  The register satisfies

       mips_valid_base_register_p and the offset is a const_arith_operand.

   ADDRESS_LO_SUM

       A LO_SUM rtx.  The first operand is a valid base register and

       the second operand is a symbolic address.

   ADDRESS_CONST_INT

       A signed 16-bit constant address.

   ADDRESS_SYMBOLIC:

       A constant symbolic address.  */

enum mips_address_type {

  ADDRESS_REG,

  ADDRESS_LO_SUM,

  ADDRESS_CONST_INT,

  ADDRESS_SYMBOLIC

};

/* Enumerates the setting of the -mr10k-cache-barrier option.  */

enum mips_r10k_cache_barrier_setting {

  R10K_CACHE_BARRIER_NONE,

  R10K_CACHE_BARRIER_STORE,

  R10K_CACHE_BARRIER_LOAD_STORE

};

/* Macros to create an enumeration identifier for a function prototype.  */

#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B

#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C

#define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D

#define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E

/* Classifies the prototype of a built-in function.  */

enum mips_function_type {

#define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,

#include "config/mips/mips-ftypes.def"

#undef DEF_MIPS_FTYPE

  MIPS_MAX_FTYPE_MAX

};

/* Specifies how a built-in function should be converted into rtl.  */

enum mips_builtin_type {

  /* The function corresponds directly to an .md pattern.  The return

     value is mapped to operand 0 and the arguments are mapped to

     operands 1 and above.  */

  MIPS_BUILTIN_DIRECT,

  /* The function corresponds directly to an .md pattern.  There is no return

     value and the arguments are mapped to operands 0 and above.  */

  MIPS_BUILTIN_DIRECT_NO_TARGET,

  /* The function corresponds to a comparison instruction followed by

     a mips_cond_move_tf_ps pattern.  The first two arguments are the

     values to compare and the second two arguments are the vector

     operands for the movt.ps or movf.ps instruction (in assembly order).  */

  MIPS_BUILTIN_MOVF,

  MIPS_BUILTIN_MOVT,

  /* The function corresponds to a V2SF comparison instruction.  Operand 0

     of this instruction is the result of the comparison, which has mode

     CCV2 or CCV4.  The function arguments are mapped to operands 1 and

     above.  The function's return value is an SImode boolean that is

     true under the following conditions:

     MIPS_BUILTIN_CMP_ANY: one of the registers is true

     MIPS_BUILTIN_CMP_ALL: all of the registers are true

     MIPS_BUILTIN_CMP_LOWER: the first register is true

     MIPS_BUILTIN_CMP_UPPER: the second register is true.  */

  MIPS_BUILTIN_CMP_ANY,

  MIPS_BUILTIN_CMP_ALL,

  MIPS_BUILTIN_CMP_UPPER,

  MIPS_BUILTIN_CMP_LOWER,

  /* As above, but the instruction only sets a single $fcc register.  */

  MIPS_BUILTIN_CMP_SINGLE,

  /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */

  MIPS_BUILTIN_BPOSGE32

};

/* Invoke MACRO (COND) for each C.cond.fmt condition.  */

#define MIPS_FP_CONDITIONS(MACRO) \

  MACRO (f),    \

  MACRO (un),   \

  MACRO (eq),   \

  MACRO (ueq),  \

  MACRO (olt),  \

  MACRO (ult),  \

  MACRO (ole),  \

  MACRO (ule),  \

  MACRO (sf),   \

  MACRO (ngle), \

  MACRO (seq),  \

  MACRO (ngl),  \

  MACRO (lt),   \

  MACRO (nge),  \

  MACRO (le),   \

  MACRO (ngt)

/* Enumerates the codes above as MIPS_FP_COND_<X>.  */

#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X

enum mips_fp_condition {

  MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)

};

/* Index X provides the string representation of MIPS_FP_COND_<X>.  */

#define STRINGIFY(X) #X

static const char *const mips_fp_conditions[] = {

  MIPS_FP_CONDITIONS (STRINGIFY)

};

/* Information about a function's frame layout.  */

struct GTY(())  mips_frame_info {

  /* The size of the frame in bytes.  */

  HOST_WIDE_INT total_size;

  /* The number of bytes allocated to variables.  */

  HOST_WIDE_INT var_size;

  /* The number of bytes allocated to outgoing function arguments.  */

  HOST_WIDE_INT args_size;

  /* The number of bytes allocated to the .cprestore slot, or 0 if there

     is no such slot.  */

  HOST_WIDE_INT cprestore_size;

  /* Bit X is set if the function saves or restores GPR X.  */

  unsigned int mask;

  /* Likewise FPR X.  */

  unsigned int fmask;

  /* Likewise doubleword accumulator X ($acX).  */

  unsigned int acc_mask;

  /* The number of GPRs, FPRs, doubleword accumulators and COP0

     registers saved.  */

  unsigned int num_gp;

  unsigned int num_fp;

  unsigned int num_acc;

  unsigned int num_cop0_regs;

  /* The offset of the topmost GPR, FPR, accumulator and COP0-register

     save slots from the top of the frame, or zero if no such slots are

     needed.  */

  HOST_WIDE_INT gp_save_offset;

  HOST_WIDE_INT fp_save_offset;

  HOST_WIDE_INT acc_save_offset;

  HOST_WIDE_INT cop0_save_offset;

  /* Likewise, but giving offsets from the bottom of the frame.  */

  HOST_WIDE_INT gp_sp_offset;

  HOST_WIDE_INT fp_sp_offset;

  HOST_WIDE_INT acc_sp_offset;

  HOST_WIDE_INT cop0_sp_offset;

  /* Similar, but the value passed to _mcount.  */

  HOST_WIDE_INT ra_fp_offset;

  /* The offset of arg_pointer_rtx from the bottom of the frame.  */

  HOST_WIDE_INT arg_pointer_offset;

  /* The offset of hard_frame_pointer_rtx from the bottom of the frame.  */

  HOST_WIDE_INT hard_frame_pointer_offset;

};

struct GTY(())  machine_function {

  /* The register returned by mips16_gp_pseudo_reg; see there for details.  */

  rtx mips16_gp_pseudo_rtx;

  /* The number of extra stack bytes taken up by register varargs.

     This area is allocated by the callee at the very top of the frame.  */

  int varargs_size;

  /* The current frame information, calculated by mips_compute_frame_info.  */

  struct mips_frame_info frame;

  /* The register to use as the function's global pointer, or INVALID_REGNUM

     if the function doesn't need one.  */

  unsigned int global_pointer;

  /* How many instructions it takes to load a label into $AT, or 0 if

     this property hasn't yet been calculated.  */

  unsigned int load_label_length;

  /* True if mips_adjust_insn_length should ignore an instruction's

     hazard attribute.  */

  bool ignore_hazard_length_p;

  /* True if the whole function is suitable for .set noreorder and

     .set nomacro.  */

  bool all_noreorder_p;

  /* True if the function has "inflexible" and "flexible" references

     to the global pointer.  See mips_cfun_has_inflexible_gp_ref_p

     and mips_cfun_has_flexible_gp_ref_p for details.  */

  bool has_inflexible_gp_insn_p;

  bool has_flexible_gp_insn_p;

  /* True if the function's prologue must load the global pointer

     value into pic_offset_table_rtx and store the same value in

     the function's cprestore slot (if any).  Even if this value

     is currently false, we may decide to set it to true later;

     see mips_must_initialize_gp_p () for details.  */

  bool must_initialize_gp_p;

  /* True if the current function must restore $gp after any potential

     clobber.  This value is only meaningful during the first post-epilogue

     split_insns pass; see mips_must_initialize_gp_p () for details.  */

  bool must_restore_gp_when_clobbered_p;

  /* True if we have emitted an instruction to initialize

     mips16_gp_pseudo_rtx.  */

  bool initialized_mips16_gp_pseudo_p;

  /* True if this is an interrupt handler.  */

  bool interrupt_handler_p;

  /* True if this is an interrupt handler that uses shadow registers.  */

  bool use_shadow_register_set_p;

  /* True if this is an interrupt handler that should keep interrupts

     masked.  */

  bool keep_interrupts_masked_p;

  /* True if this is an interrupt handler that should use DERET

     instead of ERET.  */

  bool use_debug_exception_return_p;

};

/* Information about a single argument.  */

struct mips_arg_info {

  /* True if the argument is passed in a floating-point register, or

     would have been if we hadn't run out of registers.  */

  bool fpr_p;

  /* The number of words passed in registers, rounded up.  */

  unsigned int reg_words;

  /* For EABI, the offset of the first register from GP_ARG_FIRST or

     FP_ARG_FIRST.  For other ABIs, the offset of the first register from

     the start of the ABI's argument structure (see the CUMULATIVE_ARGS

     comment for details).

     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely

     on the stack.  */

  unsigned int reg_offset;

  /* The number of words that must be passed on the stack, rounded up.  */

  unsigned int stack_words;

  /* The offset from the start of the stack overflow area of the argument's

     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */

  unsigned int stack_offset;

};

/* Information about an address described by mips_address_type.

   ADDRESS_CONST_INT

       No fields are used.

   ADDRESS_REG

       REG is the base register and OFFSET is the constant offset.

   ADDRESS_LO_SUM

       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE

       is the type of symbol it references.

   ADDRESS_SYMBOLIC

       SYMBOL_TYPE is the type of symbol that the address references.  */

struct mips_address_info {

  enum mips_address_type type;

  rtx reg;

  rtx offset;

  enum mips_symbol_type symbol_type;

};

/* One stage in a constant building sequence.  These sequences have

   the form:

        A = VALUE[0]

        A = A CODE[1] VALUE[1]

        A = A CODE[2] VALUE[2]

        ...

   where A is an accumulator, each CODE[i] is a binary rtl operation

   and each VALUE[i] is a constant integer.  CODE[0] is undefined.  */

struct mips_integer_op {

  enum rtx_code code;

  unsigned HOST_WIDE_INT value;

};

/* The largest number of operations needed to load an integer constant.

   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.

   When the lowest bit is clear, we can try, but reject a sequence with

   an extra SLL at the end.  */

#define MIPS_MAX_INTEGER_OPS 7

/* Information about a MIPS16e SAVE or RESTORE instruction.  */

struct mips16e_save_restore_info {

  /* The number of argument registers saved by a SAVE instruction.

  unsigned int nargs;

  /* Bit X is set if the instruction saves or restores GPR X.  */

  unsigned int mask;

  /* The total number of bytes to allocate.  */

  HOST_WIDE_INT size;

};

/* Global variables for machine-dependent things.  */

/* The -G setting, or the configuration's default small-data limit if

   no -G option is given.  */

static unsigned int mips_small_data_threshold;

/* The number of file directives written by mips_output_filename.  */

int num_source_filenames;

/* The name that appeared in the last .file directive written by

   mips_output_filename, or "" if mips_output_filename hasn't

   written anything yet.  */

const char *current_function_file = "";

/* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END.  */

int sdb_label_count;

/* Arrays that map GCC register numbers to debugger register numbers.  */

int mips_dbx_regno[FIRST_PSEUDO_REGISTER];

int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];

/* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs.  */

struct mips_asm_switch mips_noreorder = { "reorder", 0 };

struct mips_asm_switch mips_nomacro = { "macro", 0 };

struct mips_asm_switch mips_noat = { "at", 0 };

/* True if we're writing out a branch-likely instruction rather than a

   normal branch.  */

static bool mips_branch_likely;

/* The current instruction-set architecture.  */

enum processor_type mips_arch;

const struct mips_cpu_info *mips_arch_info;

/* The processor that we should tune the code for.  */

enum processor_type mips_tune;

const struct mips_cpu_info *mips_tune_info;

/* The ISA level associated with mips_arch.  */

int mips_isa;

/* The architecture selected by -mipsN, or null if -mipsN wasn't used.  */

static const struct mips_cpu_info *mips_isa_option_info;

/* Which ABI to use.  */

int mips_abi = MIPS_ABI_DEFAULT;

/* Which cost information to use.  */

const struct mips_rtx_cost_data *mips_cost;

/* The ambient target flags, excluding MASK_MIPS16.  */

static int mips_base_target_flags;

/* True if MIPS16 is the default mode.  */

bool mips_base_mips16;

/* The ambient values of other global variables.  */

static int mips_base_schedule_insns; /* flag_schedule_insns */

static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */

static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */

static int mips_base_align_loops; /* align_loops */

static int mips_base_align_jumps; /* align_jumps */

static int mips_base_align_functions; /* align_functions */

/* The -mcode-readable setting.  */

enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;

/* The -mr10k-cache-barrier setting.  */

static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;

/* Index [M][R] is true if register R is allowed to hold a value of mode M.  */

bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];

/* Index C is true if character C is a valid PRINT_OPERAND punctation

   character.  */

bool mips_print_operand_punct[256];

static GTY (()) int mips_output_filename_first_time = 1;

/* mips_split_p[X] is true if symbols of type X can be split by

   mips_split_symbol.  */

bool mips_split_p[NUM_SYMBOL_TYPES];

/* mips_split_hi_p[X] is true if the high parts of symbols of type X

   can be split by mips_split_symbol.  */

bool mips_split_hi_p[NUM_SYMBOL_TYPES];

/* mips_lo_relocs[X] is the relocation to use when a symbol of type X

   appears in a LO_SUM.  It can be null if such LO_SUMs aren't valid or

   if they are matched by a special .md file pattern.  */

static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];

/* Likewise for HIGHs.  */

static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];

/* Index R is the smallest register class that contains register R.  */

const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {

  LEA_REGS,     LEA_REGS,       M16_REGS,       V1_REG,

  M16_REGS,     M16_REGS,       M16_REGS,       M16_REGS,

  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,

  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,

  M16_REGS,     M16_REGS,       LEA_REGS,       LEA_REGS,

  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,

  T_REG,        PIC_FN_ADDR_REG, LEA_REGS,      LEA_REGS,

  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,

  MD0_REG,      MD1_REG,        NO_REGS,        ST_REGS,

  ST_REGS,      ST_REGS,        ST_REGS,        ST_REGS,

  ST_REGS,      ST_REGS,        ST_REGS,        NO_REGS,

  NO_REGS,      FRAME_REGS,     FRAME_REGS,     NO_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,

  DSP_ACC_REGS, DSP_ACC_REGS,   DSP_ACC_REGS,   DSP_ACC_REGS,

  DSP_ACC_REGS, DSP_ACC_REGS,   ALL_REGS,       ALL_REGS,

  ALL_REGS,     ALL_REGS,       ALL_REGS,       ALL_REGS

};

/* The value of TARGET_ATTRIBUTE_TABLE.  */

static const struct attribute_spec mips_attribute_table[] = {

  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */

  { "long_call",   0, 0, false, true,  true,  NULL },

  { "far",         0, 0, false, true,  true,  NULL },

  { "near",        0, 0, false, true,  true,  NULL },

  /* We would really like to treat "mips16" and "nomips16" as type

     attributes, but GCC doesn't provide the hooks we need to support

     the right conversion rules.  As declaration attributes, they affect

     code generation but don't carry other semantics.  */

  { "mips16",      0, 0, true,  false, false, NULL },

  { "nomips16",    0, 0, true,  false, false, NULL },

  /* Allow functions to be specified as interrupt handlers */

  { "interrupt",   0, 0, false, true,  true, NULL },

  { "use_shadow_register_set",  0, 0, false, true,  true, NULL },

  { "keep_interrupts_masked",   0, 0, false, true,  true, NULL },

  { "use_debug_exception_return", 0, 0, false, true,  true, NULL },

  { NULL,          0, 0, false, false, false, NULL }

};

/* A table describing all the processors GCC knows about.  Names are

   matched in the order listed.  The first mention of an ISA level is

   taken as the canonical name for that ISA.

   To ease comparison, please keep this table in the same order

   as GAS's mips_cpu_info_table.  Please also make sure that

   MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march

   options correctly.  */

static const struct mips_cpu_info mips_cpu_info_table[] = {

  /* Entries for generic ISAs.  */

  { "mips1", PROCESSOR_R3000, 1, 0 },

  { "mips2", PROCESSOR_R6000, 2, 0 },

  { "mips3", PROCESSOR_R4000, 3, 0 },

  { "mips4", PROCESSOR_R8000, 4, 0 },

  /* Prefer not to use branch-likely instructions for generic MIPS32rX

     and MIPS64rX code.  The instructions were officially deprecated

     in revisions 2 and earlier, but revision 3 is likely to downgrade

     that to a recommendation to avoid the instructions in code that

     isn't tuned to a specific processor.  */

  { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },

  { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },

  { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },

  /* ??? For now just tune the generic MIPS64r2 for 5KC as well.   */

  { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },

  /* MIPS I processors.  */

  { "r3000", PROCESSOR_R3000, 1, 0 },

  { "r2000", PROCESSOR_R3000, 1, 0 },

  { "r3900", PROCESSOR_R3900, 1, 0 },

  /* MIPS II processors.  */

  { "r6000", PROCESSOR_R6000, 2, 0 },

  /* MIPS III processors.  */

  { "r4000", PROCESSOR_R4000, 3, 0 },

  { "vr4100", PROCESSOR_R4100, 3, 0 },

  { "vr4111", PROCESSOR_R4111, 3, 0 },

  { "vr4120", PROCESSOR_R4120, 3, 0 },

  { "vr4130", PROCESSOR_R4130, 3, 0 },

  { "vr4300", PROCESSOR_R4300, 3, 0 },

  { "r4400", PROCESSOR_R4000, 3, 0 },

  { "r4600", PROCESSOR_R4600, 3, 0 },

  { "orion", PROCESSOR_R4600, 3, 0 },

  { "r4650", PROCESSOR_R4650, 3, 0 },

  /* ST Loongson 2E/2F processors.  */

  { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },

  { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },

  /* MIPS IV processors. */

  { "r8000", PROCESSOR_R8000, 4, 0 },

  { "r10000", PROCESSOR_R10000, 4, 0 },

  { "r12000", PROCESSOR_R10000, 4, 0 },

  { "r14000", PROCESSOR_R10000, 4, 0 },

  { "r16000", PROCESSOR_R10000, 4, 0 },

  { "vr5000", PROCESSOR_R5000, 4, 0 },

  { "vr5400", PROCESSOR_R5400, 4, 0 },

  { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },

  { "rm7000", PROCESSOR_R7000, 4, 0 },

  { "rm9000", PROCESSOR_R9000, 4, 0 },

  /* MIPS32 processors.  */

  { "4kc", PROCESSOR_4KC, 32, 0 },

  { "4km", PROCESSOR_4KC, 32, 0 },

  { "4kp", PROCESSOR_4KP, 32, 0 },

  { "4ksc", PROCESSOR_4KC, 32, 0 },

  /* MIPS32 Release 2 processors.  */

  { "m4k", PROCESSOR_M4K, 33, 0 },

  { "4kec", PROCESSOR_4KC, 33, 0 },

  { "4kem", PROCESSOR_4KC, 33, 0 },

  { "4kep", PROCESSOR_4KP, 33, 0 },

  { "4ksd", PROCESSOR_4KC, 33, 0 },

  { "24kc", PROCESSOR_24KC, 33, 0 },

  { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },