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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [mips/] [sb1.md] - Blame information for rev 282

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1 282 jeremybenn
;; Copyright (C) 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
2
;;
3
;; This file is part of GCC.
4
;;
5
;; GCC is free software; you can redistribute it and/or modify
6
;; it under the terms of the GNU General Public License as published by
7
;; the Free Software Foundation; either version 3, or (at your option)
8
;; any later version.
9
;;
10
;; GCC is distributed in the hope that it will be useful,
11
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
;; GNU General Public License for more details.
14
;;
15
;; You should have received a copy of the GNU General Public License
16
;; along with GCC; see the file COPYING3.  If not see
17
;; .
18
;;
19
;; DFA-based pipeline description for Broadcom SB-1
20
;;
21
 
22
;; The Broadcom SB-1 core is 4-way superscalar, in-order.  It has 2 load/store
23
;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP
24
;; pipes, and 1 MDMX pipes.  It can issue 2 ls insns and 2 exe/fpu/mdmx insns
25
;; each cycle.
26
 
27
;; We model the 4-way issue by ordering unit choices.  The possible choices are
28
;; {ex1,fp1}|{ex0,fp0}|ls1|ls0.  Instructions issue to the first eligible unit
29
;; in the list in most cases.  Non-indexed load/stores issue to ls0 first.
30
;; simple alu operations issue to ls1 if it is still available, and their
31
;; operands are ready (no co-issue with loads), otherwise to the first
32
;; available ex unit.
33
 
34
;; When exceptions are enabled, can only issue FP insns to fp1.  This is
35
;; to ensure that instructions complete in order.  The -mfp-exceptions option
36
;; can be used to specify whether the system has FP exceptions enabled or not.
37
 
38
;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
39
;; insn can issue per cycle (fp1).
40
 
41
;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register
42
;; file.  As a result, once an MDMX insn is issued, no FP insns can be issued
43
;; for 3 cycles.  When an FP insn is issued, no MDMX insn can be issued for
44
;; 5 cycles.  This is currently not handled because there is no MDMX insn
45
;; support as yet.
46
 
47
;;
48
;; We use two automata.  sb1_cpu_div is for the integer divides, which are
49
;; not pipelined.  sb1_cpu is for everything else.
50
;;
51
(define_automaton "sb1_cpu, sb1_cpu_div")
52
 
53
;; Load/store function units.
54
(define_cpu_unit "sb1_ls0" "sb1_cpu")
55
(define_cpu_unit "sb1_ls1" "sb1_cpu")
56
 
57
;; CPU function units.
58
(define_cpu_unit "sb1_ex0" "sb1_cpu")
59
(define_cpu_unit "sb1_ex1" "sb1_cpu")
60
 
61
;; The divide unit is not pipelined, and blocks hi/lo reads and writes.
62
(define_cpu_unit "sb1_div" "sb1_cpu_div")
63
;; DMULT block any multiply from issuing in the next cycle.
64
(define_cpu_unit "sb1_mul" "sb1_cpu")
65
 
66
;; Floating-point units.
67
(define_cpu_unit "sb1_fp0" "sb1_cpu")
68
(define_cpu_unit "sb1_fp1" "sb1_cpu")
69
 
70
;; Can only issue to one of the ex and fp pipes at a time.
71
(exclusion_set "sb1_ex0" "sb1_fp0")
72
(exclusion_set "sb1_ex1" "sb1_fp1")
73
 
74
;; Define an SB-1 specific attribute to simplify some FP descriptions.
75
;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are
76
;; disabled.
77
 
78
(define_attr "sb1_fp_pipes" "one,two"
79
  (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0))
80
              (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0)))
81
         (const_string "two")]
82
        (const_string "one")))
83
 
84
;; Define reservations for common combinations.
85
 
86
;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
87
;; effectively re-issuing the operation every 4 cycles.  This means that we
88
;; can have at most 4 long-cycle operations per pipe.
89
 
90
;; ??? The fdiv operations should be e.g.
91
;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7
92
;; but the DFA is too large when we do that.  Perhaps have to use scheduler
93
;; hooks here.
94
 
95
;; ??? Try limiting scheduler to 2 long latency operations, and see if this
96
;; results in a usable DFA, and whether it helps code performance.
97
 
98
;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3")
99
;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3")
100
 
101
;;
102
;; The ordering of the instruction-execution-path/resource-usage
103
;; descriptions (also known as reservation RTL) is roughly ordered
104
;; based on the define attribute RTL for the "type" classification.
105
;; When modifying, remember that the first test that matches is the
106
;; reservation used!
107
;;
108
 
109
(define_insn_reservation "ir_sb1_unknown" 1
110
  (and (eq_attr "cpu" "sb1,sb1a")
111
       (eq_attr "type" "unknown,multi"))
112
  "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1")
113
 
114
;; predicted taken branch causes 2 cycle ifetch bubble.  predicted not
115
;; taken branch causes 0 cycle ifetch bubble.  mispredicted branch causes 8
116
;; cycle ifetch bubble.  We assume all branches predicted not taken.
117
 
118
;; ??? This assumption that branches are predicated not taken should be
119
;; investigated.  Maybe using 2 here will give better results.
120
 
121
(define_insn_reservation "ir_sb1_branch" 0
122
  (and (eq_attr "cpu" "sb1,sb1a")
123
       (eq_attr "type" "branch,jump,call"))
124
  "sb1_ex0")
125
 
126
;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
127
;; register as destination.
128
 
129
;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on
130
;; an EX unit.  Can not co-issue if the dependent insn executes on an LS unit.
131
;; SB-1A can always co-issue here.
132
 
133
;; A load normally has a latency of zero cycles.  In some cases, dependent
134
;; insns can be issued in the same cycle.  However, a value of 1 gives
135
;; better performance in empirical testing.
136
 
137
(define_insn_reservation "ir_sb1_load" 1
138
  (and (eq_attr "cpu" "sb1")
139
       (eq_attr "type" "load,prefetch"))
140
  "sb1_ls0 | sb1_ls1")
141
 
142
(define_insn_reservation "ir_sb1a_load" 0
143
  (and (eq_attr "cpu" "sb1a")
144
       (eq_attr "type" "load,prefetch"))
145
  "sb1_ls0 | sb1_ls1")
146
 
147
;; Can not co-issue fpload with fp exe when in 32-bit mode.
148
 
149
(define_insn_reservation "ir_sb1_fpload" 0
150
  (and (eq_attr "cpu" "sb1,sb1a")
151
       (and (eq_attr "type" "fpload")
152
            (ne (symbol_ref "TARGET_FLOAT64")
153
                (const_int 0))))
154
  "sb1_ls0 | sb1_ls1")
155
 
156
(define_insn_reservation "ir_sb1_fpload_32bitfp" 1
157
  (and (eq_attr "cpu" "sb1,sb1a")
158
       (and (eq_attr "type" "fpload")
159
            (eq (symbol_ref "TARGET_FLOAT64")
160
                (const_int 0))))
161
  "sb1_ls0 | sb1_ls1")
162
 
163
;; Indexed loads can only execute on LS1 pipe.
164
 
165
(define_insn_reservation "ir_sb1_fpidxload" 0
166
  (and (eq_attr "cpu" "sb1,sb1a")
167
       (and (eq_attr "type" "fpidxload")
168
            (ne (symbol_ref "TARGET_FLOAT64")
169
                (const_int 0))))
170
  "sb1_ls1")
171
 
172
(define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
173
  (and (eq_attr "cpu" "sb1,sb1a")
174
       (and (eq_attr "type" "fpidxload")
175
            (eq (symbol_ref "TARGET_FLOAT64")
176
                (const_int 0))))
177
  "sb1_ls1")
178
 
179
;; prefx can only execute on the ls1 pipe.
180
 
181
(define_insn_reservation "ir_sb1_prefetchx" 0
182
  (and (eq_attr "cpu" "sb1,sb1a")
183
       (eq_attr "type" "prefetchx"))
184
  "sb1_ls1")
185
 
186
;; ??? There is a 4.5 cycle latency if a store is followed by a load, and
187
;; there is a RAW dependency.
188
 
189
(define_insn_reservation "ir_sb1_store" 1
190
  (and (eq_attr "cpu" "sb1,sb1a")
191
       (eq_attr "type" "store"))
192
  "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0")
193
 
194
(define_insn_reservation "ir_sb1_fpstore" 1
195
  (and (eq_attr "cpu" "sb1,sb1a")
196
       (eq_attr "type" "fpstore"))
197
  "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
198
 
199
;; Indexed stores can only execute on LS1 pipe.
200
 
201
(define_insn_reservation "ir_sb1_fpidxstore" 1
202
  (and (eq_attr "cpu" "sb1,sb1a")
203
       (eq_attr "type" "fpidxstore"))
204
  "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
205
 
206
;; Load latencies are 3 cycles for one load to another load or store (address
207
;; only).  This is 0 cycles for one load to a store using it as the data
208
;; written.
209
 
210
;; This assumes that if a load is dependent on a previous insn, then it must
211
;; be an address dependence.
212
 
213
(define_bypass 3
214
  "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
215
   ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
216
  "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
217
   ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
218
 
219
(define_bypass 3
220
  "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
221
   ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
222
  "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
223
  "mips_store_data_bypass_p")
224
 
225
;; On SB-1, simple alu instructions can execute on the LS1 unit.
226
 
227
;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
228
;; insn, to a store (for data), and to an xfer insn.  It has 1 cycle latency to
229
;; another LS insn (excluding store data).  A simple alu insn issued on an EX
230
;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
231
;; store data), otherwise a latency of 1 cycle.
232
 
233
;; ??? We cannot handle latencies properly for simple alu instructions
234
;; within the DFA pipeline model.  Latencies can be defined only from one
235
;; insn reservation to another.  We can't make them depend on which function
236
;; unit was used.  This isn't a DFA flaw.  There is a conflict here, as we
237
;; need to know the latency before we can determine which unit will be
238
;; available, but we need to know which unit it is issued to before we can
239
;; compute the latency.  Perhaps this can be handled via scheduler hooks.
240
;; This needs to be investigated.
241
 
242
;; ??? Optimal scheduling taking the LS units into account seems to require
243
;; a pre-scheduling pass.  We need to determine which instructions feed results
244
;; into store/load addresses, and thus benefit most from being issued to the
245
;; LS unit.  Also, we need to prune the list to ensure we don't overschedule
246
;; insns to the LS unit, and that we don't conflict with insns that need LS1
247
;; such as indexed loads.  We then need to emit nops to ensure that simple
248
;; alu instructions that are not supposed to be scheduled to LS1 don't
249
;; accidentally end up there because LS1 is free when they are issued.  This
250
;; will be a lot of work, and it isn't clear how useful it will be.
251
 
252
;; Empirical testing shows that 2 gives the best result.
253
 
254
(define_insn_reservation "ir_sb1_simple_alu" 2
255
  (and (eq_attr "cpu" "sb1")
256
       (eq_attr "type" "const,arith,logical,move,signext"))
257
  "sb1_ls1 | sb1_ex1 | sb1_ex0")
258
 
259
;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we
260
;; have none of the above problems.
261
 
262
(define_insn_reservation "ir_sb1a_simple_alu" 1
263
  (and (eq_attr "cpu" "sb1a")
264
       (eq_attr "type" "const,arith,logical,move,signext"))
265
  "sb1_ex1 | sb1_ex0")
266
 
267
;; ??? condmove also includes some FP instructions that execute on the FP
268
;; units.  This needs to be clarified.
269
 
270
(define_insn_reservation "ir_sb1_alu" 1
271
  (and (eq_attr "cpu" "sb1,sb1a")
272
       (eq_attr "type" "condmove,nop,shift"))
273
  "sb1_ex1 | sb1_ex0")
274
 
275
;; These are type arith/darith that only execute on the EX0 unit.
276
 
277
(define_insn_reservation "ir_sb1_alu_0" 1
278
  (and (eq_attr "cpu" "sb1,sb1a")
279
       (eq_attr "type" "slt,clz,trap"))
280
  "sb1_ex0")
281
 
282
;; An alu insn issued on an EX unit has a latency of 5 cycles when the
283
;; result goes to a LS unit (excluding store data).
284
 
285
;; This assumes that if a load is dependent on a previous insn, then it must
286
;; be an address dependence.
287
 
288
(define_bypass 5
289
  "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
290
  "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
291
   ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
292
 
293
(define_bypass 5
294
  "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
295
  "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
296
  "mips_store_data_bypass_p")
297
 
298
;; mf{hi,lo} is 1 cycle.
299
 
300
(define_insn_reservation "ir_sb1_mfhi" 1
301
  (and (eq_attr "cpu" "sb1,sb1a")
302
       (and (eq_attr "type" "mfhilo")
303
            (not (match_operand 1 "lo_operand"))))
304
  "sb1_ex1")
305
 
306
(define_insn_reservation "ir_sb1_mflo" 1
307
  (and (eq_attr "cpu" "sb1,sb1a")
308
       (and (eq_attr "type" "mfhilo")
309
            (match_operand 1 "lo_operand")))
310
  "sb1_ex1")
311
 
312
;; mt{hi,lo} to mul/div is 4 cycles.
313
 
314
(define_insn_reservation "ir_sb1_mthilo" 4
315
  (and (eq_attr "cpu" "sb1,sb1a")
316
       (eq_attr "type" "mthilo"))
317
  "sb1_ex1")
318
 
319
;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
320
 
321
(define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo")
322
 
323
;; multiply latency to an EX operation is 3 cycles.
324
 
325
;; ??? Should check whether we need to make multiply conflict with moves
326
;; to/from hilo registers.
327
 
328
(define_insn_reservation "ir_sb1_mulsi" 3
329
  (and (eq_attr "cpu" "sb1,sb1a")
330
       (and (eq_attr "type" "imul,imul3,imadd")
331
            (eq_attr "mode" "SI")))
332
  "sb1_ex1+sb1_mul")
333
 
334
;; muldi to mfhi is 4 cycles.
335
;; Blocks any other multiply insn issue for 1 cycle.
336
 
337
(define_insn_reservation "ir_sb1_muldi" 4
338
  (and (eq_attr "cpu" "sb1,sb1a")
339
       (and (eq_attr "type" "imul,imul3")
340
            (eq_attr "mode" "DI")))
341
  "sb1_ex1+sb1_mul, sb1_mul")
342
 
343
;; muldi to mflo is 3 cycles.
344
 
345
(define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo")
346
 
347
;;  mul latency is 7 cycles if the result is used by any LS insn.
348
 
349
;; This assumes that if a load is dependent on a previous insn, then it must
350
;; be an address dependence.
351
 
352
(define_bypass 7
353
  "ir_sb1_mulsi,ir_sb1_muldi"
354
  "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
355
   ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
356
 
357
(define_bypass 7
358
  "ir_sb1_mulsi,ir_sb1_muldi"
359
  "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
360
  "mips_store_data_bypass_p")
361
 
362
;; The divide unit is not pipelined.  Divide busy is asserted in the 4th
363
;; cycle, and then deasserted on the latency cycle.  So only one divide at
364
;; a time, but the first/last 4 cycles can overlap.
365
 
366
;; ??? All divides block writes to hi/lo regs.  hi/lo regs are written 4 cycles
367
;; after the latency cycle for divides (e.g. 40/72).  dmult writes lo in
368
;; cycle 7, and hi in cycle 8.  All other insns write hi/lo regs in cycle 7.
369
;; Default for output dependencies is the difference in latencies, which is
370
;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should
371
;; stall for 33 cycles.  This does not seem significant enough to worry about.
372
 
373
(define_insn_reservation "ir_sb1_divsi" 36
374
  (and (eq_attr "cpu" "sb1,sb1a")
375
       (and (eq_attr "type" "idiv")
376
            (eq_attr "mode" "SI")))
377
  "sb1_ex1, nothing*3, sb1_div*32")
378
 
379
(define_insn_reservation "ir_sb1_divdi" 68
380
  (and (eq_attr "cpu" "sb1,sb1a")
381
       (and (eq_attr "type" "idiv")
382
            (eq_attr "mode" "DI")))
383
  "sb1_ex1, nothing*3, sb1_div*64")
384
 
385
(define_insn_reservation "ir_sb1_fpu_2pipes" 4
386
  (and (eq_attr "cpu" "sb1,sb1a")
387
       (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
388
            (eq_attr "sb1_fp_pipes" "two")))
389
  "sb1_fp1 | sb1_fp0")
390
 
391
(define_insn_reservation "ir_sb1_fpu_1pipe" 4
392
  (and (eq_attr "cpu" "sb1,sb1a")
393
       (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
394
            (eq_attr "sb1_fp_pipes" "one")))
395
  "sb1_fp1")
396
 
397
(define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8
398
  (and (eq_attr "cpu" "sb1,sb1a")
399
       (and (eq_attr "type" "frdiv2,frsqrt2")
400
            (eq_attr "sb1_fp_pipes" "two")))
401
  "sb1_fp1 | sb1_fp0")
402
 
403
(define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8
404
  (and (eq_attr "cpu" "sb1,sb1a")
405
       (and (eq_attr "type" "frdiv2,frsqrt2")
406
            (eq_attr "sb1_fp_pipes" "one")))
407
  "sb1_fp1")
408
 
409
;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency
410
;; otherwise.
411
 
412
;; ??? Blocks issue of another non-madd/msub after 4 cycles.
413
 
414
(define_insn_reservation "ir_sb1_fmadd_2pipes" 8
415
  (and (eq_attr "cpu" "sb1,sb1a")
416
       (and (eq_attr "type" "fmadd")
417
            (eq_attr "sb1_fp_pipes" "two")))
418
  "sb1_fp1 | sb1_fp0")
419
 
420
(define_insn_reservation "ir_sb1_fmadd_1pipe" 8
421
  (and (eq_attr "cpu" "sb1,sb1a")
422
       (and (eq_attr "type" "fmadd")
423
            (eq_attr "sb1_fp_pipes" "one")))
424
  "sb1_fp1")
425
 
426
(define_insn_reservation "ir_sb1_fcmp" 4
427
  (and (eq_attr "cpu" "sb1,sb1a")
428
       (eq_attr "type" "fcmp"))
429
  "sb1_fp1")
430
 
431
;; mtc1 latency 5 cycles.
432
 
433
(define_insn_reservation "ir_sb1_mtxfer" 5
434
  (and (eq_attr "cpu" "sb1,sb1a")
435
       (eq_attr "type" "mtc"))
436
  "sb1_fp0")
437
 
438
;; mfc1 latency 1 cycle.
439
 
440
(define_insn_reservation "ir_sb1_mfxfer" 1
441
  (and (eq_attr "cpu" "sb1,sb1a")
442
       (eq_attr "type" "mfc"))
443
  "sb1_fp0")
444
 
445
;; ??? Can deliver at most 1 result per every 6 cycles because of issue
446
;; restrictions.
447
 
448
(define_insn_reservation "ir_sb1_divsf_2pipes" 24
449
  (and (eq_attr "cpu" "sb1,sb1a")
450
       (and (eq_attr "type" "fdiv")
451
            (and (eq_attr "mode" "SF")
452
                 (eq_attr "sb1_fp_pipes" "two"))))
453
  "sb1_fp1 | sb1_fp0")
454
 
455
(define_insn_reservation "ir_sb1_divsf_1pipe" 24
456
  (and (eq_attr "cpu" "sb1,sb1a")
457
       (and (eq_attr "type" "fdiv")
458
            (and (eq_attr "mode" "SF")
459
                 (eq_attr "sb1_fp_pipes" "one"))))
460
  "sb1_fp1")
461
 
462
;; ??? Can deliver at most 1 result per every 8 cycles because of issue
463
;; restrictions.
464
 
465
(define_insn_reservation "ir_sb1_divdf_2pipes" 32
466
  (and (eq_attr "cpu" "sb1,sb1a")
467
       (and (eq_attr "type" "fdiv")
468
            (and (eq_attr "mode" "DF")
469
                 (eq_attr "sb1_fp_pipes" "two"))))
470
  "sb1_fp1 | sb1_fp0")
471
 
472
(define_insn_reservation "ir_sb1_divdf_1pipe" 32
473
  (and (eq_attr "cpu" "sb1,sb1a")
474
       (and (eq_attr "type" "fdiv")
475
            (and (eq_attr "mode" "DF")
476
                 (eq_attr "sb1_fp_pipes" "one"))))
477
  "sb1_fp1")
478
 
479
;; ??? Can deliver at most 1 result per every 3 cycles because of issue
480
;; restrictions.
481
 
482
(define_insn_reservation "ir_sb1_recipsf_2pipes" 12
483
  (and (eq_attr "cpu" "sb1,sb1a")
484
       (and (eq_attr "type" "frdiv")
485
            (and (eq_attr "mode" "SF")
486
                 (eq_attr "sb1_fp_pipes" "two"))))
487
  "sb1_fp1 | sb1_fp0")
488
 
489
(define_insn_reservation "ir_sb1_recipsf_1pipe" 12
490
  (and (eq_attr "cpu" "sb1,sb1a")
491
       (and (eq_attr "type" "frdiv")
492
            (and (eq_attr "mode" "SF")
493
                 (eq_attr "sb1_fp_pipes" "one"))))
494
  "sb1_fp1")
495
 
496
;; ??? Can deliver at most 1 result per every 5 cycles because of issue
497
;; restrictions.
498
 
499
(define_insn_reservation "ir_sb1_recipdf_2pipes" 20
500
  (and (eq_attr "cpu" "sb1,sb1a")
501
       (and (eq_attr "type" "frdiv")
502
            (and (eq_attr "mode" "DF")
503
                 (eq_attr "sb1_fp_pipes" "two"))))
504
  "sb1_fp1 | sb1_fp0")
505
 
506
(define_insn_reservation "ir_sb1_recipdf_1pipe" 20
507
  (and (eq_attr "cpu" "sb1,sb1a")
508
       (and (eq_attr "type" "frdiv")
509
            (and (eq_attr "mode" "DF")
510
                 (eq_attr "sb1_fp_pipes" "one"))))
511
  "sb1_fp1")
512
 
513
;; ??? Can deliver at most 1 result per every 7 cycles because of issue
514
;; restrictions.
515
 
516
(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28
517
  (and (eq_attr "cpu" "sb1,sb1a")
518
       (and (eq_attr "type" "fsqrt")
519
            (and (eq_attr "mode" "SF")
520
                 (eq_attr "sb1_fp_pipes" "two"))))
521
  "sb1_fp1 | sb1_fp0")
522
 
523
(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28
524
  (and (eq_attr "cpu" "sb1,sb1a")
525
       (and (eq_attr "type" "fsqrt")
526
            (and (eq_attr "mode" "SF")
527
                 (eq_attr "sb1_fp_pipes" "one"))))
528
  "sb1_fp1")
529
 
530
;; ??? Can deliver at most 1 result per every 10 cycles because of issue
531
;; restrictions.
532
 
533
(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40
534
  (and (eq_attr "cpu" "sb1,sb1a")
535
       (and (eq_attr "type" "fsqrt")
536
            (and (eq_attr "mode" "DF")
537
                 (eq_attr "sb1_fp_pipes" "two"))))
538
  "sb1_fp1 | sb1_fp0")
539
 
540
(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40
541
  (and (eq_attr "cpu" "sb1,sb1a")
542
       (and (eq_attr "type" "fsqrt")
543
            (and (eq_attr "mode" "DF")
544
                 (eq_attr "sb1_fp_pipes" "one"))))
545
  "sb1_fp1")
546
 
547
;; ??? Can deliver at most 1 result per every 4 cycles because of issue
548
;; restrictions.
549
 
550
(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16
551
  (and (eq_attr "cpu" "sb1,sb1a")
552
       (and (eq_attr "type" "frsqrt")
553
            (and (eq_attr "mode" "SF")
554
                 (eq_attr "sb1_fp_pipes" "two"))))
555
  "sb1_fp1 | sb1_fp0")
556
 
557
(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16
558
  (and (eq_attr "cpu" "sb1,sb1a")
559
       (and (eq_attr "type" "frsqrt")
560
            (and (eq_attr "mode" "SF")
561
                 (eq_attr "sb1_fp_pipes" "one"))))
562
  "sb1_fp1")
563
 
564
;; ??? Can deliver at most 1 result per every 7 cycles because of issue
565
;; restrictions.
566
 
567
(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28
568
  (and (eq_attr "cpu" "sb1,sb1a")
569
       (and (eq_attr "type" "frsqrt")
570
            (and (eq_attr "mode" "DF")
571
                 (eq_attr "sb1_fp_pipes" "two"))))
572
  "sb1_fp1 | sb1_fp0")
573
 
574
(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28
575
  (and (eq_attr "cpu" "sb1,sb1a")
576
       (and (eq_attr "type" "frsqrt")
577
            (and (eq_attr "mode" "DF")
578
                 (eq_attr "sb1_fp_pipes" "one"))))
579
  "sb1_fp1")

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