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jeremybenn |
;; DFA-based pipeline description for the XLR.
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;;
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;; xlr.md Machine Description for the RMI XLR Microprocessor
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "xlr_main,xlr_muldiv")
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;; Definitions for xlr_main automaton.
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(define_cpu_unit "xlr_main_pipe" "xlr_main")
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(define_insn_reservation "ir_xlr_alu_slt" 2
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "slt"))
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"xlr_main_pipe")
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;; Integer arithmetic instructions.
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(define_insn_reservation "ir_xlr_alu" 1
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap"))
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"xlr_main_pipe")
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;; Integer arithmetic instructions.
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(define_insn_reservation "ir_xlr_condmove" 2
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "condmove"))
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"xlr_main_pipe")
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;; Load/store instructions.
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(define_insn_reservation "ir_xlr_load" 4
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "load"))
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"xlr_main_pipe")
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(define_insn_reservation "ir_xlr_store" 1
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "store"))
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"xlr_main_pipe")
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(define_insn_reservation "ir_xlr_prefetch_x" 1
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "prefetch,prefetchx"))
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"xlr_main_pipe")
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;; Branch instructions - use branch misprediction latency.
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(define_insn_reservation "ir_xlr_branch" 1
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "branch,jump,call"))
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"xlr_main_pipe")
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;; Coprocessor move instructions.
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(define_insn_reservation "ir_xlr_xfer" 2
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "mtc,mfc"))
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"xlr_main_pipe")
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(define_bypass 5 "ir_xlr_xfer" "ir_xlr_xfer")
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;; Definitions for the xlr_muldiv automaton.
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(define_cpu_unit "xlr_imuldiv_nopipe" "xlr_muldiv")
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(define_insn_reservation "ir_xlr_imul" 8
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "imul,imul3,imadd"))
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"xlr_main_pipe,xlr_imuldiv_nopipe*6")
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(define_insn_reservation "ir_xlr_div" 68
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "idiv"))
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"xlr_main_pipe,xlr_imuldiv_nopipe*67")
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(define_insn_reservation "xlr_hilo" 2
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(and (eq_attr "cpu" "xlr")
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(eq_attr "type" "mfhilo,mthilo"))
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"xlr_imuldiv_nopipe")
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