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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [mn10300/] [mn10300.c] - Blame information for rev 414

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Line No. Rev Author Line
1 282 jeremybenn
/* Subroutines for insn-output.c for Matsushita MN10300 series
2
   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3
   2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4
   Contributed by Jeff Law (law@cygnus.com).
5
 
6
This file is part of GCC.
7
 
8
GCC is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 3, or (at your option)
11
any later version.
12
 
13
GCC is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with GCC; see the file COPYING3.  If not see
20
<http://www.gnu.org/licenses/>.  */
21
 
22
#include "config.h"
23
#include "system.h"
24
#include "coretypes.h"
25
#include "tm.h"
26
#include "rtl.h"
27
#include "tree.h"
28
#include "regs.h"
29
#include "hard-reg-set.h"
30
#include "real.h"
31
#include "insn-config.h"
32
#include "conditions.h"
33
#include "output.h"
34
#include "insn-attr.h"
35
#include "flags.h"
36
#include "recog.h"
37
#include "reload.h"
38
#include "expr.h"
39
#include "optabs.h"
40
#include "function.h"
41
#include "obstack.h"
42
#include "toplev.h"
43
#include "tm_p.h"
44
#include "target.h"
45
#include "target-def.h"
46
 
47
/* This is used by GOTaddr2picreg to uniquely identify
48
   UNSPEC_INT_LABELs.  */
49
int mn10300_unspec_int_label_counter;
50
 
51
/* This is used in the am33_2.0-linux-gnu port, in which global symbol
52
   names are not prefixed by underscores, to tell whether to prefix a
53
   label with a plus sign or not, so that the assembler can tell
54
   symbol names from register names.  */
55
int mn10300_protect_label;
56
 
57
/* The selected processor.  */
58
enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
59
 
60
/* The size of the callee register save area.  Right now we save everything
61
   on entry since it costs us nothing in code size.  It does cost us from a
62
   speed standpoint, so we want to optimize this sooner or later.  */
63
#define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2)     \
64
                        + 4 * df_regs_ever_live_p (3)   \
65
                        + 4 * df_regs_ever_live_p (6)   \
66
                        + 4 * df_regs_ever_live_p (7)                   \
67
                        + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \
68
                                || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)))
69
 
70
 
71
static bool mn10300_handle_option (size_t, const char *, int);
72
static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool);
73
static int mn10300_address_cost_1 (rtx, int *);
74
static int mn10300_address_cost (rtx, bool);
75
static bool mn10300_rtx_costs (rtx, int, int, int *, bool);
76
static void mn10300_file_start (void);
77
static bool mn10300_return_in_memory (const_tree, const_tree);
78
static rtx mn10300_builtin_saveregs (void);
79
static void mn10300_va_start (tree, rtx);
80
static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode);
81
static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
82
                                       const_tree, bool);
83
static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
84
                                      tree, bool);
85
static unsigned int mn10300_case_values_threshold (void);
86
static void mn10300_encode_section_info (tree, rtx, int);
87
static void mn10300_asm_trampoline_template (FILE *);
88
static void mn10300_trampoline_init (rtx, tree, rtx);
89
static rtx mn10300_function_value (const_tree, const_tree, bool);
90
static rtx mn10300_libcall_value (enum machine_mode, const_rtx);
91
static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
92
static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
93
 
94
/* Initialize the GCC target structure.  */
95
#undef TARGET_ASM_ALIGNED_HI_OP
96
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
97
 
98
#undef TARGET_LEGITIMIZE_ADDRESS
99
#define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
100
 
101
#undef TARGET_RTX_COSTS
102
#define TARGET_RTX_COSTS mn10300_rtx_costs
103
#undef TARGET_ADDRESS_COST
104
#define TARGET_ADDRESS_COST mn10300_address_cost
105
 
106
#undef TARGET_ASM_FILE_START
107
#define TARGET_ASM_FILE_START mn10300_file_start
108
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
109
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
110
 
111
#undef TARGET_DEFAULT_TARGET_FLAGS
112
#define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
113
#undef TARGET_HANDLE_OPTION
114
#define TARGET_HANDLE_OPTION mn10300_handle_option
115
 
116
#undef  TARGET_ENCODE_SECTION_INFO
117
#define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
118
 
119
#undef TARGET_PROMOTE_PROTOTYPES
120
#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
121
#undef TARGET_RETURN_IN_MEMORY
122
#define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
123
#undef TARGET_PASS_BY_REFERENCE
124
#define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
125
#undef TARGET_CALLEE_COPIES
126
#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
127
#undef TARGET_ARG_PARTIAL_BYTES
128
#define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
129
 
130
#undef TARGET_EXPAND_BUILTIN_SAVEREGS
131
#define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
132
#undef TARGET_EXPAND_BUILTIN_VA_START
133
#define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
134
 
135
#undef TARGET_CASE_VALUES_THRESHOLD
136
#define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
137
 
138
#undef TARGET_LEGITIMATE_ADDRESS_P
139
#define TARGET_LEGITIMATE_ADDRESS_P     mn10300_legitimate_address_p
140
 
141
#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
142
#define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
143
#undef TARGET_TRAMPOLINE_INIT
144
#define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
145
 
146
#undef TARGET_FUNCTION_VALUE
147
#define TARGET_FUNCTION_VALUE mn10300_function_value
148
#undef TARGET_LIBCALL_VALUE
149
#define TARGET_LIBCALL_VALUE mn10300_libcall_value
150
 
151
#undef  TARGET_ASM_OUTPUT_MI_THUNK
152
#define TARGET_ASM_OUTPUT_MI_THUNK      mn10300_asm_output_mi_thunk
153
#undef  TARGET_ASM_CAN_OUTPUT_MI_THUNK
154
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK  mn10300_can_output_mi_thunk
155
 
156
struct gcc_target targetm = TARGET_INITIALIZER;
157
 
158
/* Implement TARGET_HANDLE_OPTION.  */
159
 
160
static bool
161
mn10300_handle_option (size_t code,
162
                       const char *arg ATTRIBUTE_UNUSED,
163
                       int value)
164
{
165
  switch (code)
166
    {
167
    case OPT_mam33:
168
      mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
169
      return true;
170
    case OPT_mam33_2:
171
      mn10300_processor = (value
172
                           ? PROCESSOR_AM33_2
173
                           : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
174
      return true;
175
    default:
176
      return true;
177
    }
178
}
179
 
180
/* Implement OVERRIDE_OPTIONS.  */
181
 
182
void
183
mn10300_override_options (void)
184
{
185
  if (TARGET_AM33)
186
    target_flags &= ~MASK_MULT_BUG;
187
}
188
 
189
static void
190
mn10300_file_start (void)
191
{
192
  default_file_start ();
193
 
194
  if (TARGET_AM33_2)
195
    fprintf (asm_out_file, "\t.am33_2\n");
196
  else if (TARGET_AM33)
197
    fprintf (asm_out_file, "\t.am33\n");
198
}
199
 
200
 
201
/* Print operand X using operand code CODE to assembly language output file
202
   FILE.  */
203
 
204
void
205
print_operand (FILE *file, rtx x, int code)
206
{
207
  switch (code)
208
    {
209
      case 'b':
210
      case 'B':
211
        if (cc_status.mdep.fpCC)
212
          {
213
            switch (code == 'b' ? GET_CODE (x)
214
                    : reverse_condition_maybe_unordered (GET_CODE (x)))
215
              {
216
              case NE:
217
                fprintf (file, "ne");
218
                break;
219
              case EQ:
220
                fprintf (file, "eq");
221
                break;
222
              case GE:
223
                fprintf (file, "ge");
224
                break;
225
              case GT:
226
                fprintf (file, "gt");
227
                break;
228
              case LE:
229
                fprintf (file, "le");
230
                break;
231
              case LT:
232
                fprintf (file, "lt");
233
                break;
234
              case ORDERED:
235
                fprintf (file, "lge");
236
                break;
237
              case UNORDERED:
238
                fprintf (file, "uo");
239
                break;
240
              case LTGT:
241
                fprintf (file, "lg");
242
                break;
243
              case UNEQ:
244
                fprintf (file, "ue");
245
                break;
246
              case UNGE:
247
                fprintf (file, "uge");
248
                break;
249
              case UNGT:
250
                fprintf (file, "ug");
251
                break;
252
              case UNLE:
253
                fprintf (file, "ule");
254
                break;
255
              case UNLT:
256
                fprintf (file, "ul");
257
                break;
258
              default:
259
                gcc_unreachable ();
260
              }
261
            break;
262
          }
263
        /* These are normal and reversed branches.  */
264
        switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
265
          {
266
          case NE:
267
            fprintf (file, "ne");
268
            break;
269
          case EQ:
270
            fprintf (file, "eq");
271
            break;
272
          case GE:
273
            fprintf (file, "ge");
274
            break;
275
          case GT:
276
            fprintf (file, "gt");
277
            break;
278
          case LE:
279
            fprintf (file, "le");
280
            break;
281
          case LT:
282
            fprintf (file, "lt");
283
            break;
284
          case GEU:
285
            fprintf (file, "cc");
286
            break;
287
          case GTU:
288
            fprintf (file, "hi");
289
            break;
290
          case LEU:
291
            fprintf (file, "ls");
292
            break;
293
          case LTU:
294
            fprintf (file, "cs");
295
            break;
296
          default:
297
            gcc_unreachable ();
298
          }
299
        break;
300
      case 'C':
301
        /* This is used for the operand to a call instruction;
302
           if it's a REG, enclose it in parens, else output
303
           the operand normally.  */
304
        if (GET_CODE (x) == REG)
305
          {
306
            fputc ('(', file);
307
            print_operand (file, x, 0);
308
            fputc (')', file);
309
          }
310
        else
311
          print_operand (file, x, 0);
312
        break;
313
 
314
      case 'D':
315
        switch (GET_CODE (x))
316
          {
317
          case MEM:
318
            fputc ('(', file);
319
            output_address (XEXP (x, 0));
320
            fputc (')', file);
321
            break;
322
 
323
          case REG:
324
            fprintf (file, "fd%d", REGNO (x) - 18);
325
            break;
326
 
327
          default:
328
            gcc_unreachable ();
329
          }
330
        break;
331
 
332
      /* These are the least significant word in a 64bit value.  */
333
      case 'L':
334
        switch (GET_CODE (x))
335
          {
336
          case MEM:
337
            fputc ('(', file);
338
            output_address (XEXP (x, 0));
339
            fputc (')', file);
340
            break;
341
 
342
          case REG:
343
            fprintf (file, "%s", reg_names[REGNO (x)]);
344
            break;
345
 
346
          case SUBREG:
347
            fprintf (file, "%s", reg_names[subreg_regno (x)]);
348
            break;
349
 
350
          case CONST_DOUBLE:
351
              {
352
                long val[2];
353
                REAL_VALUE_TYPE rv;
354
 
355
                switch (GET_MODE (x))
356
                  {
357
                    case DFmode:
358
                      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
359
                      REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
360
                      fprintf (file, "0x%lx", val[0]);
361
                      break;;
362
                    case SFmode:
363
                      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
364
                      REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
365
                      fprintf (file, "0x%lx", val[0]);
366
                      break;;
367
                    case VOIDmode:
368
                    case DImode:
369
                      print_operand_address (file,
370
                                             GEN_INT (CONST_DOUBLE_LOW (x)));
371
                      break;
372
                    default:
373
                      break;
374
                  }
375
                break;
376
              }
377
 
378
          case CONST_INT:
379
            {
380
              rtx low, high;
381
              split_double (x, &low, &high);
382
              fprintf (file, "%ld", (long)INTVAL (low));
383
              break;
384
            }
385
 
386
          default:
387
            gcc_unreachable ();
388
          }
389
        break;
390
 
391
      /* Similarly, but for the most significant word.  */
392
      case 'H':
393
        switch (GET_CODE (x))
394
          {
395
          case MEM:
396
            fputc ('(', file);
397
            x = adjust_address (x, SImode, 4);
398
            output_address (XEXP (x, 0));
399
            fputc (')', file);
400
            break;
401
 
402
          case REG:
403
            fprintf (file, "%s", reg_names[REGNO (x) + 1]);
404
            break;
405
 
406
          case SUBREG:
407
            fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
408
            break;
409
 
410
          case CONST_DOUBLE:
411
              {
412
                long val[2];
413
                REAL_VALUE_TYPE rv;
414
 
415
                switch (GET_MODE (x))
416
                  {
417
                    case DFmode:
418
                      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
419
                      REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
420
                      fprintf (file, "0x%lx", val[1]);
421
                      break;;
422
                    case SFmode:
423
                      gcc_unreachable ();
424
                    case VOIDmode:
425
                    case DImode:
426
                      print_operand_address (file,
427
                                             GEN_INT (CONST_DOUBLE_HIGH (x)));
428
                      break;
429
                    default:
430
                      break;
431
                  }
432
                break;
433
              }
434
 
435
          case CONST_INT:
436
            {
437
              rtx low, high;
438
              split_double (x, &low, &high);
439
              fprintf (file, "%ld", (long)INTVAL (high));
440
              break;
441
            }
442
 
443
          default:
444
            gcc_unreachable ();
445
          }
446
        break;
447
 
448
      case 'A':
449
        fputc ('(', file);
450
        if (GET_CODE (XEXP (x, 0)) == REG)
451
          output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
452
        else
453
          output_address (XEXP (x, 0));
454
        fputc (')', file);
455
        break;
456
 
457
      case 'N':
458
        gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
459
        fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
460
        break;
461
 
462
      case 'U':
463
        gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
464
        fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
465
        break;
466
 
467
      /* For shift counts.  The hardware ignores the upper bits of
468
         any immediate, but the assembler will flag an out of range
469
         shift count as an error.  So we mask off the high bits
470
         of the immediate here.  */
471
      case 'S':
472
        if (GET_CODE (x) == CONST_INT)
473
          {
474
            fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
475
            break;
476
          }
477
        /* FALL THROUGH */
478
 
479
      default:
480
        switch (GET_CODE (x))
481
          {
482
          case MEM:
483
            fputc ('(', file);
484
            output_address (XEXP (x, 0));
485
            fputc (')', file);
486
            break;
487
 
488
          case PLUS:
489
            output_address (x);
490
            break;
491
 
492
          case REG:
493
            fprintf (file, "%s", reg_names[REGNO (x)]);
494
            break;
495
 
496
          case SUBREG:
497
            fprintf (file, "%s", reg_names[subreg_regno (x)]);
498
            break;
499
 
500
          /* This will only be single precision....  */
501
          case CONST_DOUBLE:
502
            {
503
              unsigned long val;
504
              REAL_VALUE_TYPE rv;
505
 
506
              REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
507
              REAL_VALUE_TO_TARGET_SINGLE (rv, val);
508
              fprintf (file, "0x%lx", val);
509
              break;
510
            }
511
 
512
          case CONST_INT:
513
          case SYMBOL_REF:
514
          case CONST:
515
          case LABEL_REF:
516
          case CODE_LABEL:
517
          case UNSPEC:
518
            print_operand_address (file, x);
519
            break;
520
          default:
521
            gcc_unreachable ();
522
          }
523
        break;
524
   }
525
}
526
 
527
/* Output assembly language output for the address ADDR to FILE.  */
528
 
529
void
530
print_operand_address (FILE *file, rtx addr)
531
{
532
  switch (GET_CODE (addr))
533
    {
534
    case POST_INC:
535
      print_operand_address (file, XEXP (addr, 0));
536
      fputc ('+', file);
537
      break;
538
    case REG:
539
      print_operand (file, addr, 0);
540
      break;
541
    case PLUS:
542
      {
543
        rtx base, index;
544
        if (REG_P (XEXP (addr, 0))
545
            && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
546
          base = XEXP (addr, 0), index = XEXP (addr, 1);
547
        else if (REG_P (XEXP (addr, 1))
548
            && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
549
          base = XEXP (addr, 1), index = XEXP (addr, 0);
550
        else
551
          gcc_unreachable ();
552
        print_operand (file, index, 0);
553
        fputc (',', file);
554
        print_operand (file, base, 0);;
555
        break;
556
      }
557
    case SYMBOL_REF:
558
      output_addr_const (file, addr);
559
      break;
560
    default:
561
      output_addr_const (file, addr);
562
      break;
563
    }
564
}
565
 
566
/* Count the number of FP registers that have to be saved.  */
567
static int
568
fp_regs_to_save (void)
569
{
570
  int i, n = 0;
571
 
572
  if (! TARGET_AM33_2)
573
    return 0;
574
 
575
  for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
576
    if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
577
      ++n;
578
 
579
  return n;
580
}
581
 
582
/* Print a set of registers in the format required by "movm" and "ret".
583
   Register K is saved if bit K of MASK is set.  The data and address
584
   registers can be stored individually, but the extended registers cannot.
585
   We assume that the mask already takes that into account.  For instance,
586
   bits 14 to 17 must have the same value.  */
587
 
588
void
589
mn10300_print_reg_list (FILE *file, int mask)
590
{
591
  int need_comma;
592
  int i;
593
 
594
  need_comma = 0;
595
  fputc ('[', file);
596
 
597
  for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
598
    if ((mask & (1 << i)) != 0)
599
      {
600
        if (need_comma)
601
          fputc (',', file);
602
        fputs (reg_names [i], file);
603
        need_comma = 1;
604
      }
605
 
606
  if ((mask & 0x3c000) != 0)
607
    {
608
      gcc_assert ((mask & 0x3c000) == 0x3c000);
609
      if (need_comma)
610
        fputc (',', file);
611
      fputs ("exreg1", file);
612
      need_comma = 1;
613
    }
614
 
615
  fputc (']', file);
616
}
617
 
618
int
619
can_use_return_insn (void)
620
{
621
  /* size includes the fixed stack space needed for function calls.  */
622
  int size = get_frame_size () + crtl->outgoing_args_size;
623
 
624
  /* And space for the return pointer.  */
625
  size += crtl->outgoing_args_size ? 4 : 0;
626
 
627
  return (reload_completed
628
          && size == 0
629
          && !df_regs_ever_live_p (2)
630
          && !df_regs_ever_live_p (3)
631
          && !df_regs_ever_live_p (6)
632
          && !df_regs_ever_live_p (7)
633
          && !df_regs_ever_live_p (14)
634
          && !df_regs_ever_live_p (15)
635
          && !df_regs_ever_live_p (16)
636
          && !df_regs_ever_live_p (17)
637
          && fp_regs_to_save () == 0
638
          && !frame_pointer_needed);
639
}
640
 
641
/* Returns the set of live, callee-saved registers as a bitmask.  The
642
   callee-saved extended registers cannot be stored individually, so
643
   all of them will be included in the mask if any one of them is used.  */
644
 
645
int
646
mn10300_get_live_callee_saved_regs (void)
647
{
648
  int mask;
649
  int i;
650
 
651
  mask = 0;
652
  for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
653
    if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
654
      mask |= (1 << i);
655
  if ((mask & 0x3c000) != 0)
656
    mask |= 0x3c000;
657
 
658
  return mask;
659
}
660
 
661
/* Generate an instruction that pushes several registers onto the stack.
662
   Register K will be saved if bit K in MASK is set.  The function does
663
   nothing if MASK is zero.
664
 
665
   To be compatible with the "movm" instruction, the lowest-numbered
666
   register must be stored in the lowest slot.  If MASK is the set
667
   { R1,...,RN }, where R1...RN are ordered least first, the generated
668
   instruction will have the form:
669
 
670
       (parallel
671
         (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
672
         (set (mem:SI (plus:SI (reg:SI 9)
673
                               (const_int -1*4)))
674
              (reg:SI RN))
675
         ...
676
         (set (mem:SI (plus:SI (reg:SI 9)
677
                               (const_int -N*4)))
678
              (reg:SI R1))) */
679
 
680
void
681
mn10300_gen_multiple_store (int mask)
682
{
683
  if (mask != 0)
684
    {
685
      int i;
686
      int count;
687
      rtx par;
688
      int pari;
689
 
690
      /* Count how many registers need to be saved.  */
691
      count = 0;
692
      for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
693
        if ((mask & (1 << i)) != 0)
694
          count += 1;
695
 
696
      /* We need one PARALLEL element to update the stack pointer and
697
         an additional element for each register that is stored.  */
698
      par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
699
 
700
      /* Create the instruction that updates the stack pointer.  */
701
      XVECEXP (par, 0, 0)
702
        = gen_rtx_SET (SImode,
703
                       stack_pointer_rtx,
704
                       gen_rtx_PLUS (SImode,
705
                                     stack_pointer_rtx,
706
                                     GEN_INT (-count * 4)));
707
 
708
      /* Create each store.  */
709
      pari = 1;
710
      for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
711
        if ((mask & (1 << i)) != 0)
712
          {
713
            rtx address = gen_rtx_PLUS (SImode,
714
                                        stack_pointer_rtx,
715
                                        GEN_INT (-pari * 4));
716
            XVECEXP(par, 0, pari)
717
              = gen_rtx_SET (VOIDmode,
718
                             gen_rtx_MEM (SImode, address),
719
                             gen_rtx_REG (SImode, i));
720
            pari += 1;
721
          }
722
 
723
      par = emit_insn (par);
724
      RTX_FRAME_RELATED_P (par) = 1;
725
    }
726
}
727
 
728
void
729
expand_prologue (void)
730
{
731
  HOST_WIDE_INT size;
732
 
733
  /* SIZE includes the fixed stack space needed for function calls.  */
734
  size = get_frame_size () + crtl->outgoing_args_size;
735
  size += (crtl->outgoing_args_size ? 4 : 0);
736
 
737
  /* If we use any of the callee-saved registers, save them now.  */
738
  mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
739
 
740
  if (TARGET_AM33_2 && fp_regs_to_save ())
741
    {
742
      int num_regs_to_save = fp_regs_to_save (), i;
743
      HOST_WIDE_INT xsize;
744
      enum { save_sp_merge,
745
             save_sp_no_merge,
746
             save_sp_partial_merge,
747
             save_a0_merge,
748
             save_a0_no_merge } strategy;
749
      unsigned int strategy_size = (unsigned)-1, this_strategy_size;
750
      rtx reg;
751
      rtx insn;
752
 
753
      /* We have several different strategies to save FP registers.
754
         We can store them using SP offsets, which is beneficial if
755
         there are just a few registers to save, or we can use `a0' in
756
         post-increment mode (`a0' is the only call-clobbered address
757
         register that is never used to pass information to a
758
         function).  Furthermore, if we don't need a frame pointer, we
759
         can merge the two SP adds into a single one, but this isn't
760
         always beneficial; sometimes we can just split the two adds
761
         so that we don't exceed a 16-bit constant size.  The code
762
         below will select which strategy to use, so as to generate
763
         smallest code.  Ties are broken in favor or shorter sequences
764
         (in terms of number of instructions).  */
765
 
766
#define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
767
                        : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
768
#define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
769
                        : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
770
#define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
771
  (((S) >= (L)) ? (SIZE1) * (N) \
772
   : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
773
                               + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
774
   : (ELSE))
775
#define SIZE_FMOV_SP_(S,N) \
776
  (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
777
                   SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
778
                                    (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
779
#define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
780
 
781
      /* Consider alternative save_sp_merge only if we don't need the
782
         frame pointer and size is nonzero.  */
783
      if (! frame_pointer_needed && size)
784
        {
785
          /* Insn: add -(size + 4 * num_regs_to_save), sp.  */
786
          this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
787
          /* Insn: fmov fs#, (##, sp), for each fs# to be saved.  */
788
          this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
789
 
790
          if (this_strategy_size < strategy_size)
791
            {
792
              strategy = save_sp_merge;
793
              strategy_size = this_strategy_size;
794
            }
795
        }
796
 
797
      /* Consider alternative save_sp_no_merge unconditionally.  */
798
      /* Insn: add -4 * num_regs_to_save, sp.  */
799
      this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
800
      /* Insn: fmov fs#, (##, sp), for each fs# to be saved.  */
801
      this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
802
      if (size)
803
        {
804
          /* Insn: add -size, sp.  */
805
          this_strategy_size += SIZE_ADD_SP (-size);
806
        }
807
 
808
      if (this_strategy_size < strategy_size)
809
        {
810
          strategy = save_sp_no_merge;
811
          strategy_size = this_strategy_size;
812
        }
813
 
814
      /* Consider alternative save_sp_partial_merge only if we don't
815
         need a frame pointer and size is reasonably large.  */
816
      if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
817
        {
818
          /* Insn: add -128, sp.  */
819
          this_strategy_size = SIZE_ADD_SP (-128);
820
          /* Insn: fmov fs#, (##, sp), for each fs# to be saved.  */
821
          this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
822
                                              num_regs_to_save);
823
          if (size)
824
            {
825
              /* Insn: add 128-size, sp.  */
826
              this_strategy_size += SIZE_ADD_SP (128 - size);
827
            }
828
 
829
          if (this_strategy_size < strategy_size)
830
            {
831
              strategy = save_sp_partial_merge;
832
              strategy_size = this_strategy_size;
833
            }
834
        }
835
 
836
      /* Consider alternative save_a0_merge only if we don't need a
837
         frame pointer, size is nonzero and the user hasn't
838
         changed the calling conventions of a0.  */
839
      if (! frame_pointer_needed && size
840
          && call_really_used_regs [FIRST_ADDRESS_REGNUM]
841
          && ! fixed_regs[FIRST_ADDRESS_REGNUM])
842
        {
843
          /* Insn: add -(size + 4 * num_regs_to_save), sp.  */
844
          this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
845
          /* Insn: mov sp, a0.  */
846
          this_strategy_size++;
847
          if (size)
848
            {
849
              /* Insn: add size, a0.  */
850
              this_strategy_size += SIZE_ADD_AX (size);
851
            }
852
          /* Insn: fmov fs#, (a0+), for each fs# to be saved.  */
853
          this_strategy_size += 3 * num_regs_to_save;
854
 
855
          if (this_strategy_size < strategy_size)
856
            {
857
              strategy = save_a0_merge;
858
              strategy_size = this_strategy_size;
859
            }
860
        }
861
 
862
      /* Consider alternative save_a0_no_merge if the user hasn't
863
         changed the calling conventions of a0.  */
864
      if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
865
          && ! fixed_regs[FIRST_ADDRESS_REGNUM])
866
        {
867
          /* Insn: add -4 * num_regs_to_save, sp.  */
868
          this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
869
          /* Insn: mov sp, a0.  */
870
          this_strategy_size++;
871
          /* Insn: fmov fs#, (a0+), for each fs# to be saved.  */
872
          this_strategy_size += 3 * num_regs_to_save;
873
          if (size)
874
            {
875
              /* Insn: add -size, sp.  */
876
              this_strategy_size += SIZE_ADD_SP (-size);
877
            }
878
 
879
          if (this_strategy_size < strategy_size)
880
            {
881
              strategy = save_a0_no_merge;
882
              strategy_size = this_strategy_size;
883
            }
884
        }
885
 
886
      /* Emit the initial SP add, common to all strategies.  */
887
      switch (strategy)
888
        {
889
        case save_sp_no_merge:
890
        case save_a0_no_merge:
891
          emit_insn (gen_addsi3 (stack_pointer_rtx,
892
                                 stack_pointer_rtx,
893
                                 GEN_INT (-4 * num_regs_to_save)));
894
          xsize = 0;
895
          break;
896
 
897
        case save_sp_partial_merge:
898
          emit_insn (gen_addsi3 (stack_pointer_rtx,
899
                                 stack_pointer_rtx,
900
                                 GEN_INT (-128)));
901
          xsize = 128 - 4 * num_regs_to_save;
902
          size -= xsize;
903
          break;
904
 
905
        case save_sp_merge:
906
        case save_a0_merge:
907
          emit_insn (gen_addsi3 (stack_pointer_rtx,
908
                                 stack_pointer_rtx,
909
                                 GEN_INT (-(size + 4 * num_regs_to_save))));
910
          /* We'll have to adjust FP register saves according to the
911
             frame size.  */
912
          xsize = size;
913
          /* Since we've already created the stack frame, don't do it
914
             again at the end of the function.  */
915
          size = 0;
916
          break;
917
 
918
        default:
919
          gcc_unreachable ();
920
        }
921
 
922
      /* Now prepare register a0, if we have decided to use it.  */
923
      switch (strategy)
924
        {
925
        case save_sp_merge:
926
        case save_sp_no_merge:
927
        case save_sp_partial_merge:
928
          reg = 0;
929
          break;
930
 
931
        case save_a0_merge:
932
        case save_a0_no_merge:
933
          reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
934
          emit_insn (gen_movsi (reg, stack_pointer_rtx));
935
          if (xsize)
936
            emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
937
          reg = gen_rtx_POST_INC (SImode, reg);
938
          break;
939
 
940
        default:
941
          gcc_unreachable ();
942
        }
943
 
944
      /* Now actually save the FP registers.  */
945
      for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
946
        if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
947
          {
948
            rtx addr;
949
 
950
            if (reg)
951
              addr = reg;
952
            else
953
              {
954
                /* If we aren't using `a0', use an SP offset.  */
955
                if (xsize)
956
                  {
957
                    addr = gen_rtx_PLUS (SImode,
958
                                         stack_pointer_rtx,
959
                                         GEN_INT (xsize));
960
                  }
961
                else
962
                  addr = stack_pointer_rtx;
963
 
964
                xsize += 4;
965
              }
966
 
967
            insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
968
                                         gen_rtx_REG (SImode, i)));
969
 
970
            RTX_FRAME_RELATED_P (insn) = 1;
971
          }
972
    }
973
 
974
  /* Now put the frame pointer into the frame pointer register.  */
975
  if (frame_pointer_needed)
976
    emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
977
 
978
  /* Allocate stack for this frame.  */
979
  if (size)
980
    emit_insn (gen_addsi3 (stack_pointer_rtx,
981
                           stack_pointer_rtx,
982
                           GEN_INT (-size)));
983
  if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
984
    emit_insn (gen_GOTaddr2picreg ());
985
}
986
 
987
void
988
expand_epilogue (void)
989
{
990
  HOST_WIDE_INT size;
991
 
992
  /* SIZE includes the fixed stack space needed for function calls.  */
993
  size = get_frame_size () + crtl->outgoing_args_size;
994
  size += (crtl->outgoing_args_size ? 4 : 0);
995
 
996
  if (TARGET_AM33_2 && fp_regs_to_save ())
997
    {
998
      int num_regs_to_save = fp_regs_to_save (), i;
999
      rtx reg = 0;
1000
 
1001
      /* We have several options to restore FP registers.  We could
1002
         load them from SP offsets, but, if there are enough FP
1003
         registers to restore, we win if we use a post-increment
1004
         addressing mode.  */
1005
 
1006
      /* If we have a frame pointer, it's the best option, because we
1007
         already know it has the value we want.  */
1008
      if (frame_pointer_needed)
1009
        reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1010
      /* Otherwise, we may use `a1', since it's call-clobbered and
1011
         it's never used for return values.  But only do so if it's
1012
         smaller than using SP offsets.  */
1013
      else
1014
        {
1015
          enum { restore_sp_post_adjust,
1016
                 restore_sp_pre_adjust,
1017
                 restore_sp_partial_adjust,
1018
                 restore_a1 } strategy;
1019
          unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1020
 
1021
          /* Consider using sp offsets before adjusting sp.  */
1022
          /* Insn: fmov (##,sp),fs#, for each fs# to be restored.  */
1023
          this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1024
          /* If size is too large, we'll have to adjust SP with an
1025
                 add.  */
1026
          if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1027
            {
1028
              /* Insn: add size + 4 * num_regs_to_save, sp.  */
1029
              this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1030
            }
1031
          /* If we don't have to restore any non-FP registers,
1032
                 we'll be able to save one byte by using rets.  */
1033
          if (! REG_SAVE_BYTES)
1034
            this_strategy_size--;
1035
 
1036
          if (this_strategy_size < strategy_size)
1037
            {
1038
              strategy = restore_sp_post_adjust;
1039
              strategy_size = this_strategy_size;
1040
            }
1041
 
1042
          /* Consider using sp offsets after adjusting sp.  */
1043
          /* Insn: add size, sp.  */
1044
          this_strategy_size = SIZE_ADD_SP (size);
1045
          /* Insn: fmov (##,sp),fs#, for each fs# to be restored.  */
1046
          this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1047
          /* We're going to use ret to release the FP registers
1048
                 save area, so, no savings.  */
1049
 
1050
          if (this_strategy_size < strategy_size)
1051
            {
1052
              strategy = restore_sp_pre_adjust;
1053
              strategy_size = this_strategy_size;
1054
            }
1055
 
1056
          /* Consider using sp offsets after partially adjusting sp.
1057
             When size is close to 32Kb, we may be able to adjust SP
1058
             with an imm16 add instruction while still using fmov
1059
             (d8,sp).  */
1060
          if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1061
            {
1062
              /* Insn: add size + 4 * num_regs_to_save
1063
                                + REG_SAVE_BYTES - 252,sp.  */
1064
              this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1065
                                                + REG_SAVE_BYTES - 252);
1066
              /* Insn: fmov (##,sp),fs#, fo each fs# to be restored.  */
1067
              this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1068
                                                  - 4 * num_regs_to_save,
1069
                                                  num_regs_to_save);
1070
              /* We're going to use ret to release the FP registers
1071
                 save area, so, no savings.  */
1072
 
1073
              if (this_strategy_size < strategy_size)
1074
                {
1075
                  strategy = restore_sp_partial_adjust;
1076
                  strategy_size = this_strategy_size;
1077
                }
1078
            }
1079
 
1080
          /* Consider using a1 in post-increment mode, as long as the
1081
             user hasn't changed the calling conventions of a1.  */
1082
          if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1083
              && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1084
            {
1085
              /* Insn: mov sp,a1.  */
1086
              this_strategy_size = 1;
1087
              if (size)
1088
                {
1089
                  /* Insn: add size,a1.  */
1090
                  this_strategy_size += SIZE_ADD_AX (size);
1091
                }
1092
              /* Insn: fmov (a1+),fs#, for each fs# to be restored.  */
1093
              this_strategy_size += 3 * num_regs_to_save;
1094
              /* If size is large enough, we may be able to save a
1095
                 couple of bytes.  */
1096
              if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1097
                {
1098
                  /* Insn: mov a1,sp.  */
1099
                  this_strategy_size += 2;
1100
                }
1101
              /* If we don't have to restore any non-FP registers,
1102
                 we'll be able to save one byte by using rets.  */
1103
              if (! REG_SAVE_BYTES)
1104
                this_strategy_size--;
1105
 
1106
              if (this_strategy_size < strategy_size)
1107
                {
1108
                  strategy = restore_a1;
1109
                  strategy_size = this_strategy_size;
1110
                }
1111
            }
1112
 
1113
          switch (strategy)
1114
            {
1115
            case restore_sp_post_adjust:
1116
              break;
1117
 
1118
            case restore_sp_pre_adjust:
1119
              emit_insn (gen_addsi3 (stack_pointer_rtx,
1120
                                     stack_pointer_rtx,
1121
                                     GEN_INT (size)));
1122
              size = 0;
1123
              break;
1124
 
1125
            case restore_sp_partial_adjust:
1126
              emit_insn (gen_addsi3 (stack_pointer_rtx,
1127
                                     stack_pointer_rtx,
1128
                                     GEN_INT (size + 4 * num_regs_to_save
1129
                                              + REG_SAVE_BYTES - 252)));
1130
              size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1131
              break;
1132
 
1133
            case restore_a1:
1134
              reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1135
              emit_insn (gen_movsi (reg, stack_pointer_rtx));
1136
              if (size)
1137
                emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1138
              break;
1139
 
1140
            default:
1141
              gcc_unreachable ();
1142
            }
1143
        }
1144
 
1145
      /* Adjust the selected register, if any, for post-increment.  */
1146
      if (reg)
1147
        reg = gen_rtx_POST_INC (SImode, reg);
1148
 
1149
      for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1150
        if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1151
          {
1152
            rtx addr;
1153
 
1154
            if (reg)
1155
              addr = reg;
1156
            else if (size)
1157
              {
1158
                /* If we aren't using a post-increment register, use an
1159
                   SP offset.  */
1160
                addr = gen_rtx_PLUS (SImode,
1161
                                     stack_pointer_rtx,
1162
                                     GEN_INT (size));
1163
              }
1164
            else
1165
              addr = stack_pointer_rtx;
1166
 
1167
            size += 4;
1168
 
1169
            emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1170
                                  gen_rtx_MEM (SImode, addr)));
1171
          }
1172
 
1173
      /* If we were using the restore_a1 strategy and the number of
1174
         bytes to be released won't fit in the `ret' byte, copy `a1'
1175
         to `sp', to avoid having to use `add' to adjust it.  */
1176
      if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1177
        {
1178
          emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1179
          size = 0;
1180
        }
1181
    }
1182
 
1183
  /* Maybe cut back the stack, except for the register save area.
1184
 
1185
     If the frame pointer exists, then use the frame pointer to
1186
     cut back the stack.
1187
 
1188
     If the stack size + register save area is more than 255 bytes,
1189
     then the stack must be cut back here since the size + register
1190
     save size is too big for a ret/retf instruction.
1191
 
1192
     Else leave it alone, it will be cut back as part of the
1193
     ret/retf instruction, or there wasn't any stack to begin with.
1194
 
1195
     Under no circumstances should the register save area be
1196
     deallocated here, that would leave a window where an interrupt
1197
     could occur and trash the register save area.  */
1198
  if (frame_pointer_needed)
1199
    {
1200
      emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1201
      size = 0;
1202
    }
1203
  else if (size + REG_SAVE_BYTES > 255)
1204
    {
1205
      emit_insn (gen_addsi3 (stack_pointer_rtx,
1206
                             stack_pointer_rtx,
1207
                             GEN_INT (size)));
1208
      size = 0;
1209
    }
1210
 
1211
  /* Adjust the stack and restore callee-saved registers, if any.  */
1212
  if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1213
      || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1214
      || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1215
      || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1216
      || frame_pointer_needed)
1217
    emit_jump_insn (gen_return_internal_regs
1218
                    (GEN_INT (size + REG_SAVE_BYTES)));
1219
  else
1220
    emit_jump_insn (gen_return_internal ());
1221
}
1222
 
1223
/* Update the condition code from the insn.  */
1224
 
1225
void
1226
notice_update_cc (rtx body, rtx insn)
1227
{
1228
  switch (get_attr_cc (insn))
1229
    {
1230
    case CC_NONE:
1231
      /* Insn does not affect CC at all.  */
1232
      break;
1233
 
1234
    case CC_NONE_0HIT:
1235
      /* Insn does not change CC, but the 0'th operand has been changed.  */
1236
      if (cc_status.value1 != 0
1237
          && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1238
        cc_status.value1 = 0;
1239
      break;
1240
 
1241
    case CC_SET_ZN:
1242
      /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1243
         V,C are unusable.  */
1244
      CC_STATUS_INIT;
1245
      cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1246
      cc_status.value1 = recog_data.operand[0];
1247
      break;
1248
 
1249
    case CC_SET_ZNV:
1250
      /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1251
         C is unusable.  */
1252
      CC_STATUS_INIT;
1253
      cc_status.flags |= CC_NO_CARRY;
1254
      cc_status.value1 = recog_data.operand[0];
1255
      break;
1256
 
1257
    case CC_COMPARE:
1258
      /* The insn is a compare instruction.  */
1259
      CC_STATUS_INIT;
1260
      cc_status.value1 = SET_SRC (body);
1261
      if (GET_CODE (cc_status.value1) == COMPARE
1262
          && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1263
        cc_status.mdep.fpCC = 1;
1264
      break;
1265
 
1266
    case CC_CLOBBER:
1267
      /* Insn doesn't leave CC in a usable state.  */
1268
      CC_STATUS_INIT;
1269
      break;
1270
 
1271
    default:
1272
      gcc_unreachable ();
1273
    }
1274
}
1275
 
1276
/* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1277
   This function is for MATCH_PARALLEL and so assumes OP is known to be
1278
   parallel.  If OP is a multiple store, return a mask indicating which
1279
   registers it saves.  Return 0 otherwise.  */
1280
 
1281
int
1282
store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1283
{
1284
  int count;
1285
  int mask;
1286
  int i;
1287
  unsigned int last;
1288
  rtx elt;
1289
 
1290
  count = XVECLEN (op, 0);
1291
  if (count < 2)
1292
    return 0;
1293
 
1294
  /* Check that first instruction has the form (set (sp) (plus A B)) */
1295
  elt = XVECEXP (op, 0, 0);
1296
  if (GET_CODE (elt) != SET
1297
      || GET_CODE (SET_DEST (elt)) != REG
1298
      || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1299
      || GET_CODE (SET_SRC (elt)) != PLUS)
1300
    return 0;
1301
 
1302
  /* Check that A is the stack pointer and B is the expected stack size.
1303
     For OP to match, each subsequent instruction should push a word onto
1304
     the stack.  We therefore expect the first instruction to create
1305
     COUNT-1 stack slots.  */
1306
  elt = SET_SRC (elt);
1307
  if (GET_CODE (XEXP (elt, 0)) != REG
1308
      || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1309
      || GET_CODE (XEXP (elt, 1)) != CONST_INT
1310
      || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1311
    return 0;
1312
 
1313
  /* Now go through the rest of the vector elements.  They must be
1314
     ordered so that the first instruction stores the highest-numbered
1315
     register to the highest stack slot and that subsequent instructions
1316
     store a lower-numbered register to the slot below.
1317
 
1318
     LAST keeps track of the smallest-numbered register stored so far.
1319
     MASK is the set of stored registers.  */
1320
  last = LAST_EXTENDED_REGNUM + 1;
1321
  mask = 0;
1322
  for (i = 1; i < count; i++)
1323
    {
1324
      /* Check that element i is a (set (mem M) R) and that R is valid.  */
1325
      elt = XVECEXP (op, 0, i);
1326
      if (GET_CODE (elt) != SET
1327
          || GET_CODE (SET_DEST (elt)) != MEM
1328
          || GET_CODE (SET_SRC (elt)) != REG
1329
          || REGNO (SET_SRC (elt)) >= last)
1330
        return 0;
1331
 
1332
      /* R was OK, so provisionally add it to MASK.  We return 0 in any
1333
         case if the rest of the instruction has a flaw.  */
1334
      last = REGNO (SET_SRC (elt));
1335
      mask |= (1 << last);
1336
 
1337
      /* Check that M has the form (plus (sp) (const_int -I*4)) */
1338
      elt = XEXP (SET_DEST (elt), 0);
1339
      if (GET_CODE (elt) != PLUS
1340
          || GET_CODE (XEXP (elt, 0)) != REG
1341
          || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1342
          || GET_CODE (XEXP (elt, 1)) != CONST_INT
1343
          || INTVAL (XEXP (elt, 1)) != -i * 4)
1344
        return 0;
1345
    }
1346
 
1347
  /* All or none of the callee-saved extended registers must be in the set.  */
1348
  if ((mask & 0x3c000) != 0
1349
      && (mask & 0x3c000) != 0x3c000)
1350
    return 0;
1351
 
1352
  return mask;
1353
}
1354
 
1355
/* What (if any) secondary registers are needed to move IN with mode
1356
   MODE into a register in register class RCLASS.
1357
 
1358
   We might be able to simplify this.  */
1359
enum reg_class
1360
mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
1361
                                rtx in)
1362
{
1363
  rtx inner = in;
1364
 
1365
  /* Strip off any SUBREG expressions from IN.  Basically we want
1366
     to know if IN is a pseudo or (subreg (pseudo)) as those can
1367
     turn into MEMs during reload.  */
1368
  while (GET_CODE (inner) == SUBREG)
1369
    inner = SUBREG_REG (inner);
1370
 
1371
  /* Memory loads less than a full word wide can't have an
1372
     address or stack pointer destination.  They must use
1373
     a data register as an intermediate register.  */
1374
  if ((GET_CODE (in) == MEM
1375
       || (GET_CODE (inner) == REG
1376
           && REGNO (inner) >= FIRST_PSEUDO_REGISTER))
1377
      && (mode == QImode || mode == HImode)
1378
      && (rclass == ADDRESS_REGS || rclass == SP_REGS
1379
          || rclass == SP_OR_ADDRESS_REGS))
1380
    {
1381
      if (TARGET_AM33)
1382
        return DATA_OR_EXTENDED_REGS;
1383
      return DATA_REGS;
1384
    }
1385
 
1386
  /* We can't directly load sp + const_int into a data register;
1387
     we must use an address register as an intermediate.  */
1388
  if (rclass != SP_REGS
1389
      && rclass != ADDRESS_REGS
1390
      && rclass != SP_OR_ADDRESS_REGS
1391
      && rclass != SP_OR_EXTENDED_REGS
1392
      && rclass != ADDRESS_OR_EXTENDED_REGS
1393
      && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS
1394
      && (in == stack_pointer_rtx
1395
          || (GET_CODE (in) == PLUS
1396
              && (XEXP (in, 0) == stack_pointer_rtx
1397
                  || XEXP (in, 1) == stack_pointer_rtx))))
1398
    return ADDRESS_REGS;
1399
 
1400
  if (GET_CODE (in) == PLUS
1401
      && (XEXP (in, 0) == stack_pointer_rtx
1402
          || XEXP (in, 1) == stack_pointer_rtx))
1403
    return GENERAL_REGS;
1404
 
1405
  if (TARGET_AM33_2
1406
      && rclass == FP_REGS)
1407
    {
1408
      /* We can't load directly into an FP register from a
1409
         constant address.  */
1410
      if (GET_CODE (in) == MEM
1411
          && CONSTANT_ADDRESS_P (XEXP (in, 0)))
1412
        return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1413
 
1414
      /* Handle case were a pseudo may not get a hard register
1415
         but has an equivalent memory location defined.  */
1416
      if (GET_CODE (inner) == REG
1417
          && REGNO (inner) >= FIRST_PSEUDO_REGISTER
1418
          && reg_equiv_mem [REGNO (inner)]
1419
          && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
1420
        return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1421
    }
1422
 
1423
  /* Otherwise assume no secondary reloads are needed.  */
1424
  return NO_REGS;
1425
}
1426
 
1427
int
1428
initial_offset (int from, int to)
1429
{
1430
  /* The difference between the argument pointer and the frame pointer
1431
     is the size of the callee register save area.  */
1432
  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1433
    {
1434
      if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1435
          || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1436
          || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1437
          || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1438
          || fp_regs_to_save ()
1439
          || frame_pointer_needed)
1440
        return REG_SAVE_BYTES
1441
          + 4 * fp_regs_to_save ();
1442
      else
1443
        return 0;
1444
    }
1445
 
1446
  /* The difference between the argument pointer and the stack pointer is
1447
     the sum of the size of this function's frame, the callee register save
1448
     area, and the fixed stack space needed for function calls (if any).  */
1449
  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1450
    {
1451
      if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1452
          || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1453
          || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1454
          || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1455
          || fp_regs_to_save ()
1456
          || frame_pointer_needed)
1457
        return (get_frame_size () + REG_SAVE_BYTES
1458
                + 4 * fp_regs_to_save ()
1459
                + (crtl->outgoing_args_size
1460
                   ? crtl->outgoing_args_size + 4 : 0));
1461
      else
1462
        return (get_frame_size ()
1463
                + (crtl->outgoing_args_size
1464
                   ? crtl->outgoing_args_size + 4 : 0));
1465
    }
1466
 
1467
  /* The difference between the frame pointer and stack pointer is the sum
1468
     of the size of this function's frame and the fixed stack space needed
1469
     for function calls (if any).  */
1470
  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1471
    return (get_frame_size ()
1472
            + (crtl->outgoing_args_size
1473
               ? crtl->outgoing_args_size + 4 : 0));
1474
 
1475
  gcc_unreachable ();
1476
}
1477
 
1478
/* Worker function for TARGET_RETURN_IN_MEMORY.  */
1479
 
1480
static bool
1481
mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1482
{
1483
  /* Return values > 8 bytes in length in memory.  */
1484
  return (int_size_in_bytes (type) > 8
1485
          || int_size_in_bytes (type) == 0
1486
          || TYPE_MODE (type) == BLKmode);
1487
}
1488
 
1489
/* Flush the argument registers to the stack for a stdarg function;
1490
   return the new argument pointer.  */
1491
static rtx
1492
mn10300_builtin_saveregs (void)
1493
{
1494
  rtx offset, mem;
1495
  tree fntype = TREE_TYPE (current_function_decl);
1496
  int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1497
                   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1498
                       != void_type_node)))
1499
                ? UNITS_PER_WORD : 0);
1500
  alias_set_type set = get_varargs_alias_set ();
1501
 
1502
  if (argadj)
1503
    offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
1504
  else
1505
    offset = crtl->args.arg_offset_rtx;
1506
 
1507
  mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1508
  set_mem_alias_set (mem, set);
1509
  emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1510
 
1511
  mem = gen_rtx_MEM (SImode,
1512
                     plus_constant (crtl->args.internal_arg_pointer, 4));
1513
  set_mem_alias_set (mem, set);
1514
  emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1515
 
1516
  return copy_to_reg (expand_binop (Pmode, add_optab,
1517
                                    crtl->args.internal_arg_pointer,
1518
                                    offset, 0, 0, OPTAB_LIB_WIDEN));
1519
}
1520
 
1521
static void
1522
mn10300_va_start (tree valist, rtx nextarg)
1523
{
1524
  nextarg = expand_builtin_saveregs ();
1525
  std_expand_builtin_va_start (valist, nextarg);
1526
}
1527
 
1528
/* Return true when a parameter should be passed by reference.  */
1529
 
1530
static bool
1531
mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1532
                           enum machine_mode mode, const_tree type,
1533
                           bool named ATTRIBUTE_UNUSED)
1534
{
1535
  unsigned HOST_WIDE_INT size;
1536
 
1537
  if (type)
1538
    size = int_size_in_bytes (type);
1539
  else
1540
    size = GET_MODE_SIZE (mode);
1541
 
1542
  return (size > 8 || size == 0);
1543
}
1544
 
1545
/* Return an RTX to represent where a value with mode MODE will be returned
1546
   from a function.  If the result is NULL_RTX, the argument is pushed.  */
1547
 
1548
rtx
1549
function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1550
              tree type, int named ATTRIBUTE_UNUSED)
1551
{
1552
  rtx result = NULL_RTX;
1553
  int size, align;
1554
 
1555
  /* We only support using 2 data registers as argument registers.  */
1556
  int nregs = 2;
1557
 
1558
  /* Figure out the size of the object to be passed.  */
1559
  if (mode == BLKmode)
1560
    size = int_size_in_bytes (type);
1561
  else
1562
    size = GET_MODE_SIZE (mode);
1563
 
1564
  /* Figure out the alignment of the object to be passed.  */
1565
  align = size;
1566
 
1567
  cum->nbytes = (cum->nbytes + 3) & ~3;
1568
 
1569
  /* Don't pass this arg via a register if all the argument registers
1570
     are used up.  */
1571
  if (cum->nbytes > nregs * UNITS_PER_WORD)
1572
    return result;
1573
 
1574
  /* Don't pass this arg via a register if it would be split between
1575
     registers and memory.  */
1576
  if (type == NULL_TREE
1577
      && cum->nbytes + size > nregs * UNITS_PER_WORD)
1578
    return result;
1579
 
1580
  switch (cum->nbytes / UNITS_PER_WORD)
1581
    {
1582
    case 0:
1583
      result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1584
      break;
1585
    case 1:
1586
      result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1587
      break;
1588
    default:
1589
      break;
1590
    }
1591
 
1592
  return result;
1593
}
1594
 
1595
/* Return the number of bytes of registers to use for an argument passed
1596
   partially in registers and partially in memory.  */
1597
 
1598
static int
1599
mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1600
                           tree type, bool named ATTRIBUTE_UNUSED)
1601
{
1602
  int size, align;
1603
 
1604
  /* We only support using 2 data registers as argument registers.  */
1605
  int nregs = 2;
1606
 
1607
  /* Figure out the size of the object to be passed.  */
1608
  if (mode == BLKmode)
1609
    size = int_size_in_bytes (type);
1610
  else
1611
    size = GET_MODE_SIZE (mode);
1612
 
1613
  /* Figure out the alignment of the object to be passed.  */
1614
  align = size;
1615
 
1616
  cum->nbytes = (cum->nbytes + 3) & ~3;
1617
 
1618
  /* Don't pass this arg via a register if all the argument registers
1619
     are used up.  */
1620
  if (cum->nbytes > nregs * UNITS_PER_WORD)
1621
    return 0;
1622
 
1623
  if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1624
    return 0;
1625
 
1626
  /* Don't pass this arg via a register if it would be split between
1627
     registers and memory.  */
1628
  if (type == NULL_TREE
1629
      && cum->nbytes + size > nregs * UNITS_PER_WORD)
1630
    return 0;
1631
 
1632
  return nregs * UNITS_PER_WORD - cum->nbytes;
1633
}
1634
 
1635
/* Return the location of the function's value.  This will be either
1636
   $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1637
   $d0 and $a0 if the -mreturn-pointer-on-do flag is set.  Note that
1638
   we only return the PARALLEL for outgoing values; we do not want
1639
   callers relying on this extra copy.  */
1640
 
1641
static rtx
1642
mn10300_function_value (const_tree valtype,
1643
                        const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1644
                        bool outgoing)
1645
{
1646
  rtx rv;
1647
  enum machine_mode mode = TYPE_MODE (valtype);
1648
 
1649
  if (! POINTER_TYPE_P (valtype))
1650
    return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1651
  else if (! TARGET_PTR_A0D0 || ! outgoing
1652
           || cfun->returns_struct)
1653
    return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1654
 
1655
  rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1656
  XVECEXP (rv, 0, 0)
1657
    = gen_rtx_EXPR_LIST (VOIDmode,
1658
                         gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1659
                         GEN_INT (0));
1660
 
1661
  XVECEXP (rv, 0, 1)
1662
    = gen_rtx_EXPR_LIST (VOIDmode,
1663
                         gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1664
                         GEN_INT (0));
1665
  return rv;
1666
}
1667
 
1668
/* Implements TARGET_LIBCALL_VALUE.  */
1669
 
1670
static rtx
1671
mn10300_libcall_value (enum machine_mode mode,
1672
                       const_rtx fun ATTRIBUTE_UNUSED)
1673
{
1674
  return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1675
}
1676
 
1677
/* Implements FUNCTION_VALUE_REGNO_P.  */
1678
 
1679
bool
1680
mn10300_function_value_regno_p (const unsigned int regno)
1681
{
1682
 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1683
}
1684
 
1685
/* Output a tst insn.  */
1686
const char *
1687
output_tst (rtx operand, rtx insn)
1688
{
1689
  rtx temp;
1690
  int past_call = 0;
1691
 
1692
  /* We can save a byte if we can find a register which has the value
1693
     zero in it.  */
1694
  temp = PREV_INSN (insn);
1695
  while (optimize && temp)
1696
    {
1697
      rtx set;
1698
 
1699
      /* We allow the search to go through call insns.  We record
1700
         the fact that we've past a CALL_INSN and reject matches which
1701
         use call clobbered registers.  */
1702
      if (GET_CODE (temp) == CODE_LABEL
1703
          || GET_CODE (temp) == JUMP_INSN
1704
          || GET_CODE (temp) == BARRIER)
1705
        break;
1706
 
1707
      if (GET_CODE (temp) == CALL_INSN)
1708
        past_call = 1;
1709
 
1710
      if (GET_CODE (temp) == NOTE)
1711
        {
1712
          temp = PREV_INSN (temp);
1713
          continue;
1714
        }
1715
 
1716
      /* It must be an insn, see if it is a simple set.  */
1717
      set = single_set (temp);
1718
      if (!set)
1719
        {
1720
          temp = PREV_INSN (temp);
1721
          continue;
1722
        }
1723
 
1724
      /* Are we setting a data register to zero (this does not win for
1725
         address registers)?
1726
 
1727
         If it's a call clobbered register, have we past a call?
1728
 
1729
         Make sure the register we find isn't the same as ourself;
1730
         the mn10300 can't encode that.
1731
 
1732
         ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1733
         so the code to detect calls here isn't doing anything useful.  */
1734
      if (REG_P (SET_DEST (set))
1735
          && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1736
          && !reg_set_between_p (SET_DEST (set), temp, insn)
1737
          && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1738
              == REGNO_REG_CLASS (REGNO (operand)))
1739
          && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1740
          && REGNO (SET_DEST (set)) != REGNO (operand)
1741
          && (!past_call
1742
              || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1743
        {
1744
          rtx xoperands[2];
1745
          xoperands[0] = operand;
1746
          xoperands[1] = SET_DEST (set);
1747
 
1748
          output_asm_insn ("cmp %1,%0", xoperands);
1749
          return "";
1750
        }
1751
 
1752
      if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1753
          && REG_P (SET_DEST (set))
1754
          && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1755
          && !reg_set_between_p (SET_DEST (set), temp, insn)
1756
          && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1757
              != REGNO_REG_CLASS (REGNO (operand)))
1758
          && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1759
          && REGNO (SET_DEST (set)) != REGNO (operand)
1760
          && (!past_call
1761
              || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1762
        {
1763
          rtx xoperands[2];
1764
          xoperands[0] = operand;
1765
          xoperands[1] = SET_DEST (set);
1766
 
1767
          output_asm_insn ("cmp %1,%0", xoperands);
1768
          return "";
1769
        }
1770
      temp = PREV_INSN (temp);
1771
    }
1772
  return "cmp 0,%0";
1773
}
1774
 
1775
int
1776
impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1777
{
1778
  if (GET_CODE (op) != PLUS)
1779
    return 0;
1780
 
1781
  if (XEXP (op, 0) == stack_pointer_rtx
1782
      || XEXP (op, 1) == stack_pointer_rtx)
1783
    return 1;
1784
 
1785
  return 0;
1786
}
1787
 
1788
/* Similarly, but when using a zero_extract pattern for a btst where
1789
   the source operand might end up in memory.  */
1790
int
1791
mask_ok_for_mem_btst (int len, int bit)
1792
{
1793
  unsigned int mask = 0;
1794
 
1795
  while (len > 0)
1796
    {
1797
      mask |= (1 << bit);
1798
      bit++;
1799
      len--;
1800
    }
1801
 
1802
  /* MASK must bit into an 8bit value.  */
1803
  return (((mask & 0xff) == mask)
1804
          || ((mask & 0xff00) == mask)
1805
          || ((mask & 0xff0000) == mask)
1806
          || ((mask & 0xff000000) == mask));
1807
}
1808
 
1809
/* Return 1 if X contains a symbolic expression.  We know these
1810
   expressions will have one of a few well defined forms, so
1811
   we need only check those forms.  */
1812
int
1813
symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1814
{
1815
  switch (GET_CODE (op))
1816
    {
1817
    case SYMBOL_REF:
1818
    case LABEL_REF:
1819
      return 1;
1820
    case CONST:
1821
      op = XEXP (op, 0);
1822
      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1823
               || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1824
              && GET_CODE (XEXP (op, 1)) == CONST_INT);
1825
    default:
1826
      return 0;
1827
    }
1828
}
1829
 
1830
/* Try machine dependent ways of modifying an illegitimate address
1831
   to be legitimate.  If we find one, return the new valid address.
1832
   This macro is used in only one place: `memory_address' in explow.c.
1833
 
1834
   OLDX is the address as it was before break_out_memory_refs was called.
1835
   In some cases it is useful to look at this to decide what needs to be done.
1836
 
1837
   Normally it is always safe for this macro to do nothing.  It exists to
1838
   recognize opportunities to optimize the output.
1839
 
1840
   But on a few ports with segmented architectures and indexed addressing
1841
   (mn10300, hppa) it is used to rewrite certain problematical addresses.  */
1842
rtx
1843
mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1844
                            enum machine_mode mode ATTRIBUTE_UNUSED)
1845
{
1846
  if (flag_pic && ! legitimate_pic_operand_p (x))
1847
    x = legitimize_pic_address (oldx, NULL_RTX);
1848
 
1849
  /* Uh-oh.  We might have an address for x[n-100000].  This needs
1850
     special handling to avoid creating an indexed memory address
1851
     with x-100000 as the base.  */
1852
  if (GET_CODE (x) == PLUS
1853
      && symbolic_operand (XEXP (x, 1), VOIDmode))
1854
    {
1855
      /* Ugly.  We modify things here so that the address offset specified
1856
         by the index expression is computed first, then added to x to form
1857
         the entire address.  */
1858
 
1859
      rtx regx1, regy1, regy2, y;
1860
 
1861
      /* Strip off any CONST.  */
1862
      y = XEXP (x, 1);
1863
      if (GET_CODE (y) == CONST)
1864
        y = XEXP (y, 0);
1865
 
1866
      if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1867
        {
1868
          regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1869
          regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1870
          regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1871
          regx1 = force_reg (Pmode,
1872
                             gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2));
1873
          return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1874
        }
1875
    }
1876
  return x;
1877
}
1878
 
1879
/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1880
   @GOTOFF in `reg'.  */
1881
rtx
1882
legitimize_pic_address (rtx orig, rtx reg)
1883
{
1884
  if (GET_CODE (orig) == LABEL_REF
1885
      || (GET_CODE (orig) == SYMBOL_REF
1886
          && (CONSTANT_POOL_ADDRESS_P (orig)
1887
              || ! MN10300_GLOBAL_P (orig))))
1888
    {
1889
      if (reg == 0)
1890
        reg = gen_reg_rtx (Pmode);
1891
 
1892
      emit_insn (gen_symGOTOFF2reg (reg, orig));
1893
      return reg;
1894
    }
1895
  else if (GET_CODE (orig) == SYMBOL_REF)
1896
    {
1897
      if (reg == 0)
1898
        reg = gen_reg_rtx (Pmode);
1899
 
1900
      emit_insn (gen_symGOT2reg (reg, orig));
1901
      return reg;
1902
    }
1903
  return orig;
1904
}
1905
 
1906
/* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1907
   isn't protected by a PIC unspec; nonzero otherwise.  */
1908
int
1909
legitimate_pic_operand_p (rtx x)
1910
{
1911
  register const char *fmt;
1912
  register int i;
1913
 
1914
  if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1915
    return 0;
1916
 
1917
  if (GET_CODE (x) == UNSPEC
1918
      && (XINT (x, 1) == UNSPEC_PIC
1919
          || XINT (x, 1) == UNSPEC_GOT
1920
          || XINT (x, 1) == UNSPEC_GOTOFF
1921
          || XINT (x, 1) == UNSPEC_PLT
1922
          || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1923
      return 1;
1924
 
1925
  fmt = GET_RTX_FORMAT (GET_CODE (x));
1926
  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1927
    {
1928
      if (fmt[i] == 'E')
1929
        {
1930
          register int j;
1931
 
1932
          for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1933
            if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1934
              return 0;
1935
        }
1936
      else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1937
        return 0;
1938
    }
1939
 
1940
  return 1;
1941
}
1942
 
1943
/* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1944
   legitimate, and FALSE otherwise.
1945
 
1946
   On the mn10300, the value in the address register must be
1947
   in the same memory space/segment as the effective address.
1948
 
1949
   This is problematical for reload since it does not understand
1950
   that base+index != index+base in a memory reference.
1951
 
1952
   Note it is still possible to use reg+reg addressing modes,
1953
   it's just much more difficult.  For a discussion of a possible
1954
   workaround and solution, see the comments in pa.c before the
1955
   function record_unscaled_index_insn_codes.  */
1956
 
1957
bool
1958
mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1959
{
1960
  if (CONSTANT_ADDRESS_P (x)
1961
      && (! flag_pic || legitimate_pic_operand_p (x)))
1962
    return TRUE;
1963
 
1964
  if (RTX_OK_FOR_BASE_P (x, strict))
1965
    return TRUE;
1966
 
1967
  if (TARGET_AM33
1968
      && GET_CODE (x) == POST_INC
1969
      && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1970
      && (mode == SImode || mode == SFmode || mode == HImode))
1971
    return TRUE;
1972
 
1973
  if (GET_CODE (x) == PLUS)
1974
    {
1975
      rtx base = 0, index = 0;
1976
 
1977
      if (REG_P (XEXP (x, 0))
1978
          && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict))
1979
        {
1980
          base = XEXP (x, 0);
1981
          index = XEXP (x, 1);
1982
        }
1983
 
1984
      if (REG_P (XEXP (x, 1))
1985
          && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict))
1986
        {
1987
          base = XEXP (x, 1);
1988
          index = XEXP (x, 0);
1989
        }
1990
 
1991
      if (base != 0 && index != 0)
1992
        {
1993
          if (GET_CODE (index) == CONST_INT)
1994
            return TRUE;
1995
          if (GET_CODE (index) == CONST
1996
              && GET_CODE (XEXP (index, 0)) != PLUS
1997
              && (! flag_pic
1998
                  || legitimate_pic_operand_p (index)))
1999
            return TRUE;
2000
        }
2001
    }
2002
 
2003
  return FALSE;
2004
}
2005
 
2006
static int
2007
mn10300_address_cost_1 (rtx x, int *unsig)
2008
{
2009
  switch (GET_CODE (x))
2010
    {
2011
    case REG:
2012
      switch (REGNO_REG_CLASS (REGNO (x)))
2013
        {
2014
        case SP_REGS:
2015
          *unsig = 1;
2016
          return 0;
2017
 
2018
        case ADDRESS_REGS:
2019
          return 1;
2020
 
2021
        case DATA_REGS:
2022
        case EXTENDED_REGS:
2023
        case FP_REGS:
2024
          return 3;
2025
 
2026
        case NO_REGS:
2027
          return 5;
2028
 
2029
        default:
2030
          gcc_unreachable ();
2031
        }
2032
 
2033
    case PLUS:
2034
    case MINUS:
2035
    case ASHIFT:
2036
    case AND:
2037
    case IOR:
2038
      return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
2039
              + mn10300_address_cost_1 (XEXP (x, 1), unsig));
2040
 
2041
    case EXPR_LIST:
2042
    case SUBREG:
2043
    case MEM:
2044
      return mn10300_address_cost (XEXP (x, 0), !optimize_size);
2045
 
2046
    case ZERO_EXTEND:
2047
      *unsig = 1;
2048
      return mn10300_address_cost_1 (XEXP (x, 0), unsig);
2049
 
2050
    case CONST_INT:
2051
      if (INTVAL (x) == 0)
2052
        return 0;
2053
      if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
2054
        return 1;
2055
      if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
2056
        return 3;
2057
      if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
2058
        return 5;
2059
      return 7;
2060
 
2061
    case CONST:
2062
    case SYMBOL_REF:
2063
    case LABEL_REF:
2064
      return 8;
2065
 
2066
    default:
2067
      gcc_unreachable ();
2068
 
2069
    }
2070
}
2071
 
2072
static int
2073
mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
2074
{
2075
  int s = 0;
2076
  return mn10300_address_cost_1 (x, &s);
2077
}
2078
 
2079
static bool
2080
mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED)
2081
{
2082
  switch (code)
2083
    {
2084
    case CONST_INT:
2085
      /* Zeros are extremely cheap.  */
2086
      if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
2087
        *total = 0;
2088
      /* If it fits in 8 bits, then it's still relatively cheap.  */
2089
      else if (INT_8_BITS (INTVAL (x)))
2090
        *total = 1;
2091
      /* This is the "base" cost, includes constants where either the
2092
         upper or lower 16bits are all zeros.  */
2093
      else if (INT_16_BITS (INTVAL (x))
2094
               || (INTVAL (x) & 0xffff) == 0
2095
               || (INTVAL (x) & 0xffff0000) == 0)
2096
        *total = 2;
2097
      else
2098
        *total = 4;
2099
      return true;
2100
 
2101
    case CONST:
2102
    case LABEL_REF:
2103
    case SYMBOL_REF:
2104
      /* These are more costly than a CONST_INT, but we can relax them,
2105
         so they're less costly than a CONST_DOUBLE.  */
2106
      *total = 6;
2107
      return true;
2108
 
2109
    case CONST_DOUBLE:
2110
      /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2111
         so their cost is very high.  */
2112
      *total = 8;
2113
      return true;
2114
 
2115
    case ZERO_EXTRACT:
2116
      /* This is cheap, we can use btst.  */
2117
      if (outer_code == COMPARE)
2118
        *total = 0;
2119
      return false;
2120
 
2121
   /* ??? This probably needs more work.  */
2122
    case MOD:
2123
    case DIV:
2124
    case MULT:
2125
      *total = 8;
2126
      return true;
2127
 
2128
    default:
2129
      return false;
2130
    }
2131
}
2132
 
2133
/* Check whether a constant used to initialize a DImode or DFmode can
2134
   use a clr instruction.  The code here must be kept in sync with
2135
   movdf and movdi.  */
2136
 
2137
bool
2138
mn10300_wide_const_load_uses_clr (rtx operands[2])
2139
{
2140
  long val[2];
2141
 
2142
  if (GET_CODE (operands[0]) != REG
2143
      || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2144
    return false;
2145
 
2146
  switch (GET_CODE (operands[1]))
2147
    {
2148
    case CONST_INT:
2149
      {
2150
        rtx low, high;
2151
        split_double (operands[1], &low, &high);
2152
        val[0] = INTVAL (low);
2153
        val[1] = INTVAL (high);
2154
      }
2155
      break;
2156
 
2157
    case CONST_DOUBLE:
2158
      if (GET_MODE (operands[1]) == DFmode)
2159
        {
2160
          REAL_VALUE_TYPE rv;
2161
 
2162
          REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2163
          REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2164
        }
2165
      else if (GET_MODE (operands[1]) == VOIDmode
2166
               || GET_MODE (operands[1]) == DImode)
2167
        {
2168
          val[0] = CONST_DOUBLE_LOW (operands[1]);
2169
          val[1] = CONST_DOUBLE_HIGH (operands[1]);
2170
        }
2171
      break;
2172
 
2173
    default:
2174
      return false;
2175
    }
2176
 
2177
  return val[0] == 0 || val[1] == 0;
2178
}
2179
/* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2180
   may access it using GOTOFF instead of GOT.  */
2181
 
2182
static void
2183
mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2184
{
2185
  rtx symbol;
2186
 
2187
  if (GET_CODE (rtl) != MEM)
2188
    return;
2189
  symbol = XEXP (rtl, 0);
2190
  if (GET_CODE (symbol) != SYMBOL_REF)
2191
    return;
2192
 
2193
  if (flag_pic)
2194
    SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2195
}
2196
 
2197
/* Dispatch tables on the mn10300 are extremely expensive in terms of code
2198
   and readonly data size.  So we crank up the case threshold value to
2199
   encourage a series of if/else comparisons to implement many small switch
2200
   statements.  In theory, this value could be increased much more if we
2201
   were solely optimizing for space, but we keep it "reasonable" to avoid
2202
   serious code efficiency lossage.  */
2203
 
2204
unsigned int mn10300_case_values_threshold (void)
2205
{
2206
  return 6;
2207
}
2208
 
2209
/* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.  */
2210
 
2211
static void
2212
mn10300_asm_trampoline_template (FILE *f)
2213
{
2214
  fprintf (f, "\tadd -4,sp\n");
2215
  fprintf (f, "\t.long 0x0004fffa\n");
2216
  fprintf (f, "\tmov (0,sp),a0\n");
2217
  fprintf (f, "\tadd 4,sp\n");
2218
  fprintf (f, "\tmov (13,a0),a1\n");
2219
  fprintf (f, "\tmov (17,a0),a0\n");
2220
  fprintf (f, "\tjmp (a0)\n");
2221
  fprintf (f, "\t.long 0\n");
2222
  fprintf (f, "\t.long 0\n");
2223
}
2224
 
2225
/* Worker function for TARGET_TRAMPOLINE_INIT.  */
2226
 
2227
static void
2228
mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2229
{
2230
  rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2231
  rtx mem;
2232
 
2233
  emit_block_move (m_tramp, assemble_trampoline_template (),
2234
                   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2235
 
2236
  mem = adjust_address (m_tramp, SImode, 0x14);
2237
  emit_move_insn (mem, chain_value);
2238
  mem = adjust_address (m_tramp, SImode, 0x18);
2239
  emit_move_insn (mem, fnaddr);
2240
}
2241
 
2242
/* Output the assembler code for a C++ thunk function.
2243
   THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2244
   is the decl for the target function.  DELTA is an immediate constant
2245
   offset to be added to the THIS parameter.  If VCALL_OFFSET is nonzero
2246
   the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2247
   additionally added to THIS.  Finally jump to the entry point of
2248
   FUNCTION.  */
2249
 
2250
static void
2251
mn10300_asm_output_mi_thunk (FILE *        file,
2252
                             tree          thunk_fndecl ATTRIBUTE_UNUSED,
2253
                             HOST_WIDE_INT delta,
2254
                             HOST_WIDE_INT vcall_offset,
2255
                             tree          function)
2256
{
2257
  const char * _this;
2258
 
2259
  /* Get the register holding the THIS parameter.  Handle the case
2260
     where there is a hidden first argument for a returned structure.  */
2261
  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2262
    _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2263
  else
2264
    _this = reg_names [FIRST_ARGUMENT_REGNUM];
2265
 
2266
  fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2267
 
2268
  if (delta)
2269
    fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2270
 
2271
  if (vcall_offset)
2272
    {
2273
      const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2274
 
2275
      fprintf (file, "\tmov %s, %s\n", _this, scratch);
2276
      fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2277
      fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2278
      fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2279
      fprintf (file, "\tadd %s, %s\n", scratch, _this);
2280
    }
2281
 
2282
  fputs ("\tjmp ", file);
2283
  assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2284
  putc ('\n', file);
2285
}
2286
 
2287
/* Return true if mn10300_output_mi_thunk would be able to output the
2288
   assembler code for the thunk function specified by the arguments
2289
   it is passed, and false otherwise.  */
2290
 
2291
static bool
2292
mn10300_can_output_mi_thunk (const_tree    thunk_fndecl ATTRIBUTE_UNUSED,
2293
                             HOST_WIDE_INT delta        ATTRIBUTE_UNUSED,
2294
                             HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2295
                             const_tree    function     ATTRIBUTE_UNUSED)
2296
{
2297
  return true;
2298
}

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