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jeremybenn |
;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
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;; 2009, 2010 Free Software Foundation, Inc.
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399 |
jeremybenn |
;; Copyright (C) 2010 Embecosm Limited
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282 |
jeremybenn |
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;; Contributed by Damjan Lampret in 1999.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Floating point additions by Jungsook Yang
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;; Julius Baxter in 2010
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399 |
jeremybenn |
;; Updated for GCC 4.5 by Jeremy Bennett
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;; and Joern Rennecke in 2010
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282 |
jeremybenn |
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;; This file is part of GNU CC.
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;; This program is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 3 of the License, or (at your option)
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;; any later version.
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;;
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;; This program is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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;; more details.
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;;
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;; You should have received a copy of the GNU General Public License along
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;; with this program. If not, see . */
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399 |
jeremybenn |
(define_constants [
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414 |
jeremybenn |
(SP_REG 1)
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(FP_REG 2) ; hard frame pointer
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399 |
jeremybenn |
(CC_REG 34)
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414 |
jeremybenn |
;; unspec values
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(UNSPEC_FRAME 0)
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399 |
jeremybenn |
;; unspec_volatile values
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(UNSPECV_SIBCALL_EPILOGUE 0)
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])
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282 |
jeremybenn |
(include "predicates.md")
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399 |
jeremybenn |
(include "constraints.md")
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282 |
jeremybenn |
(define_attr "type"
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399 |
jeremybenn |
"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp,jump_restore"
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jeremybenn |
(const_string "unknown"))
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;; Number of machine instructions required to implement an insn.
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(define_attr "length" "" (const_int 1))
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;; Single delay slot after branch or jump instructions, wich may contain any
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;; instruction but another branch or jump.
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(define_delay (eq_attr "type" "branch,jump")
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[(and (eq_attr "type" "!branch,jump")
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(eq_attr "length" "1")) (nil) (nil)])
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;; ALU is modelled as a single functional unit, which is reserved for varying
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;; numbers of slots.
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;;
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;; I think this is all incorrect for the OR1K. The latency says when the
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;; result will be ready, not how long the pipeline takes to execute.
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(define_cpu_unit "or32_alu")
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(define_insn_reservation "bit_unit" 3 (eq_attr "type" "shift") "or32_alu")
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(define_insn_reservation "lsu_load" 3 (eq_attr "type" "load") "or32_alu*3")
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(define_insn_reservation "lsu_store" 2 (eq_attr "type" "store") "or32_alu")
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(define_insn_reservation "alu_unit" 2
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(eq_attr "type" "add,logic,extend,move,compare")
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"or32_alu")
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(define_insn_reservation "mul_unit" 16 (eq_attr "type" "mul") "or32_alu*16")
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;; Called after register allocation to add any instructions needed for the
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;; prologue. Using a prologue insn is favored compared to putting all of the
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;; instructions in output_function_prologue(), since it allows the scheduler
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;; to intermix instructions with the saves of the caller saved registers. In
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;; some cases, it might be necessary to emit a barrier instruction as the last
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;; insn to prevent such scheduling.
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(define_expand "prologue"
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[(use (const_int 1))]
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399 |
jeremybenn |
"TARGET_SCHED_LOGUE"
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282 |
jeremybenn |
{
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or32_expand_prologue ();
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DONE;
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})
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;; Called after register allocation to add any instructions needed for the
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;; epilogue. Using an epilogue insn is favored compared to putting all of the
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;; instructions in output_function_epilogue(), since it allows the scheduler
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;; to intermix instructions with the restores of the caller saved registers.
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;; In some cases, it might be necessary to emit a barrier instruction as the
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;; first insn to prevent such scheduling.
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(define_expand "epilogue"
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[(use (const_int 2))]
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jeremybenn |
"TARGET_SCHED_LOGUE"
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282 |
jeremybenn |
{
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jeremybenn |
or32_expand_epilogue (NULL_RTX);
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jeremybenn |
DONE;
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})
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jeremybenn |
(define_insn_and_split "sibcall_epilogue"
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[(unspec_volatile [(const_int 2)] UNSPECV_SIBCALL_EPILOGUE)]
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"TARGET_SCHED_LOGUE"
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"#"
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""
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[(pc)]
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jeremybenn |
{
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jeremybenn |
or32_expand_epilogue (curr_insn);
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jeremybenn |
DONE;
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})
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414 |
jeremybenn |
(define_insn "frame_dealloc_fp"
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[(set (reg:SI SP_REG) (reg:SI FP_REG))
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(clobber (mem:QI (plus:SI (reg:SI FP_REG)
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(unspec:SI [(const_int FP_REG)] UNSPEC_FRAME))))]
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""
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"l.ori\tr1,r2,0\t# deallocate frame"
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[(set_attr "type" "logic")
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(set_attr "length" "1")])
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(define_insn "frame_dealloc_sp"
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[(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 0 "nonmemory_operand" "r,I")))
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(clobber (mem:QI (plus:SI (reg:SI SP_REG)
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(unspec:SI [(const_int SP_REG)] UNSPEC_FRAME))))]
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""
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"@
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l.add\tr1,r1,%0
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l.addi\tr1,r1,%0"
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[(set_attr "type" "add")
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(set_attr "length" "1")])
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282 |
jeremybenn |
(define_insn "return_internal"
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[(return)
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(use (match_operand 0 "pmode_register_operand" ""))]
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399 |
jeremybenn |
"TARGET_SCHED_LOGUE"
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282 |
jeremybenn |
"l.jr \t%0%("
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[(set_attr "type" "jump")
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(set_attr "length" "1")])
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;;
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;; Sibcalls
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;;
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(define_expand "sibcall"
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[(parallel [(call (match_operand 0 "" "")
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(match_operand 1 "" ""))
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(use (match_operand 2 "" "")) ;; next_arg_reg
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(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
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399 |
jeremybenn |
""
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282 |
jeremybenn |
"
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{
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or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
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DONE;
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}")
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(define_expand "sibcall_value"
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[(set (match_operand 0 "" "")
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(call (match_operand:SI 1 "" "")
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(match_operand 2 "" "")))]
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399 |
jeremybenn |
""
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282 |
jeremybenn |
"
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{
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or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
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DONE;
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}")
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(define_insn "sibcall_internal"
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399 |
jeremybenn |
[(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,Rsc,r"))
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282 |
jeremybenn |
(match_operand 1 "" ""))
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(use (reg:SI 9))]
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399 |
jeremybenn |
""
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282 |
jeremybenn |
"@
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399 |
jeremybenn |
l.j\t%S0%(\t# sibcall s
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l.jr\t%0%(\t# sibcall Rsc
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l.jr\t%0\t\t# sibcall r%J0"
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[(set_attr "type" "jump,jump,jump_restore")])
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282 |
jeremybenn |
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;;
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;; movQI
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;;
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand" "")
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(match_operand:QI 1 "general_operand" ""))]
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""
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"
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if (can_create_pseudo_p())
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{
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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| 194 |
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rtx reg = gen_reg_rtx (SImode);
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emit_insn (gen_movsi (reg, operands[1]));
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operands[1] = gen_lowpart (QImode, reg);
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}
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if (GET_CODE (operands[1]) == MEM && optimize > 0)
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{
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| 201 |
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rtx reg = gen_reg_rtx (SImode);
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| 203 |
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emit_insn (gen_rtx_SET (SImode, reg,
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gen_rtx_ZERO_EXTEND (SImode,
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operands[1])));
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| 207 |
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operands[1] = gen_lowpart (QImode, reg);
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| 208 |
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}
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if (GET_CODE (operands[0]) != REG)
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| 210 |
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operands[1] = force_reg (QImode, operands[1]);
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| 211 |
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}
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| 212 |
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")
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| 213 |
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| 214 |
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(define_insn "*movqi_internal"
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| 215 |
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[(set (match_operand:QI 0 "nonimmediate_operand" "=m,r,r,r,r")
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| 216 |
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(match_operand:QI 1 "general_operand" "r,r,I,K,m"))]
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| 217 |
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""
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| 218 |
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"@
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| 219 |
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l.sb \t%0,%1\t # movqi
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| 220 |
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l.ori \t%0,%1,0\t # movqi: move reg to reg
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| 221 |
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l.addi \t%0,r0,%1\t # movqi: move immediate
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| 222 |
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l.ori \t%0,r0,%1\t # movqi: move immediate
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| 223 |
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l.lbz \t%0,%1\t # movqi"
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| 224 |
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[(set_attr "type" "store,add,add,logic,load")])
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| 225 |
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| 226 |
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| 227 |
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;;
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| 228 |
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;; movHI
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| 229 |
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;;
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| 230 |
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| 231 |
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(define_expand "movhi"
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| 232 |
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[(set (match_operand:HI 0 "general_operand" "")
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| 233 |
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(match_operand:HI 1 "general_operand" ""))]
|
| 234 |
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""
|
| 235 |
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"
|
| 236 |
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if (can_create_pseudo_p())
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| 237 |
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{
|
| 238 |
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if (GET_CODE (operands[1]) == CONST_INT)
|
| 239 |
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{
|
| 240 |
|
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rtx reg = gen_reg_rtx (SImode);
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| 241 |
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| 242 |
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emit_insn (gen_movsi (reg, operands[1]));
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| 243 |
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operands[1] = gen_lowpart (HImode, reg);
|
| 244 |
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}
|
| 245 |
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if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
| 246 |
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{
|
| 247 |
|
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rtx reg = gen_reg_rtx (SImode);
|
| 248 |
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|
|
| 249 |
|
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emit_insn (gen_rtx_SET (SImode, reg,
|
| 250 |
|
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gen_rtx_ZERO_EXTEND (SImode,
|
| 251 |
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operands[1])));
|
| 252 |
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operands[1] = gen_lowpart (HImode, reg);
|
| 253 |
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}
|
| 254 |
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if (GET_CODE (operands[0]) != REG)
|
| 255 |
|
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operands[1] = force_reg (HImode, operands[1]);
|
| 256 |
|
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}
|
| 257 |
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")
|
| 258 |
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|
|
| 259 |
|
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(define_insn "*movhi_internal"
|
| 260 |
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[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
| 261 |
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(match_operand:HI 1 "general_operand" "r,r,I,K,m"))]
|
| 262 |
|
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""
|
| 263 |
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"@
|
| 264 |
|
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l.sh \t%0,%1\t # movhi
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| 265 |
|
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l.ori \t%0,%1,0\t # movhi: move reg to reg
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| 266 |
|
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l.addi \t%0,r0,%1\t # movhi: move immediate
|
| 267 |
|
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l.ori \t%0,r0,%1\t # movhi: move immediate
|
| 268 |
|
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l.lhz \t%0,%1\t # movhi"
|
| 269 |
|
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[(set_attr "type" "store,add,add,logic,load")])
|
| 270 |
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|
|
| 271 |
|
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(define_expand "movsi"
|
| 272 |
|
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[(set (match_operand:SI 0 "general_operand" "")
|
| 273 |
|
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(match_operand:SI 1 "general_operand" ""))]
|
| 274 |
|
|
""
|
| 275 |
|
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{
|
| 276 |
|
|
/* Working with CONST_INTs is easier, so convert
|
| 277 |
|
|
a double if needed. */
|
| 278 |
|
|
|
| 279 |
|
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if (GET_CODE (operands[1]) == CONST_DOUBLE) {
|
| 280 |
|
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operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
|
| 281 |
|
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}
|
| 282 |
|
|
|
| 283 |
|
|
/* Handle sets of MEM first. */
|
| 284 |
|
|
if (GET_CODE (operands[0]) == MEM)
|
| 285 |
|
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{
|
| 286 |
|
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if (register_operand(operands[1], SImode)
|
| 287 |
|
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|| (operands[1] == const0_rtx))
|
| 288 |
|
|
goto movsi_is_ok;
|
| 289 |
|
|
|
| 290 |
|
|
if (! reload_in_progress)
|
| 291 |
|
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{
|
| 292 |
|
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operands[0] = validize_mem (operands[0]);
|
| 293 |
|
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operands[1] = force_reg (SImode, operands[1]);
|
| 294 |
|
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}
|
| 295 |
|
|
}
|
| 296 |
|
|
|
| 297 |
|
|
/* This makes sure we will not get rematched due to splittage. */
|
| 298 |
|
|
if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
|
| 299 |
|
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;
|
| 300 |
|
|
else if (CONSTANT_P (operands[1])
|
| 301 |
|
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&& GET_CODE (operands[1]) != HIGH
|
| 302 |
|
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&& GET_CODE (operands[1]) != LO_SUM)
|
| 303 |
|
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{
|
| 304 |
|
|
or32_emit_set_const32 (operands[0], operands[1]);
|
| 305 |
|
|
DONE;
|
| 306 |
|
|
}
|
| 307 |
|
|
movsi_is_ok:
|
| 308 |
|
|
;
|
| 309 |
|
|
})
|
| 310 |
|
|
|
| 311 |
|
|
;;
|
| 312 |
|
|
;; movSI
|
| 313 |
|
|
;;
|
| 314 |
|
|
|
| 315 |
|
|
(define_insn "*movsi_insn"
|
| 316 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
|
| 317 |
|
|
(match_operand:SI 1 "input_operand" "I,K,M,r,m,r"))]
|
| 318 |
|
|
"(register_operand (operands[0], SImode)
|
| 319 |
|
|
|| register_operand (operands[1], SImode)
|
| 320 |
|
|
|| (operands[1] == const0_rtx))"
|
| 321 |
|
|
"@
|
| 322 |
|
|
l.addi \t%0,r0,%1\t # move immediate I
|
| 323 |
|
|
l.ori \t%0,r0,%1\t # move immediate K
|
| 324 |
|
|
l.movhi \t%0,hi(%1)\t # move immediate M
|
| 325 |
|
|
l.ori \t%0,%1,0\t # move reg to reg
|
| 326 |
|
|
l.lwz \t%0,%1\t # SI load
|
| 327 |
|
|
l.sw \t%0,%1\t # SI store"
|
| 328 |
|
|
[(set_attr "type" "add,load,store,add,logic,move")
|
| 329 |
|
|
(set_attr "length" "1,1,1,1,1,1")])
|
| 330 |
|
|
|
| 331 |
399 |
jeremybenn |
(define_insn "movsi_lo_sum"
|
| 332 |
282 |
jeremybenn |
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 333 |
|
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
| 334 |
|
|
(match_operand:SI 2 "immediate_operand" "i")))]
|
| 335 |
|
|
""
|
| 336 |
|
|
"l.ori \t%0,%1,lo(%2)"
|
| 337 |
|
|
[(set_attr "type" "logic")
|
| 338 |
|
|
(set_attr "length" "1")])
|
| 339 |
|
|
|
| 340 |
399 |
jeremybenn |
(define_insn "movsi_high"
|
| 341 |
282 |
jeremybenn |
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 342 |
|
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
| 343 |
|
|
""
|
| 344 |
|
|
"l.movhi \t%0,hi(%1)"
|
| 345 |
|
|
[(set_attr "type" "move")
|
| 346 |
|
|
(set_attr "length" "1")])
|
| 347 |
|
|
|
| 348 |
399 |
jeremybenn |
(define_insn_and_split "movsi_insn_big"
|
| 349 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 350 |
282 |
jeremybenn |
(match_operand:SI 1 "immediate_operand" "i"))]
|
| 351 |
399 |
jeremybenn |
"GET_CODE (operands[1]) != CONST_INT"
|
| 352 |
282 |
jeremybenn |
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)"
|
| 353 |
399 |
jeremybenn |
;; the switch of or32 bfd to Rela allows us to schedule insns separately.
|
| 354 |
|
|
"&& reload_completed
|
| 355 |
|
|
&& GET_CODE (operands[1]) != HIGH && GET_CODE (operands[1]) != LO_SUM"
|
| 356 |
|
|
[(pc)]
|
| 357 |
|
|
{
|
| 358 |
|
|
emit_insn (gen_movsi_high (operands[0], operands[1]));
|
| 359 |
|
|
emit_insn (gen_movsi_lo_sum (operands[0], operands[0], operands[1]));
|
| 360 |
|
|
DONE;
|
| 361 |
|
|
}
|
| 362 |
282 |
jeremybenn |
[(set_attr "type" "move")
|
| 363 |
|
|
(set_attr "length" "2")])
|
| 364 |
|
|
|
| 365 |
|
|
|
| 366 |
|
|
;;
|
| 367 |
|
|
;; Conditional Branches & Moves
|
| 368 |
|
|
;;
|
| 369 |
|
|
|
| 370 |
|
|
(define_expand "addsicc"
|
| 371 |
|
|
[(match_operand:SI 0 "register_operand" "")
|
| 372 |
|
|
(match_operand 1 "comparison_operator" "")
|
| 373 |
|
|
(match_operand:SI 2 "register_operand" "")
|
| 374 |
|
|
(match_operand:SI 3 "register_operand" "")]
|
| 375 |
|
|
""
|
| 376 |
|
|
"FAIL;")
|
| 377 |
|
|
|
| 378 |
|
|
(define_expand "addhicc"
|
| 379 |
|
|
[(match_operand:HI 0 "register_operand" "")
|
| 380 |
|
|
(match_operand 1 "comparison_operator" "")
|
| 381 |
|
|
(match_operand:HI 2 "register_operand" "")
|
| 382 |
|
|
(match_operand:HI 3 "register_operand" "")]
|
| 383 |
|
|
""
|
| 384 |
|
|
"FAIL;")
|
| 385 |
|
|
|
| 386 |
|
|
(define_expand "addqicc"
|
| 387 |
|
|
[(match_operand:QI 0 "register_operand" "")
|
| 388 |
|
|
(match_operand 1 "comparison_operator" "")
|
| 389 |
|
|
(match_operand:QI 2 "register_operand" "")
|
| 390 |
|
|
(match_operand:QI 3 "register_operand" "")]
|
| 391 |
|
|
""
|
| 392 |
|
|
"FAIL;")
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
;;
|
| 396 |
|
|
;; conditional moves
|
| 397 |
|
|
;;
|
| 398 |
|
|
|
| 399 |
|
|
(define_expand "movsicc"
|
| 400 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 401 |
|
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
| 402 |
|
|
(match_operand:SI 2 "register_operand" "")
|
| 403 |
|
|
(match_operand:SI 3 "register_operand" "")))]
|
| 404 |
|
|
"TARGET_MASK_CMOV"
|
| 405 |
|
|
"
|
| 406 |
|
|
{
|
| 407 |
|
|
if (or32_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
| 408 |
|
|
DONE;
|
| 409 |
|
|
}")
|
| 410 |
|
|
|
| 411 |
|
|
(define_expand "movhicc"
|
| 412 |
|
|
[(set (match_operand:HI 0 "register_operand" "")
|
| 413 |
|
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
| 414 |
|
|
(match_operand:HI 2 "register_operand" "")
|
| 415 |
|
|
(match_operand:HI 3 "register_operand" "")))]
|
| 416 |
|
|
""
|
| 417 |
|
|
"
|
| 418 |
|
|
{
|
| 419 |
|
|
FAIL;
|
| 420 |
|
|
}")
|
| 421 |
|
|
|
| 422 |
|
|
(define_expand "movqicc"
|
| 423 |
|
|
[(set (match_operand:QI 0 "register_operand" "")
|
| 424 |
|
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
| 425 |
|
|
(match_operand:QI 2 "register_operand" "")
|
| 426 |
|
|
(match_operand:QI 3 "register_operand" "")))]
|
| 427 |
|
|
""
|
| 428 |
|
|
"
|
| 429 |
|
|
{
|
| 430 |
|
|
FAIL;
|
| 431 |
|
|
}")
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
;; We use the BASE_REGS for the cmov input operands because, if rA is
|
| 435 |
|
|
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
|
| 436 |
|
|
;; because we may switch the operands and rB may end up being rA.
|
| 437 |
|
|
|
| 438 |
|
|
(define_insn "cmov"
|
| 439 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 440 |
|
|
(if_then_else:SI
|
| 441 |
|
|
(match_operator 1 "comparison_operator"
|
| 442 |
|
|
[(match_operand 4 "cc_reg_operand" "")
|
| 443 |
|
|
(const_int 0)])
|
| 444 |
|
|
(match_operand:SI 2 "register_operand" "r")
|
| 445 |
|
|
(match_operand:SI 3 "register_operand" "r")))]
|
| 446 |
|
|
"TARGET_MASK_CMOV"
|
| 447 |
|
|
"*
|
| 448 |
|
|
return or32_output_cmov(operands);
|
| 449 |
|
|
")
|
| 450 |
|
|
|
| 451 |
|
|
;;
|
| 452 |
|
|
;; ....................
|
| 453 |
|
|
;;
|
| 454 |
|
|
;; COMPARISONS
|
| 455 |
|
|
;;
|
| 456 |
|
|
;; ....................
|
| 457 |
|
|
|
| 458 |
|
|
;; Flow here is rather complex:
|
| 459 |
|
|
;;
|
| 460 |
|
|
;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
|
| 461 |
|
|
;; arguments into the branch_cmp array, and the type into
|
| 462 |
|
|
;; branch_type. No RTL is generated.
|
| 463 |
|
|
;;
|
| 464 |
|
|
;; 2) The appropriate branch define_expand is called, which then
|
| 465 |
|
|
;; creates the appropriate RTL for the comparison and branch.
|
| 466 |
|
|
;; Different CC modes are used, based on what type of branch is
|
| 467 |
|
|
;; done, so that we can constrain things appropriately. There
|
| 468 |
|
|
;; are assumptions in the rest of GCC that break if we fold the
|
| 469 |
|
|
;; operands into the branches for integer operations, and use cc0
|
| 470 |
|
|
;; for floating point, so we use the fp status register instead.
|
| 471 |
|
|
;; If needed, an appropriate temporary is created to hold the
|
| 472 |
|
|
;; of the integer compare.
|
| 473 |
|
|
|
| 474 |
|
|
;; Compare insns are next. Note that the RS/6000 has two types of compares,
|
| 475 |
|
|
;; signed & unsigned, and one type of branch.
|
| 476 |
|
|
;;
|
| 477 |
|
|
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
|
| 478 |
|
|
;; insns, and branches. We store the operands of compares until we see
|
| 479 |
|
|
;; how it is used.
|
| 480 |
|
|
|
| 481 |
|
|
;; JPB 31-Aug-10: cmpxx appears to be obsolete in GCC 4.5. Needs more
|
| 482 |
|
|
;; investigation.
|
| 483 |
|
|
|
| 484 |
|
|
;;(define_expand "cmpsi"
|
| 485 |
399 |
jeremybenn |
;; [(set (reg:CC CC_REG)
|
| 486 |
282 |
jeremybenn |
;; (compare:CC (match_operand:SI 0 "register_operand" "")
|
| 487 |
|
|
;; (match_operand:SI 1 "nonmemory_operand" "")))]
|
| 488 |
|
|
;; ""
|
| 489 |
|
|
;; {
|
| 490 |
|
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
| 491 |
|
|
;; operands[0] = force_reg (SImode, operands[0]);
|
| 492 |
|
|
;; or32_compare_op0 = operands[0];
|
| 493 |
|
|
;; or32_compare_op1 = operands[1];
|
| 494 |
|
|
;; DONE;
|
| 495 |
|
|
;; })
|
| 496 |
|
|
|
| 497 |
|
|
;; (define_expand "cmpsf"
|
| 498 |
399 |
jeremybenn |
;; [(set (reg:CC CC_REG)
|
| 499 |
282 |
jeremybenn |
;; (compare:CC (match_operand:SF 0 "register_operand" "")
|
| 500 |
|
|
;; (match_operand:SF 1 "register_operand" "")))]
|
| 501 |
|
|
;; "TARGET_HARD_FLOAT"
|
| 502 |
|
|
;; {
|
| 503 |
|
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
| 504 |
|
|
;; operands[0] = force_reg (SFmode, operands[0]);
|
| 505 |
|
|
;; or32_compare_op0 = operands[0];
|
| 506 |
|
|
;; or32_compare_op1 = operands[1];
|
| 507 |
|
|
;; DONE;
|
| 508 |
|
|
;; })
|
| 509 |
|
|
|
| 510 |
|
|
(define_expand "cbranchsi4"
|
| 511 |
|
|
[(match_operator 0 "comparison_operator"
|
| 512 |
|
|
[(match_operand:SI 1 "register_operand")
|
| 513 |
|
|
(match_operand:SI 2 "nonmemory_operand")])
|
| 514 |
|
|
(match_operand 3 "")]
|
| 515 |
|
|
""
|
| 516 |
|
|
{
|
| 517 |
|
|
or32_expand_conditional_branch (operands, SImode);
|
| 518 |
|
|
DONE;
|
| 519 |
|
|
})
|
| 520 |
|
|
|
| 521 |
|
|
(define_expand "cbranchsf4"
|
| 522 |
|
|
[(match_operator 0 "comparison_operator"
|
| 523 |
|
|
[(match_operand:SI 1 "register_operand")
|
| 524 |
|
|
(match_operand:SI 2 "register_operand")])
|
| 525 |
|
|
(match_operand 3 "")]
|
| 526 |
|
|
"TARGET_HARD_FLOAT"
|
| 527 |
|
|
{
|
| 528 |
|
|
or32_expand_conditional_branch (operands, SFmode);
|
| 529 |
|
|
DONE;
|
| 530 |
|
|
})
|
| 531 |
|
|
|
| 532 |
|
|
;;
|
| 533 |
|
|
;; Setting a CCxx registers from comparision
|
| 534 |
|
|
;;
|
| 535 |
|
|
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
;; Here are the actual compare insns.
|
| 539 |
|
|
(define_insn "*cmpsi_eq"
|
| 540 |
399 |
jeremybenn |
[(set (reg:CCEQ CC_REG)
|
| 541 |
282 |
jeremybenn |
(compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
|
| 542 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 543 |
|
|
""
|
| 544 |
|
|
"@
|
| 545 |
|
|
l.sfeqi\t%0,%1
|
| 546 |
|
|
l.sfeq \t%0,%1")
|
| 547 |
|
|
|
| 548 |
|
|
(define_insn "*cmpsi_ne"
|
| 549 |
399 |
jeremybenn |
[(set (reg:CCNE CC_REG)
|
| 550 |
282 |
jeremybenn |
(compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
|
| 551 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 552 |
|
|
""
|
| 553 |
|
|
"@
|
| 554 |
|
|
l.sfnei\t%0,%1
|
| 555 |
|
|
l.sfne \t%0,%1")
|
| 556 |
|
|
|
| 557 |
|
|
(define_insn "*cmpsi_gt"
|
| 558 |
399 |
jeremybenn |
[(set (reg:CCGT CC_REG)
|
| 559 |
282 |
jeremybenn |
(compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
|
| 560 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 561 |
|
|
""
|
| 562 |
|
|
"@
|
| 563 |
|
|
l.sfgtsi\t%0,%1
|
| 564 |
|
|
l.sfgts \t%0,%1")
|
| 565 |
|
|
|
| 566 |
|
|
(define_insn "*cmpsi_gtu"
|
| 567 |
399 |
jeremybenn |
[(set (reg:CCGTU CC_REG)
|
| 568 |
282 |
jeremybenn |
(compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
|
| 569 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 570 |
|
|
""
|
| 571 |
|
|
"@
|
| 572 |
|
|
l.sfgtui\t%0,%1
|
| 573 |
|
|
l.sfgtu \t%0,%1")
|
| 574 |
|
|
|
| 575 |
|
|
(define_insn "*cmpsi_lt"
|
| 576 |
399 |
jeremybenn |
[(set (reg:CCLT CC_REG)
|
| 577 |
282 |
jeremybenn |
(compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
|
| 578 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 579 |
|
|
""
|
| 580 |
|
|
"@
|
| 581 |
|
|
l.sfltsi\t%0,%1
|
| 582 |
|
|
l.sflts \t%0,%1")
|
| 583 |
|
|
|
| 584 |
|
|
(define_insn "*cmpsi_ltu"
|
| 585 |
399 |
jeremybenn |
[(set (reg:CCLTU CC_REG)
|
| 586 |
282 |
jeremybenn |
(compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
|
| 587 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 588 |
|
|
""
|
| 589 |
|
|
"@
|
| 590 |
|
|
l.sfltui\t%0,%1
|
| 591 |
|
|
l.sfltu \t%0,%1")
|
| 592 |
|
|
|
| 593 |
|
|
(define_insn "*cmpsi_ge"
|
| 594 |
399 |
jeremybenn |
[(set (reg:CCGE CC_REG)
|
| 595 |
282 |
jeremybenn |
(compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
|
| 596 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 597 |
|
|
""
|
| 598 |
|
|
"@
|
| 599 |
|
|
l.sfgesi\t%0,%1
|
| 600 |
|
|
l.sfges \t%0,%1")
|
| 601 |
|
|
|
| 602 |
|
|
|
| 603 |
|
|
(define_insn "*cmpsi_geu"
|
| 604 |
399 |
jeremybenn |
[(set (reg:CCGEU CC_REG)
|
| 605 |
282 |
jeremybenn |
(compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
|
| 606 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 607 |
|
|
""
|
| 608 |
|
|
"@
|
| 609 |
|
|
l.sfgeui\t%0,%1
|
| 610 |
|
|
l.sfgeu \t%0,%1")
|
| 611 |
|
|
|
| 612 |
|
|
|
| 613 |
|
|
(define_insn "*cmpsi_le"
|
| 614 |
399 |
jeremybenn |
[(set (reg:CCLE CC_REG)
|
| 615 |
282 |
jeremybenn |
(compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
|
| 616 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 617 |
|
|
""
|
| 618 |
|
|
"@
|
| 619 |
|
|
l.sflesi\t%0,%1
|
| 620 |
|
|
l.sfles \t%0,%1")
|
| 621 |
|
|
|
| 622 |
|
|
(define_insn "*cmpsi_leu"
|
| 623 |
399 |
jeremybenn |
[(set (reg:CCLEU CC_REG)
|
| 624 |
282 |
jeremybenn |
(compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
|
| 625 |
|
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
| 626 |
|
|
""
|
| 627 |
|
|
"@
|
| 628 |
|
|
l.sfleui\t%0,%1
|
| 629 |
|
|
l.sfleu \t%0,%1")
|
| 630 |
|
|
|
| 631 |
|
|
;; Single precision floating point evaluation instructions
|
| 632 |
|
|
(define_insn "*cmpsf_eq"
|
| 633 |
399 |
jeremybenn |
[(set (reg:CCEQ CC_REG)
|
| 634 |
282 |
jeremybenn |
(compare:CCEQ (match_operand:SF 0 "register_operand" "r,r")
|
| 635 |
|
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
| 636 |
|
|
"TARGET_HARD_FLOAT"
|
| 637 |
|
|
"lf.sfeq.s\t%0,%1")
|
| 638 |
|
|
|
| 639 |
|
|
(define_insn "*cmpsf_ne"
|
| 640 |
399 |
jeremybenn |
[(set (reg:CCNE CC_REG)
|
| 641 |
282 |
jeremybenn |
(compare:CCNE (match_operand:SF 0 "register_operand" "r,r")
|
| 642 |
|
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
| 643 |
|
|
"TARGET_HARD_FLOAT"
|
| 644 |
|
|
"lf.sfne.s\t%0,%1")
|
| 645 |
|
|
|
| 646 |
|
|
|
| 647 |
|
|
(define_insn "*cmpsf_gt"
|
| 648 |
399 |
jeremybenn |
[(set (reg:CCGT CC_REG)
|
| 649 |
282 |
jeremybenn |
(compare:CCGT (match_operand:SF 0 "register_operand" "r,r")
|
| 650 |
|
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
| 651 |
|
|
"TARGET_HARD_FLOAT"
|
| 652 |
|
|
"lf.sfgt.s\t%0,%1")
|
| 653 |
|
|
|
| 654 |
|
|
(define_insn "*cmpsf_ge"
|
| 655 |
399 |
jeremybenn |
[(set (reg:CCGE CC_REG)
|
| 656 |
282 |
jeremybenn |
(compare:CCGE (match_operand:SF 0 "register_operand" "r,r")
|
| 657 |
|
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
| 658 |
|
|
"TARGET_HARD_FLOAT"
|
| 659 |
|
|
"lf.sfge.s\t%0,%1")
|
| 660 |
|
|
|
| 661 |
|
|
|
| 662 |
|
|
(define_insn "*cmpsf_lt"
|
| 663 |
399 |
jeremybenn |
[(set (reg:CCLT CC_REG)
|
| 664 |
282 |
jeremybenn |
(compare:CCLT (match_operand:SF 0 "register_operand" "r,r")
|
| 665 |
|
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
| 666 |
|
|
"TARGET_HARD_FLOAT"
|
| 667 |
|
|
"lf.sflt.s\t%0,%1")
|
| 668 |
|
|
|
| 669 |
|
|
(define_insn "*cmpsf_le"
|
| 670 |
399 |
jeremybenn |
[(set (reg:CCLE CC_REG)
|
| 671 |
282 |
jeremybenn |
(compare:CCLE (match_operand:SF 0 "register_operand" "r,r")
|
| 672 |
|
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
| 673 |
|
|
"TARGET_HARD_FLOAT"
|
| 674 |
|
|
"lf.sfle.s\t%0,%1")
|
| 675 |
|
|
|
| 676 |
|
|
(define_insn "*bf"
|
| 677 |
|
|
[(set (pc)
|
| 678 |
|
|
(if_then_else (match_operator 1 "comparison_operator"
|
| 679 |
|
|
[(match_operand 2
|
| 680 |
|
|
"cc_reg_operand" "")
|
| 681 |
|
|
(const_int 0)])
|
| 682 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 683 |
|
|
(pc)))]
|
| 684 |
|
|
""
|
| 685 |
|
|
"*
|
| 686 |
|
|
return or32_output_bf(operands);
|
| 687 |
|
|
"
|
| 688 |
|
|
[(set_attr "type" "branch")
|
| 689 |
|
|
(set_attr "length" "1")])
|
| 690 |
|
|
|
| 691 |
|
|
;;
|
| 692 |
|
|
;;
|
| 693 |
|
|
;;
|
| 694 |
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
| 695 |
|
|
;;
|
| 696 |
|
|
;;
|
| 697 |
|
|
(define_insn "movdi"
|
| 698 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m, r")
|
| 699 |
|
|
(match_operand:DI 1 "general_operand" " r, m, r, i"))]
|
| 700 |
|
|
""
|
| 701 |
|
|
"*
|
| 702 |
|
|
return or32_output_move_double (operands);
|
| 703 |
|
|
"
|
| 704 |
|
|
[(set_attr "length" "2,2,2,3")])
|
| 705 |
|
|
|
| 706 |
|
|
;; Moving double and single precision floating point values
|
| 707 |
|
|
|
| 708 |
|
|
(define_insn "movdf"
|
| 709 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r, r, m, r")
|
| 710 |
|
|
(match_operand:DF 1 "general_operand" " r, m, r, i"))]
|
| 711 |
|
|
""
|
| 712 |
|
|
"*
|
| 713 |
|
|
return or32_output_move_double (operands);
|
| 714 |
|
|
"
|
| 715 |
|
|
[(set_attr "length" "2,2,2,3")])
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
(define_insn "movsf"
|
| 719 |
|
|
[(set (match_operand:SF 0 "general_operand" "=r,r,m")
|
| 720 |
|
|
(match_operand:SF 1 "general_operand" "r,m,r"))]
|
| 721 |
|
|
""
|
| 722 |
|
|
"@
|
| 723 |
|
|
l.ori \t%0,%1,0\t # movsf
|
| 724 |
|
|
l.lwz \t%0,%1\t # movsf
|
| 725 |
|
|
l.sw \t%0,%1\t # movsf"
|
| 726 |
|
|
[(set_attr "type" "move,load,store")
|
| 727 |
|
|
(set_attr "length" "1,1,1")])
|
| 728 |
|
|
|
| 729 |
|
|
|
| 730 |
|
|
;;
|
| 731 |
|
|
;; extendqisi2
|
| 732 |
|
|
;;
|
| 733 |
|
|
|
| 734 |
|
|
(define_expand "extendqisi2"
|
| 735 |
|
|
[(use (match_operand:SI 0 "register_operand" ""))
|
| 736 |
|
|
(use (match_operand:QI 1 "nonimmediate_operand" ""))]
|
| 737 |
|
|
""
|
| 738 |
|
|
"
|
| 739 |
|
|
{
|
| 740 |
|
|
if (TARGET_MASK_SEXT)
|
| 741 |
|
|
emit_insn (gen_extendqisi2_sext(operands[0], operands[1]));
|
| 742 |
|
|
else {
|
| 743 |
|
|
if ( GET_CODE(operands[1]) == MEM ) {
|
| 744 |
|
|
emit_insn (gen_extendqisi2_no_sext_mem(operands[0], operands[1]));
|
| 745 |
|
|
}
|
| 746 |
|
|
else {
|
| 747 |
|
|
emit_insn (gen_extendqisi2_no_sext_reg(operands[0], operands[1]));
|
| 748 |
|
|
}
|
| 749 |
|
|
}
|
| 750 |
|
|
DONE;
|
| 751 |
|
|
}")
|
| 752 |
|
|
|
| 753 |
|
|
(define_insn "extendqisi2_sext"
|
| 754 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 755 |
|
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
| 756 |
|
|
"TARGET_MASK_SEXT"
|
| 757 |
|
|
"@
|
| 758 |
|
|
l.extbs \t%0,%1\t # extendqisi2_has_signed_extend
|
| 759 |
|
|
l.lbs \t%0,%1\t # extendqisi2_has_signed_extend"
|
| 760 |
|
|
[(set_attr "length" "1,1")
|
| 761 |
|
|
(set_attr "type" "extend,load")])
|
| 762 |
|
|
|
| 763 |
|
|
(define_insn "extendqisi2_no_sext_mem"
|
| 764 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 765 |
|
|
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
|
| 766 |
|
|
"!TARGET_MASK_SEXT"
|
| 767 |
|
|
"l.lbs \t%0,%1\t # extendqisi2_no_sext_mem"
|
| 768 |
|
|
[(set_attr "length" "1")
|
| 769 |
|
|
(set_attr "type" "load")])
|
| 770 |
|
|
|
| 771 |
|
|
(define_expand "extendqisi2_no_sext_reg"
|
| 772 |
|
|
[(set (match_dup 2)
|
| 773 |
|
|
(ashift:SI (match_operand:QI 1 "register_operand" "")
|
| 774 |
|
|
(const_int 24)))
|
| 775 |
|
|
(set (match_operand:SI 0 "register_operand" "")
|
| 776 |
|
|
(ashiftrt:SI (match_dup 2)
|
| 777 |
|
|
(const_int 24)))]
|
| 778 |
|
|
"!TARGET_MASK_SEXT"
|
| 779 |
|
|
"
|
| 780 |
|
|
{
|
| 781 |
|
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
| 782 |
|
|
operands[2] = gen_reg_rtx (SImode); }")
|
| 783 |
|
|
|
| 784 |
|
|
;;
|
| 785 |
|
|
;; extendhisi2
|
| 786 |
|
|
;;
|
| 787 |
|
|
|
| 788 |
|
|
(define_expand "extendhisi2"
|
| 789 |
|
|
[(use (match_operand:SI 0 "register_operand" ""))
|
| 790 |
|
|
(use (match_operand:HI 1 "nonimmediate_operand" ""))]
|
| 791 |
|
|
""
|
| 792 |
|
|
"
|
| 793 |
|
|
{
|
| 794 |
|
|
if (TARGET_MASK_SEXT)
|
| 795 |
|
|
emit_insn (gen_extendhisi2_sext(operands[0], operands[1]));
|
| 796 |
|
|
else {
|
| 797 |
|
|
if ( GET_CODE(operands[1]) == MEM ) {
|
| 798 |
|
|
emit_insn (gen_extendhisi2_no_sext_mem(operands[0], operands[1]));
|
| 799 |
|
|
}
|
| 800 |
|
|
else {
|
| 801 |
|
|
emit_insn (gen_extendhisi2_no_sext_reg(operands[0], operands[1]));
|
| 802 |
|
|
}
|
| 803 |
|
|
}
|
| 804 |
|
|
DONE;
|
| 805 |
|
|
}")
|
| 806 |
|
|
|
| 807 |
|
|
(define_insn "extendhisi2_sext"
|
| 808 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 809 |
|
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
| 810 |
|
|
"TARGET_MASK_SEXT"
|
| 811 |
|
|
"@
|
| 812 |
|
|
l.exths \t%0,%1\t # extendhisi2_has_signed_extend
|
| 813 |
|
|
l.lhs \t%0,%1\t # extendhisi2_has_signed_extend"
|
| 814 |
|
|
[(set_attr "length" "1,1")
|
| 815 |
|
|
(set_attr "type" "extend,load")])
|
| 816 |
|
|
|
| 817 |
|
|
(define_insn "extendhisi2_no_sext_mem"
|
| 818 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 819 |
|
|
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
|
| 820 |
|
|
"!TARGET_MASK_SEXT"
|
| 821 |
|
|
"l.lhs \t%0,%1\t # extendhisi2_no_sext_mem"
|
| 822 |
|
|
[(set_attr "length" "1")
|
| 823 |
|
|
(set_attr "type" "load")])
|
| 824 |
|
|
|
| 825 |
|
|
(define_expand "extendhisi2_no_sext_reg"
|
| 826 |
|
|
[(set (match_dup 2)
|
| 827 |
|
|
(ashift:SI (match_operand:HI 1 "register_operand" "")
|
| 828 |
|
|
(const_int 16)))
|
| 829 |
|
|
(set (match_operand:SI 0 "register_operand" "")
|
| 830 |
|
|
(ashiftrt:SI (match_dup 2)
|
| 831 |
|
|
(const_int 16)))]
|
| 832 |
|
|
"!TARGET_MASK_SEXT"
|
| 833 |
|
|
"
|
| 834 |
|
|
{
|
| 835 |
|
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
| 836 |
|
|
operands[2] = gen_reg_rtx (SImode); }")
|
| 837 |
|
|
|
| 838 |
|
|
|
| 839 |
|
|
;;
|
| 840 |
|
|
;; zero_extend2
|
| 841 |
|
|
;;
|
| 842 |
|
|
|
| 843 |
|
|
(define_insn "zero_extendqisi2"
|
| 844 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 845 |
|
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
| 846 |
|
|
""
|
| 847 |
|
|
"@
|
| 848 |
|
|
l.andi \t%0,%1,0xff\t # zero_extendqisi2
|
| 849 |
|
|
l.lbz \t%0,%1\t # zero_extendqisi2"
|
| 850 |
|
|
[(set_attr "type" "logic,load")
|
| 851 |
|
|
(set_attr "length" "1,1")])
|
| 852 |
|
|
|
| 853 |
|
|
|
| 854 |
|
|
(define_insn "zero_extendhisi2"
|
| 855 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 856 |
|
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
| 857 |
|
|
""
|
| 858 |
|
|
"@
|
| 859 |
|
|
l.andi \t%0,%1,0xffff\t # zero_extendqisi2
|
| 860 |
|
|
l.lhz \t%0,%1\t # zero_extendqisi2"
|
| 861 |
|
|
[(set_attr "type" "logic,load")
|
| 862 |
|
|
(set_attr "length" "1,1")])
|
| 863 |
|
|
|
| 864 |
|
|
;;
|
| 865 |
|
|
;; Shift/rotate operations
|
| 866 |
|
|
;;
|
| 867 |
|
|
|
| 868 |
|
|
(define_insn "ashlsi3"
|
| 869 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 870 |
|
|
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
|
| 871 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
| 872 |
|
|
""
|
| 873 |
|
|
"@
|
| 874 |
|
|
l.sll \t%0,%1,%2
|
| 875 |
|
|
l.slli \t%0,%1,%2"
|
| 876 |
|
|
[(set_attr "type" "shift,shift")
|
| 877 |
|
|
(set_attr "length" "1,1")])
|
| 878 |
|
|
|
| 879 |
|
|
(define_insn "ashrsi3"
|
| 880 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 881 |
|
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
| 882 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
| 883 |
|
|
""
|
| 884 |
|
|
"@
|
| 885 |
|
|
l.sra \t%0,%1,%2
|
| 886 |
|
|
l.srai \t%0,%1,%2"
|
| 887 |
|
|
[(set_attr "type" "shift,shift")
|
| 888 |
|
|
(set_attr "length" "1,1")])
|
| 889 |
|
|
|
| 890 |
|
|
(define_insn "lshrsi3"
|
| 891 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 892 |
|
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
| 893 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
| 894 |
|
|
""
|
| 895 |
|
|
"@
|
| 896 |
|
|
l.srl \t%0,%1,%2
|
| 897 |
|
|
l.srli \t%0,%1,%2"
|
| 898 |
|
|
[(set_attr "type" "shift,shift")
|
| 899 |
|
|
(set_attr "length" "1,1")])
|
| 900 |
|
|
|
| 901 |
|
|
(define_insn "rotrsi3"
|
| 902 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 903 |
|
|
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
|
| 904 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
| 905 |
|
|
"TARGET_MASK_ROR"
|
| 906 |
|
|
"@
|
| 907 |
|
|
l.ror \t%0,%1,%2
|
| 908 |
|
|
l.rori \t%0,%1,%2"
|
| 909 |
|
|
[(set_attr "type" "shift,shift")
|
| 910 |
|
|
(set_attr "length" "1,1")])
|
| 911 |
|
|
|
| 912 |
|
|
;;
|
| 913 |
|
|
;; Logical bitwise operations
|
| 914 |
|
|
;;
|
| 915 |
|
|
|
| 916 |
|
|
(define_insn "andsi3"
|
| 917 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 918 |
|
|
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
|
| 919 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
| 920 |
|
|
""
|
| 921 |
|
|
"@
|
| 922 |
|
|
l.and \t%0,%1,%2
|
| 923 |
|
|
l.andi \t%0,%1,%2"
|
| 924 |
|
|
[(set_attr "type" "logic,logic")
|
| 925 |
|
|
(set_attr "length" "1,1")])
|
| 926 |
|
|
|
| 927 |
|
|
(define_insn "iorsi3"
|
| 928 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 929 |
|
|
(ior:SI (match_operand:SI 1 "register_operand" "%r,r")
|
| 930 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
| 931 |
|
|
""
|
| 932 |
|
|
"@
|
| 933 |
|
|
l.or \t%0,%1,%2
|
| 934 |
|
|
l.ori \t%0,%1,%2"
|
| 935 |
|
|
[(set_attr "type" "logic,logic")
|
| 936 |
|
|
(set_attr "length" "1,1")])
|
| 937 |
|
|
|
| 938 |
|
|
(define_insn "xorsi3"
|
| 939 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 940 |
|
|
(xor:SI (match_operand:SI 1 "register_operand" "%r,r")
|
| 941 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
| 942 |
|
|
""
|
| 943 |
|
|
"@
|
| 944 |
|
|
l.xor \t%0,%1,%2
|
| 945 |
|
|
l.xori \t%0,%1,%2"
|
| 946 |
|
|
[(set_attr "type" "logic,logic")
|
| 947 |
|
|
(set_attr "length" "1,1")])
|
| 948 |
|
|
|
| 949 |
|
|
(define_insn "one_cmplqi2"
|
| 950 |
|
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
| 951 |
|
|
(not:QI (match_operand:QI 1 "register_operand" "r")))]
|
| 952 |
|
|
""
|
| 953 |
|
|
"l.xori \t%0,%1,0x00ff"
|
| 954 |
|
|
[(set_attr "type" "logic")
|
| 955 |
|
|
(set_attr "length" "1")])
|
| 956 |
|
|
|
| 957 |
|
|
(define_insn "one_cmplsi2"
|
| 958 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 959 |
|
|
(not:SI (match_operand:SI 1 "register_operand" "r")))]
|
| 960 |
|
|
""
|
| 961 |
|
|
"l.xori \t%0,%1,0xffff"
|
| 962 |
|
|
[(set_attr "type" "logic")
|
| 963 |
|
|
(set_attr "length" "1")])
|
| 964 |
|
|
|
| 965 |
|
|
;;
|
| 966 |
|
|
;; Arithmetic operations
|
| 967 |
|
|
;;
|
| 968 |
|
|
|
| 969 |
|
|
(define_insn "negsi2"
|
| 970 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 971 |
|
|
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
|
| 972 |
|
|
""
|
| 973 |
|
|
"l.sub \t%0,r0,%1"
|
| 974 |
|
|
[(set_attr "type" "add")
|
| 975 |
|
|
(set_attr "length" "1")])
|
| 976 |
|
|
|
| 977 |
|
|
(define_insn "addsi3"
|
| 978 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 979 |
|
|
(plus:SI (match_operand:SI 1 "register_operand" "%r,r")
|
| 980 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
| 981 |
|
|
""
|
| 982 |
|
|
"@
|
| 983 |
|
|
l.add \t%0,%1,%2
|
| 984 |
|
|
l.addi \t%0,%1,%2"
|
| 985 |
|
|
[(set_attr "type" "add,add")
|
| 986 |
|
|
(set_attr "length" "1,1")])
|
| 987 |
|
|
|
| 988 |
|
|
(define_insn "subsi3"
|
| 989 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
| 990 |
|
|
(minus:SI (match_operand:SI 1 "register_operand" "r,r")
|
| 991 |
|
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
| 992 |
|
|
""
|
| 993 |
|
|
"@
|
| 994 |
|
|
l.sub \t%0,%1,%2
|
| 995 |
|
|
l.addi \t%0,%1,%n2"
|
| 996 |
|
|
[(set_attr "type" "add,add")]
|
| 997 |
|
|
)
|
| 998 |
|
|
|
| 999 |
|
|
;;
|
| 1000 |
|
|
;; mul and div
|
| 1001 |
|
|
;;
|
| 1002 |
|
|
|
| 1003 |
|
|
(define_insn "mulsi3"
|
| 1004 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 1005 |
|
|
(mult:SI (match_operand:SI 1 "register_operand" "r")
|
| 1006 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
| 1007 |
|
|
"TARGET_HARD_MUL"
|
| 1008 |
|
|
"l.mul \t%0,%1,%2"
|
| 1009 |
|
|
[(set_attr "type" "mul")
|
| 1010 |
|
|
(set_attr "length" "1")])
|
| 1011 |
|
|
|
| 1012 |
|
|
(define_insn "divsi3"
|
| 1013 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 1014 |
|
|
(div:SI (match_operand:SI 1 "register_operand" "r")
|
| 1015 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
| 1016 |
|
|
"TARGET_HARD_DIV"
|
| 1017 |
|
|
"l.div \t%0,%1,%2"
|
| 1018 |
|
|
[(set_attr "type" "mul")
|
| 1019 |
|
|
(set_attr "length" "1")])
|
| 1020 |
|
|
|
| 1021 |
|
|
(define_insn "udivsi3"
|
| 1022 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 1023 |
|
|
(udiv:SI (match_operand:SI 1 "register_operand" "r")
|
| 1024 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
| 1025 |
|
|
"TARGET_HARD_DIV"
|
| 1026 |
|
|
"l.divu \t%0,%1,%2"
|
| 1027 |
|
|
[(set_attr "type" "mul")
|
| 1028 |
|
|
(set_attr "length" "1")])
|
| 1029 |
|
|
|
| 1030 |
|
|
;;
|
| 1031 |
|
|
;; jumps
|
| 1032 |
|
|
;;
|
| 1033 |
|
|
|
| 1034 |
|
|
;; jump
|
| 1035 |
|
|
|
| 1036 |
|
|
(define_expand "jump"
|
| 1037 |
|
|
[(set (pc)
|
| 1038 |
|
|
(label_ref (match_operand 0 "" "")))]
|
| 1039 |
|
|
""
|
| 1040 |
|
|
"
|
| 1041 |
|
|
{
|
| 1042 |
399 |
jeremybenn |
emit_jump_insn (gen_jump_internal (operands[0]));
|
| 1043 |
282 |
jeremybenn |
DONE;
|
| 1044 |
|
|
}")
|
| 1045 |
|
|
|
| 1046 |
|
|
(define_insn "jump_internal"
|
| 1047 |
|
|
[(set (pc)
|
| 1048 |
|
|
(label_ref (match_operand 0 "" "")))]
|
| 1049 |
399 |
jeremybenn |
""
|
| 1050 |
282 |
jeremybenn |
"l.j \t%l0%("
|
| 1051 |
|
|
[(set_attr "type" "jump")
|
| 1052 |
|
|
(set_attr "length" "1")])
|
| 1053 |
|
|
|
| 1054 |
|
|
;; indirect jump
|
| 1055 |
|
|
|
| 1056 |
|
|
(define_expand "indirect_jump"
|
| 1057 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
| 1058 |
|
|
""
|
| 1059 |
|
|
"
|
| 1060 |
|
|
{
|
| 1061 |
399 |
jeremybenn |
emit_jump_insn (gen_indirect_jump_internal (operands[0]));
|
| 1062 |
282 |
jeremybenn |
DONE;
|
| 1063 |
|
|
|
| 1064 |
|
|
}")
|
| 1065 |
|
|
|
| 1066 |
|
|
(define_insn "indirect_jump_internal"
|
| 1067 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
| 1068 |
399 |
jeremybenn |
""
|
| 1069 |
282 |
jeremybenn |
"l.jr \t%0%("
|
| 1070 |
|
|
[(set_attr "type" "jump")
|
| 1071 |
|
|
(set_attr "length" "1")])
|
| 1072 |
|
|
|
| 1073 |
|
|
;;
|
| 1074 |
|
|
;; calls
|
| 1075 |
|
|
;;
|
| 1076 |
|
|
|
| 1077 |
|
|
;; call
|
| 1078 |
|
|
|
| 1079 |
|
|
(define_expand "call"
|
| 1080 |
|
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
| 1081 |
|
|
(match_operand 1 "" "i"))
|
| 1082 |
|
|
(clobber (reg:SI 9))])]
|
| 1083 |
|
|
""
|
| 1084 |
|
|
"
|
| 1085 |
|
|
{
|
| 1086 |
399 |
jeremybenn |
emit_call_insn (gen_call_internal (operands[0], operands[1]));
|
| 1087 |
282 |
jeremybenn |
DONE;
|
| 1088 |
|
|
}")
|
| 1089 |
|
|
|
| 1090 |
|
|
(define_insn "call_internal"
|
| 1091 |
|
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
| 1092 |
|
|
(match_operand 1 "" "i"))
|
| 1093 |
|
|
(clobber (reg:SI 9))])]
|
| 1094 |
399 |
jeremybenn |
""
|
| 1095 |
282 |
jeremybenn |
"l.jal \t%S0%("
|
| 1096 |
|
|
[(set_attr "type" "jump")
|
| 1097 |
|
|
(set_attr "length" "1")])
|
| 1098 |
|
|
|
| 1099 |
|
|
;; call value
|
| 1100 |
|
|
|
| 1101 |
|
|
(define_expand "call_value"
|
| 1102 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
| 1103 |
|
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
| 1104 |
|
|
(match_operand 2 "" "i")))
|
| 1105 |
|
|
(clobber (reg:SI 9))])]
|
| 1106 |
|
|
""
|
| 1107 |
|
|
"
|
| 1108 |
|
|
{
|
| 1109 |
399 |
jeremybenn |
emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
|
| 1110 |
282 |
jeremybenn |
DONE;
|
| 1111 |
|
|
}")
|
| 1112 |
|
|
|
| 1113 |
|
|
(define_insn "call_value_internal"
|
| 1114 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
| 1115 |
|
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
| 1116 |
|
|
(match_operand 2 "" "i")))
|
| 1117 |
|
|
(clobber (reg:SI 9))])]
|
| 1118 |
399 |
jeremybenn |
""
|
| 1119 |
282 |
jeremybenn |
"l.jal \t%S1%("
|
| 1120 |
|
|
[(set_attr "type" "jump")
|
| 1121 |
|
|
(set_attr "length" "1")])
|
| 1122 |
|
|
|
| 1123 |
|
|
;; indirect call value
|
| 1124 |
|
|
|
| 1125 |
|
|
(define_expand "call_value_indirect"
|
| 1126 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
| 1127 |
|
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
| 1128 |
|
|
(match_operand 2 "" "i")))
|
| 1129 |
|
|
(clobber (reg:SI 9))])]
|
| 1130 |
|
|
""
|
| 1131 |
|
|
"
|
| 1132 |
|
|
{
|
| 1133 |
399 |
jeremybenn |
emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
|
| 1134 |
282 |
jeremybenn |
DONE;
|
| 1135 |
|
|
}")
|
| 1136 |
|
|
|
| 1137 |
|
|
(define_insn "call_value_indirect_internal"
|
| 1138 |
|
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
| 1139 |
|
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
| 1140 |
|
|
(match_operand 2 "" "i")))
|
| 1141 |
|
|
(clobber (reg:SI 9))])]
|
| 1142 |
399 |
jeremybenn |
""
|
| 1143 |
282 |
jeremybenn |
"l.jalr \t%1%("
|
| 1144 |
|
|
[(set_attr "type" "jump")
|
| 1145 |
|
|
(set_attr "length" "1")])
|
| 1146 |
|
|
|
| 1147 |
|
|
;; indirect call
|
| 1148 |
|
|
|
| 1149 |
|
|
(define_expand "call_indirect"
|
| 1150 |
|
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
| 1151 |
|
|
(match_operand 1 "" "i"))
|
| 1152 |
|
|
(clobber (reg:SI 9))])]
|
| 1153 |
|
|
""
|
| 1154 |
|
|
"
|
| 1155 |
|
|
{
|
| 1156 |
399 |
jeremybenn |
emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
|
| 1157 |
282 |
jeremybenn |
DONE;
|
| 1158 |
|
|
}")
|
| 1159 |
|
|
|
| 1160 |
|
|
(define_insn "call_indirect_internal"
|
| 1161 |
|
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
| 1162 |
|
|
(match_operand 1 "" "i"))
|
| 1163 |
|
|
(clobber (reg:SI 9))])]
|
| 1164 |
399 |
jeremybenn |
""
|
| 1165 |
282 |
jeremybenn |
"l.jalr \t%0%("
|
| 1166 |
|
|
[(set_attr "type" "jump")
|
| 1167 |
|
|
(set_attr "length" "1")])
|
| 1168 |
|
|
|
| 1169 |
|
|
;; table jump
|
| 1170 |
|
|
|
| 1171 |
|
|
(define_expand "tablejump"
|
| 1172 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
| 1173 |
|
|
(use (label_ref (match_operand 1 "" "")))]
|
| 1174 |
|
|
""
|
| 1175 |
|
|
"
|
| 1176 |
|
|
{
|
| 1177 |
399 |
jeremybenn |
if (CASE_VECTOR_PC_RELATIVE || flag_pic)
|
| 1178 |
|
|
operands[0]
|
| 1179 |
|
|
= force_reg (Pmode,
|
| 1180 |
|
|
gen_rtx_PLUS (Pmode, operands[0],
|
| 1181 |
|
|
gen_rtx_LABEL_REF (Pmode, operands[1])));
|
| 1182 |
|
|
emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
|
| 1183 |
282 |
jeremybenn |
DONE;
|
| 1184 |
|
|
}")
|
| 1185 |
|
|
|
| 1186 |
|
|
(define_insn "tablejump_internal"
|
| 1187 |
|
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
| 1188 |
|
|
(use (label_ref (match_operand 1 "" "")))]
|
| 1189 |
399 |
jeremybenn |
""
|
| 1190 |
282 |
jeremybenn |
"l.jr \t%0%("
|
| 1191 |
|
|
[(set_attr "type" "jump")
|
| 1192 |
|
|
(set_attr "length" "1")])
|
| 1193 |
|
|
|
| 1194 |
|
|
|
| 1195 |
|
|
;; no-op
|
| 1196 |
|
|
|
| 1197 |
|
|
(define_insn "nop"
|
| 1198 |
|
|
[(const_int 0)]
|
| 1199 |
|
|
""
|
| 1200 |
|
|
"l.nop"
|
| 1201 |
|
|
[(set_attr "type" "logic")
|
| 1202 |
|
|
(set_attr "length" "1")])
|
| 1203 |
|
|
|
| 1204 |
|
|
;;
|
| 1205 |
|
|
;; floating point
|
| 1206 |
|
|
;;
|
| 1207 |
|
|
|
| 1208 |
|
|
;; floating point arithmetic
|
| 1209 |
|
|
|
| 1210 |
|
|
(define_insn "addsf3"
|
| 1211 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
| 1212 |
|
|
(plus:SF (match_operand:SF 1 "register_operand" "r")
|
| 1213 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
| 1214 |
|
|
"TARGET_HARD_FLOAT"
|
| 1215 |
|
|
"lf.add.s\t%0,%1,%2"
|
| 1216 |
|
|
[(set_attr "type" "fp")
|
| 1217 |
|
|
(set_attr "length" "1")])
|
| 1218 |
|
|
|
| 1219 |
|
|
(define_insn "adddf3"
|
| 1220 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
| 1221 |
|
|
(plus:DF (match_operand:DF 1 "register_operand" "r")
|
| 1222 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
| 1223 |
|
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
| 1224 |
|
|
"lf.add.d\t%0,%1,%2"
|
| 1225 |
|
|
[(set_attr "type" "fp")
|
| 1226 |
|
|
(set_attr "length" "1")])
|
| 1227 |
|
|
|
| 1228 |
|
|
(define_insn "subsf3"
|
| 1229 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
| 1230 |
|
|
(minus:SF (match_operand:SF 1 "register_operand" "r")
|
| 1231 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
| 1232 |
|
|
"TARGET_HARD_FLOAT"
|
| 1233 |
|
|
"lf.sub.s\t%0,%1,%2"
|
| 1234 |
|
|
[(set_attr "type" "fp")
|
| 1235 |
|
|
(set_attr "length" "1")])
|
| 1236 |
|
|
|
| 1237 |
|
|
(define_insn "subdf3"
|
| 1238 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
| 1239 |
|
|
(minus:DF (match_operand:DF 1 "register_operand" "r")
|
| 1240 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
| 1241 |
|
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
| 1242 |
|
|
"lf.sub.d\t%0,%1,%2"
|
| 1243 |
|
|
[(set_attr "type" "fp")
|
| 1244 |
|
|
(set_attr "length" "1")])
|
| 1245 |
|
|
|
| 1246 |
|
|
(define_insn "mulsf3"
|
| 1247 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
| 1248 |
|
|
(mult:SF (match_operand:SF 1 "register_operand" "r")
|
| 1249 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
| 1250 |
|
|
"TARGET_HARD_FLOAT"
|
| 1251 |
|
|
"lf.mul.s\t%0,%1,%2"
|
| 1252 |
|
|
[(set_attr "type" "fp")
|
| 1253 |
|
|
(set_attr "length" "1")])
|
| 1254 |
|
|
|
| 1255 |
|
|
(define_insn "muldf3"
|
| 1256 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
| 1257 |
|
|
(mult:DF (match_operand:DF 1 "register_operand" "r")
|
| 1258 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
| 1259 |
|
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
| 1260 |
|
|
"lf.mul.d\t%0,%1,%2"
|
| 1261 |
|
|
[(set_attr "type" "fp")
|
| 1262 |
|
|
(set_attr "length" "1")])
|
| 1263 |
|
|
|
| 1264 |
|
|
(define_insn "divsf3"
|
| 1265 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
| 1266 |
|
|
(div:SF (match_operand:SF 1 "register_operand" "r")
|
| 1267 |
|
|
(match_operand:SF 2 "register_operand" "r")))]
|
| 1268 |
|
|
"TARGET_HARD_FLOAT"
|
| 1269 |
|
|
"lf.div.s\t%0,%1,%2"
|
| 1270 |
|
|
[(set_attr "type" "fp")
|
| 1271 |
|
|
(set_attr "length" "1")])
|
| 1272 |
|
|
|
| 1273 |
|
|
(define_insn "divdf3"
|
| 1274 |
|
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
| 1275 |
|
|
(div:DF (match_operand:DF 1 "register_operand" "r")
|
| 1276 |
|
|
(match_operand:DF 2 "register_operand" "r")))]
|
| 1277 |
|
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
| 1278 |
|
|
"lf.div.d\t%0,%1,%2"
|
| 1279 |
|
|
[(set_attr "type" "fp")
|
| 1280 |
|
|
(set_attr "length" "1")])
|
| 1281 |
|
|
|
| 1282 |
|
|
;; Conversion between fixed point and floating point.
|
| 1283 |
|
|
|
| 1284 |
|
|
|
| 1285 |
|
|
(define_insn "floatsisf2"
|
| 1286 |
|
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
| 1287 |
|
|
(float:SF (match_operand:SI 1 "register_operand" "r")))]
|
| 1288 |
|
|
"TARGET_HARD_FLOAT"
|
| 1289 |
|
|
"lf.itof.s\t%0, %1"
|
| 1290 |
|
|
[(set_attr "type" "fp")
|
| 1291 |
|
|
(set_attr "length" "1")])
|
| 1292 |
|
|
|
| 1293 |
|
|
;; not working
|
| 1294 |
|
|
(define_insn "fixunssfsi2"
|
| 1295 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
| 1296 |
|
|
(fix:SI (match_operand:SF 1 "register_operand" "r")))]
|
| 1297 |
|
|
"TARGET_HARD_FLOAT"
|
| 1298 |
|
|
"lf.ftoi.s\t%0, %1"
|
| 1299 |
|
|
[(set_attr "type" "fp")
|
| 1300 |
|
|
(set_attr "length" "1")])
|
| 1301 |
|
|
|
| 1302 |
|
|
|
| 1303 |
|
|
;; Local variables:
|
| 1304 |
|
|
;; mode:emacs-lisp
|
| 1305 |
|
|
;; comment-start: ";; "
|
| 1306 |
|
|
;; eval: (set-syntax-table (copy-sequence (syntax-table)))
|
| 1307 |
|
|
;; eval: (modify-syntax-entry ?[ "(]")
|
| 1308 |
|
|
;; eval: (modify-syntax-entry ?] ")[")
|
| 1309 |
|
|
;; eval: (modify-syntax-entry ?{ "(}")
|
| 1310 |
|
|
;; eval: (modify-syntax-entry ?} "){")
|
| 1311 |
|
|
;; eval: (setq indent-tabs-mode t)
|
| 1312 |
|
|
;; End:
|
