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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [pa/] [constraints.md] - Blame information for rev 282

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1 282 jeremybenn
;; Constraint definitions for pa
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;;; Unused letters:
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;;;    ABCDEF H             V  Y
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;;;     bcde ghijklmnop  stuvw  z
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;; Register constraints.
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(define_register_constraint "a" "R1_REGS"
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  "General register 1.")
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(define_register_constraint "f" "FP_REGS"
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  "Floating-point register.")
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(define_register_constraint "q" "SHIFT_REGS"
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  "Shift amount register.")
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;; Keep 'x' for backward compatibility with user asm.
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(define_register_constraint "x" "FP_REGS"
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  "Floating-point register.")
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(define_register_constraint "y" "TARGET_64BIT ? FP_REGS : FPUPPER_REGS"
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  "Upper floating-point register.")
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(define_register_constraint "Z" "ALL_REGS"
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  "Any register.")
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;; Integer constant constraints.
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(define_constraint "I"
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  "Signed 11-bit integer constant."
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  (and (match_code "const_int")
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       (match_test "VAL_11_BITS_P (ival)")))
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(define_constraint "J"
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  "Signed 14-bit integer constant."
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  (and (match_code "const_int")
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       (match_test "VAL_14_BITS_P (ival)")))
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(define_constraint "K"
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  "Integer constant that can be deposited with a zdepi instruction."
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  (and (match_code "const_int")
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       (match_test "zdepi_cint_p (ival)")))
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(define_constraint "L"
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  "Signed 5-bit integer constant."
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  (and (match_code "const_int")
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       (match_test "VAL_5_BITS_P (ival)")))
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(define_constraint "M"
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  "Integer constant 0."
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  (and (match_code "const_int")
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       (match_test "ival == 0")))
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(define_constraint "N"
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  "Integer constant that can be loaded with a ldil instruction."
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  (and (match_code "const_int")
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       (match_test "ldil_cint_p (ival)")))
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(define_constraint "O"
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  "Integer constant such that ival+1 is a power of 2."
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  (and (match_code "const_int")
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       (match_test "(ival & (ival + 1)) == 0")))
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(define_constraint "P"
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  "Integer constant that can be used as an and mask in depi and
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   extru instructions."
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  (and (match_code "const_int")
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       (match_test "and_mask_p (ival)")))
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(define_constraint "S"
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  "Integer constant 31."
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  (and (match_code "const_int")
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       (match_test "ival == 31")))
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(define_constraint "U"
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  "Integer constant 63."
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  (and (match_code "const_int")
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       (match_test "ival == 63")))
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;; Floating-point constant constraints.
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(define_constraint "G"
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  "Floating-point constant 0."
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  (and (match_code "const_double")
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       (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT
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                    && op == CONST0_RTX (mode)")))
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;; Extra constraints.
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(define_constraint "A"
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  "A LO_SUM DLT memory operand."
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  (and (match_code "mem")
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       (match_test "IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))")))
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(define_constraint "Q"
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  "A memory operand that can be used as the destination operand of an
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   integer store, or the source operand of an integer load.  That is
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   any memory operand that isn't a symbolic, indexed or lo_sum memory
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   operand.  Note that an unassigned pseudo register is such a memory
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   operand.  We accept unassigned pseudo registers because reload
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   generates them and then doesn't re-recognize the insn, causing
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   constrain_operands to fail."
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  (match_test "integer_store_memory_operand (op, mode)"))
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(define_constraint "R"
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  "A scaled or unscaled indexed memory operand that can be used as the
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   source address in integer and floating-point loads."
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  (and (match_code "mem")
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       (match_test "IS_INDEX_ADDR_P (XEXP (op, 0))")))
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(define_constraint "T"
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  "A memory operand for floating-point loads and stores."
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  (and (match_code "mem")
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       (match_test "!IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))
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                    && !IS_INDEX_ADDR_P (XEXP (op, 0))
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                    && memory_address_p ((GET_MODE_SIZE (mode) == 4
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                                          ? SFmode : DFmode),
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                                         XEXP (op, 0))")))
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;; We could allow short displacements but TARGET_LEGITIMATE_ADDRESS_P
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;; can't tell when a long displacement is valid.
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(define_constraint "W"
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  "A register indirect memory operand."
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  (and (match_code "mem")
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       (match_test "REG_P (XEXP (op, 0))
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                    && REG_OK_FOR_BASE_P (XEXP (op, 0))")))

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