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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [picochip/] [dfa_space.md] - Blame information for rev 282

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1 282 jeremybenn
;; GCC machine description for picochip
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;; Contributed by picoChip Designs Ltd (http://www.picochip.com)
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;; Maintained by Daniel Towner (dant@picochip.com) and Hariharan
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;; Sandanagobalane (hariharan@picochip.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not, see
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;; .
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;; The following DFA description schedules instructions for space.  The
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;; schedule seeks to avoid stall cycles (e.g., memory load), but the
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;; instructions are not VLIW packed (whenever instructions are packed
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;; together, an additional byte is used to denote this, which
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;; increases the code size).
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;; No special handling of the long constants is necessary (as in
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;; dfa_speed.md), since VLIW packing is not used.
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;; Memory instructions stall for one cycle.  All other instructions
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;; complete ready for the next cycle.
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(define_insn_reservation "nonStallInsn" 1
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  (and (eq_attr "schedType" "space")
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       (eq_attr "type" "!mem"))
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  "slot0+slot1+slot2")
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(define_insn_reservation "stallInsn" 2
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  (and (eq_attr "schedType" "space")
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       (eq_attr "type" "mem"))
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  "slot0+slot1+slot2")

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