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jeremybenn |
;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
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;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "ppc40x,ppc40xiu")
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(define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
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(define_cpu_unit "iu_40x" "ppc40xiu")
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;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
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;; Embedded PowerPC controller
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;; In-order execution
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;; Max issue two insns/cycle (includes one branch)
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(define_insn_reservation "ppc403-load" 2
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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load_l,store_c,sync")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-store" 2
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(and (eq_attr "type" "store,store_ux,store_u")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-integer" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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var_shift_rotate,cntlz,exts,isel")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x,iu_40x")
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(define_insn_reservation "ppc403-three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x,iu_40x,iu_40x")
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(define_insn_reservation "ppc403-compare" 3
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(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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var_delayed_compare")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x,nothing,bpu_40x")
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(define_insn_reservation "ppc403-imul" 4
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppc403"))
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"iu_40x*4")
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(define_insn_reservation "ppc405-imul" 5
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(and (eq_attr "type" "imul,imul_compare")
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(eq_attr "cpu" "ppc405"))
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"iu_40x*4")
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(define_insn_reservation "ppc405-imul2" 3
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(and (eq_attr "type" "imul2")
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(eq_attr "cpu" "ppc405"))
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"iu_40x*2")
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(define_insn_reservation "ppc405-imul3" 2
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(and (eq_attr "type" "imul3")
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(eq_attr "cpu" "ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-idiv" 33
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x*33")
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(define_insn_reservation "ppc403-mfcr" 2
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-mtcr" 3
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-mtjmpr" 4
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-mfjmpr" 2
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-jmpreg" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "ppc403,ppc405"))
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"bpu_40x")
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(define_insn_reservation "ppc403-cr" 2
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppc403,ppc405"))
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"bpu_40x")
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(define_insn_reservation "ppc405-float" 11
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,\
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fpcompare,fp,dmul,sdiv,ddiv")
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(eq_attr "cpu" "ppc405"))
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"fpu_405*10")
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