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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [rs6000/] [440.md] - Blame information for rev 301

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Line No. Rev Author Line
1 282 jeremybenn
;; Scheduling description for IBM PowerPC 440 processor.
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;;   Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;; PPC440 Embedded PowerPC controller
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;; dual issue
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;; i_pipe - complex integer / compare / branch
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;; j_pipe - simple integer arithmetic
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;; l_pipe - load-store
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;; f_pipe - floating point arithmetic
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(define_automaton "ppc440_core,ppc440_apu")
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(define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
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(define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
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(define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
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(define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
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(define_insn_reservation "ppc440-load" 3
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  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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                        load_l,store_c,sync")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_l_pipe")
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(define_insn_reservation "ppc440-store" 3
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  (and (eq_attr "type" "store,store_ux,store_u")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_l_pipe")
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(define_insn_reservation "ppc440-fpload" 4
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  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_l_pipe")
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(define_insn_reservation "ppc440-fpstore" 3
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  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_l_pipe")
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(define_insn_reservation "ppc440-integer" 1
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  (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
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                        trap,var_shift_rotate,cntlz,exts,isel")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
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(define_insn_reservation "ppc440-two" 1
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  (and (eq_attr "type" "two")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue_0+ppc440_issue_1,\
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   ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
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(define_insn_reservation "ppc440-three" 1
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  (and (eq_attr "type" "three")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
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   ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
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(define_insn_reservation "ppc440-imul" 3
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  (and (eq_attr "type" "imul,imul_compare")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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(define_insn_reservation "ppc440-imul2" 2
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  (and (eq_attr "type" "imul2,imul3")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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(define_insn_reservation "ppc440-idiv" 34
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  (and (eq_attr "type" "idiv")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe*33")
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(define_insn_reservation "ppc440-branch" 1
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  (and (eq_attr "type" "branch,jmpreg,isync")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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(define_insn_reservation "ppc440-compare" 2
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  (and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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(define_insn_reservation "ppc440-fpcompare" 3 ; 2
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  (and (eq_attr "type" "fpcompare")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
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(define_insn_reservation "ppc440-fp" 5
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  (and (eq_attr "type" "fp,dmul")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_f_pipe")
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(define_insn_reservation "ppc440-sdiv" 19
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  (and (eq_attr "type" "sdiv")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_f_pipe*15")
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(define_insn_reservation "ppc440-ddiv" 33
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  (and (eq_attr "type" "ddiv")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_f_pipe*29")
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(define_insn_reservation "ppc440-mtcr" 3
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  (and (eq_attr "type" "mtcr")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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(define_insn_reservation "ppc440-mtjmpr" 4
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  (and (eq_attr "type" "mtjmpr")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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(define_insn_reservation "ppc440-mfjmpr" 2
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  (and (eq_attr "type" "mfjmpr")
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       (eq_attr "cpu" "ppc440"))
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  "ppc440_issue,ppc440_i_pipe")
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