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jeremybenn |
;; Scheduling description for Motorola PowerPC 7450 processor.
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;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
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(define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
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(define_cpu_unit "mciu_7450" "ppc7450mciu")
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(define_cpu_unit "fpu_7450" "ppc7450fp")
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(define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
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(define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
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(define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
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(define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
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;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
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;; IU1,IU2,IU3 can perform all integer operations
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;; MCIU performs imul and idiv, cr logical, SPR moves
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;; LSU 2 stage pipelined
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;; FPU 3 stage pipelined
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;; It also has 4 vector units, one for each type of vector instruction.
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;; However, we can only dispatch 2 instructions per cycle.
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;; Max issue 3 insns/clock cycle (includes 1 branch)
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;; In-order execution
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;; Branches go straight to the BPU. All other insns are handled
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;; by a dispatch unit which can issue a max of 3 insns per cycle.
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(define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
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(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
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(define_insn_reservation "ppc7450-load" 3
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
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load_ux,load_u,vecload")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,lsu_7450")
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(define_insn_reservation "ppc7450-store" 3
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(and (eq_attr "type" "store,store_ux,store_u,vecstore")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,lsu_7450")
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(define_insn_reservation "ppc7450-fpload" 4
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,lsu_7450")
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(define_insn_reservation "ppc7450-fpstore" 3
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(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,lsu_7450*3")
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(define_insn_reservation "ppc7450-llsc" 3
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(and (eq_attr "type" "load_l,store_c")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,lsu_7450")
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(define_insn_reservation "ppc7450-sync" 35
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(and (eq_attr "type" "sync")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,lsu_7450")
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(define_insn_reservation "ppc7450-integer" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
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trap,var_shift_rotate,cntlz,exts,isel")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
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(define_insn_reservation "ppc7450-two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
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(define_insn_reservation "ppc7450-three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
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iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
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(define_insn_reservation "ppc7450-imul" 4
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(and (eq_attr "type" "imul,imul_compare")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,mciu_7450*2")
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(define_insn_reservation "ppc7450-imul2" 3
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(and (eq_attr "type" "imul2,imul3")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,mciu_7450")
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(define_insn_reservation "ppc7450-idiv" 23
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,mciu_7450*23")
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(define_insn_reservation "ppc7450-compare" 2
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(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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var_delayed_compare")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
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(define_insn_reservation "ppc7450-fpcompare" 5
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,fpu_7450")
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(define_insn_reservation "ppc7450-fp" 5
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(and (eq_attr "type" "fp,dmul")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,fpu_7450")
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; Divides are not pipelined
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(define_insn_reservation "ppc7450-sdiv" 21
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,fpu_7450*21")
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(define_insn_reservation "ppc7450-ddiv" 35
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,fpu_7450*35")
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(define_insn_reservation "ppc7450-mfcr" 2
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(and (eq_attr "type" "mfcr,mtcr")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,mciu_7450")
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(define_insn_reservation "ppc7450-crlogical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,mciu_7450")
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(define_insn_reservation "ppc7450-mtjmpr" 2
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppc7450"))
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"nothing,mciu_7450*2")
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(define_insn_reservation "ppc7450-mfjmpr" 3
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "ppc7450"))
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"nothing,mciu_7450*2")
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(define_insn_reservation "ppc7450-jmpreg" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "ppc7450"))
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"nothing,bpu_7450")
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;; Altivec
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(define_insn_reservation "ppc7450-vecsimple" 1
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(and (eq_attr "type" "vecsimple")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
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(define_insn_reservation "ppc7450-veccomplex" 4
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(and (eq_attr "type" "veccomplex")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
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(define_insn_reservation "ppc7450-veccmp" 2
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(and (eq_attr "type" "veccmp")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
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(define_insn_reservation "ppc7450-vecfloat" 4
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(and (eq_attr "type" "vecfloat")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,ppc7450_vec_du,vecflt_7450")
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(define_insn_reservation "ppc7450-vecperm" 2
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(and (eq_attr "type" "vecperm")
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(eq_attr "cpu" "ppc7450"))
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"ppc7450_du,ppc7450_vec_du,vecperm_7450")
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