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jeremybenn |
/* Definitions of target machine for GNU compiler, for IBM RS/6000.
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Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
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Free Software Foundation, Inc.
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Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Note that some other tm.h files include this one and then override
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many of the definitions. */
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/* Definitions for the object file format. These are set at
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compile-time. */
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#define OBJECT_XCOFF 1
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#define OBJECT_ELF 2
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#define OBJECT_PEF 3
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#define OBJECT_MACHO 4
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#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
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#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
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#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
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#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
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#ifndef TARGET_AIX
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#define TARGET_AIX 0
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#endif
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/* Control whether function entry points use a "dot" symbol when
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ABI_AIX. */
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#define DOT_SYMBOLS 1
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/* Default string to use for cpu if not specified. */
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#ifndef TARGET_CPU_DEFAULT
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#define TARGET_CPU_DEFAULT ((char *)0)
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#endif
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/* If configured for PPC405, support PPC405CR Erratum77. */
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#ifdef CONFIG_PPC405CR
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#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
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#else
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#define PPC405_ERRATUM77 0
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#endif
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#ifndef TARGET_PAIRED_FLOAT
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#define TARGET_PAIRED_FLOAT 0
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#endif
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#ifdef HAVE_AS_POPCNTB
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#define ASM_CPU_POWER5_SPEC "-mpower5"
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#else
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#define ASM_CPU_POWER5_SPEC "-mpower4"
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#endif
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#ifdef HAVE_AS_DFP
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#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
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#else
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#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
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#endif
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#ifdef HAVE_AS_POPCNTD
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#define ASM_CPU_POWER7_SPEC "-mpower7"
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#else
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#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
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#endif
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#ifdef HAVE_AS_DCI
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#define ASM_CPU_476_SPEC "-m476"
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#else
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#define ASM_CPU_476_SPEC "-mpower4"
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#endif
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/* Common ASM definitions used by ASM_SPEC among the various targets for
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handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
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provide the default assembler options if the user uses -mcpu=native, so if
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you make changes here, make them also there. */
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#define ASM_CPU_SPEC \
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"%{!mcpu*: \
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%{mpower: %{!mpower2: -mpwr}} \
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%{mpower2: -mpwrx} \
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%{mpowerpc64*: -mppc64} \
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%{!mpowerpc64*: %{mpowerpc*: -mppc}} \
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%{mno-power: %{!mpowerpc*: -mcom}} \
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%{!mno-power: %{!mpower*: %(asm_default)}}} \
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%{mcpu=native: %(asm_cpu_native)} \
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%{mcpu=common: -mcom} \
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%{mcpu=cell: -mcell} \
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%{mcpu=power: -mpwr} \
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%{mcpu=power2: -mpwrx} \
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%{mcpu=power3: -mppc64} \
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%{mcpu=power4: -mpower4} \
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%{mcpu=power5: %(asm_cpu_power5)} \
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%{mcpu=power5+: %(asm_cpu_power5)} \
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%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
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%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
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%{mcpu=power7: %(asm_cpu_power7)} \
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%{mcpu=a2: -ma2} \
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%{mcpu=powerpc: -mppc} \
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%{mcpu=rios: -mpwr} \
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%{mcpu=rios1: -mpwr} \
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%{mcpu=rios2: -mpwrx} \
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%{mcpu=rsc: -mpwr} \
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%{mcpu=rsc1: -mpwr} \
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%{mcpu=rs64a: -mppc64} \
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%{mcpu=401: -mppc} \
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%{mcpu=403: -m403} \
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%{mcpu=405: -m405} \
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%{mcpu=405fp: -m405} \
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%{mcpu=440: -m440} \
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%{mcpu=440fp: -m440} \
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%{mcpu=464: -m440} \
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%{mcpu=464fp: -m440} \
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%{mcpu=476: %(asm_cpu_476)} \
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%{mcpu=476fp: %(asm_cpu_476)} \
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%{mcpu=505: -mppc} \
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%{mcpu=601: -m601} \
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%{mcpu=602: -mppc} \
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%{mcpu=603: -mppc} \
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%{mcpu=603e: -mppc} \
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%{mcpu=ec603e: -mppc} \
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%{mcpu=604: -mppc} \
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%{mcpu=604e: -mppc} \
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%{mcpu=620: -mppc64} \
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%{mcpu=630: -mppc64} \
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%{mcpu=740: -mppc} \
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%{mcpu=750: -mppc} \
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%{mcpu=G3: -mppc} \
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%{mcpu=7400: -mppc -maltivec} \
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%{mcpu=7450: -mppc -maltivec} \
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%{mcpu=G4: -mppc -maltivec} \
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%{mcpu=801: -mppc} \
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%{mcpu=821: -mppc} \
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%{mcpu=823: -mppc} \
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%{mcpu=860: -mppc} \
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%{mcpu=970: -mpower4 -maltivec} \
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%{mcpu=G5: -mpower4 -maltivec} \
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%{mcpu=8540: -me500} \
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%{mcpu=8548: -me500} \
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%{mcpu=e300c2: -me300} \
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%{mcpu=e300c3: -me300} \
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%{mcpu=e500mc: -me500mc} \
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%{mcpu=e500mc64: -me500mc64} \
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%{maltivec: -maltivec} \
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-many"
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#define CPP_DEFAULT_SPEC ""
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#define ASM_DEFAULT_SPEC ""
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/* This macro defines names of additional specifications to put in the specs
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that can be used in various specifications like CC1_SPEC. Its definition
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is an initializer with a subgrouping for each command option.
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Each subgrouping contains a string constant, that defines the
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specification name, and a string constant that used by the GCC driver
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program.
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Do not define this macro if it does not need to do anything. */
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#define SUBTARGET_EXTRA_SPECS
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#define EXTRA_SPECS \
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{ "cpp_default", CPP_DEFAULT_SPEC }, \
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{ "asm_cpu", ASM_CPU_SPEC }, \
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{ "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
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{ "asm_default", ASM_DEFAULT_SPEC }, \
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{ "cc1_cpu", CC1_CPU_SPEC }, \
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{ "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
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{ "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
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{ "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
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{ "asm_cpu_476", ASM_CPU_476_SPEC }, \
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SUBTARGET_EXTRA_SPECS
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/* -mcpu=native handling only makes sense with compiler running on
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an PowerPC chip. If changing this condition, also change
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the condition in driver-rs6000.c. */
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#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
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/* In driver-rs6000.c. */
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extern const char *host_detect_local_cpu (int argc, const char **argv);
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#define EXTRA_SPEC_FUNCTIONS \
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{ "local_cpu_detect", host_detect_local_cpu },
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#define HAVE_LOCAL_CPU_DETECT
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#define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
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#else
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#define ASM_CPU_NATIVE_SPEC "%(asm_default)"
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#endif
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#ifndef CC1_CPU_SPEC
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#ifdef HAVE_LOCAL_CPU_DETECT
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#define CC1_CPU_SPEC \
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"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
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%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
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#else
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#define CC1_CPU_SPEC ""
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#endif
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#endif
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/* Architecture type. */
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/* Define TARGET_MFCRF if the target assembler does not support the
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optional field operand for mfcr. */
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#ifndef HAVE_AS_MFCRF
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#undef TARGET_MFCRF
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#define TARGET_MFCRF 0
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#endif
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/* Define TARGET_POPCNTB if the target assembler does not support the
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popcount byte instruction. */
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#ifndef HAVE_AS_POPCNTB
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#undef TARGET_POPCNTB
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#define TARGET_POPCNTB 0
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#endif
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/* Define TARGET_FPRND if the target assembler does not support the
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fp rounding instructions. */
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#ifndef HAVE_AS_FPRND
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#undef TARGET_FPRND
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#define TARGET_FPRND 0
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#endif
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/* Define TARGET_CMPB if the target assembler does not support the
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cmpb instruction. */
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#ifndef HAVE_AS_CMPB
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#undef TARGET_CMPB
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#define TARGET_CMPB 0
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#endif
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/* Define TARGET_MFPGPR if the target assembler does not support the
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mffpr and mftgpr instructions. */
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#ifndef HAVE_AS_MFPGPR
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#undef TARGET_MFPGPR
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#define TARGET_MFPGPR 0
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#endif
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/* Define TARGET_DFP if the target assembler does not support decimal
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floating point instructions. */
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#ifndef HAVE_AS_DFP
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#undef TARGET_DFP
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#define TARGET_DFP 0
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#endif
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/* Define TARGET_POPCNTD if the target assembler does not support the
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popcount word and double word instructions. */
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#ifndef HAVE_AS_POPCNTD
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#undef TARGET_POPCNTD
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#define TARGET_POPCNTD 0
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#endif
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/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
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not, generate the lwsync code as an integer constant. */
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#ifdef HAVE_AS_LWSYNC
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#define TARGET_LWSYNC_INSTRUCTION 1
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#else
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#define TARGET_LWSYNC_INSTRUCTION 0
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#endif
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/* Define TARGET_TLS_MARKERS if the target assembler does not support
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arg markers for __tls_get_addr calls. */
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#ifndef HAVE_AS_TLS_MARKERS
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#undef TARGET_TLS_MARKERS
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#define TARGET_TLS_MARKERS 0
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#else
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#define TARGET_TLS_MARKERS tls_markers
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#endif
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#ifndef TARGET_SECURE_PLT
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#define TARGET_SECURE_PLT 0
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#endif
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#define TARGET_32BIT (! TARGET_64BIT)
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#ifndef HAVE_AS_TLS
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#define HAVE_AS_TLS 0
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#endif
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/* Return 1 for a symbol ref for a thread-local storage symbol. */
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#define RS6000_SYMBOL_REF_TLS_P(RTX) \
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(GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
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#ifdef IN_LIBGCC2
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/* For libgcc2 we make sure this is a compile time constant */
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#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
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#undef TARGET_POWERPC64
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#define TARGET_POWERPC64 1
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#else
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#undef TARGET_POWERPC64
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#define TARGET_POWERPC64 0
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#endif
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#else
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/* The option machinery will define this. */
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#endif
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#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
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/* Processor type. Order must match cpu attribute in MD file. */
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enum processor_type
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{
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PROCESSOR_RIOS1,
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PROCESSOR_RIOS2,
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PROCESSOR_RS64A,
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PROCESSOR_MPCCORE,
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PROCESSOR_PPC403,
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PROCESSOR_PPC405,
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PROCESSOR_PPC440,
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PROCESSOR_PPC476,
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PROCESSOR_PPC601,
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PROCESSOR_PPC603,
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PROCESSOR_PPC604,
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|
|
PROCESSOR_PPC604e,
|
336 |
|
|
PROCESSOR_PPC620,
|
337 |
|
|
PROCESSOR_PPC630,
|
338 |
|
|
PROCESSOR_PPC750,
|
339 |
|
|
PROCESSOR_PPC7400,
|
340 |
|
|
PROCESSOR_PPC7450,
|
341 |
|
|
PROCESSOR_PPC8540,
|
342 |
|
|
PROCESSOR_PPCE300C2,
|
343 |
|
|
PROCESSOR_PPCE300C3,
|
344 |
|
|
PROCESSOR_PPCE500MC,
|
345 |
|
|
PROCESSOR_PPCE500MC64,
|
346 |
|
|
PROCESSOR_POWER4,
|
347 |
|
|
PROCESSOR_POWER5,
|
348 |
|
|
PROCESSOR_POWER6,
|
349 |
|
|
PROCESSOR_POWER7,
|
350 |
|
|
PROCESSOR_CELL,
|
351 |
|
|
PROCESSOR_PPCA2
|
352 |
|
|
};
|
353 |
|
|
|
354 |
|
|
/* FPU operations supported.
|
355 |
|
|
Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
|
356 |
|
|
also test TARGET_HARD_FLOAT. */
|
357 |
|
|
#define TARGET_SINGLE_FLOAT 1
|
358 |
|
|
#define TARGET_DOUBLE_FLOAT 1
|
359 |
|
|
#define TARGET_SINGLE_FPU 0
|
360 |
|
|
#define TARGET_SIMPLE_FPU 0
|
361 |
|
|
#define TARGET_XILINX_FPU 0
|
362 |
|
|
|
363 |
|
|
extern enum processor_type rs6000_cpu;
|
364 |
|
|
|
365 |
|
|
/* Recast the processor type to the cpu attribute. */
|
366 |
|
|
#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
|
367 |
|
|
|
368 |
|
|
/* Define generic processor types based upon current deployment. */
|
369 |
|
|
#define PROCESSOR_COMMON PROCESSOR_PPC601
|
370 |
|
|
#define PROCESSOR_POWER PROCESSOR_RIOS1
|
371 |
|
|
#define PROCESSOR_POWERPC PROCESSOR_PPC604
|
372 |
|
|
#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
|
373 |
|
|
|
374 |
|
|
/* Define the default processor. This is overridden by other tm.h files. */
|
375 |
|
|
#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
|
376 |
|
|
#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
|
377 |
|
|
|
378 |
|
|
/* FP processor type. */
|
379 |
|
|
enum fpu_type_t
|
380 |
|
|
{
|
381 |
|
|
FPU_NONE, /* No FPU */
|
382 |
|
|
FPU_SF_LITE, /* Limited Single Precision FPU */
|
383 |
|
|
FPU_DF_LITE, /* Limited Double Precision FPU */
|
384 |
|
|
FPU_SF_FULL, /* Full Single Precision FPU */
|
385 |
|
|
FPU_DF_FULL /* Full Double Single Precision FPU */
|
386 |
|
|
};
|
387 |
|
|
|
388 |
|
|
extern enum fpu_type_t fpu_type;
|
389 |
|
|
|
390 |
|
|
/* Specify the dialect of assembler to use. New mnemonics is dialect one
|
391 |
|
|
and the old mnemonics are dialect zero. */
|
392 |
|
|
#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
|
393 |
|
|
|
394 |
|
|
/* Types of costly dependences. */
|
395 |
|
|
enum rs6000_dependence_cost
|
396 |
|
|
{
|
397 |
|
|
max_dep_latency = 1000,
|
398 |
|
|
no_dep_costly,
|
399 |
|
|
all_deps_costly,
|
400 |
|
|
true_store_to_load_dep_costly,
|
401 |
|
|
store_to_load_dep_costly
|
402 |
|
|
};
|
403 |
|
|
|
404 |
|
|
/* Types of nop insertion schemes in sched target hook sched_finish. */
|
405 |
|
|
enum rs6000_nop_insertion
|
406 |
|
|
{
|
407 |
|
|
sched_finish_regroup_exact = 1000,
|
408 |
|
|
sched_finish_pad_groups,
|
409 |
|
|
sched_finish_none
|
410 |
|
|
};
|
411 |
|
|
|
412 |
|
|
/* Dispatch group termination caused by an insn. */
|
413 |
|
|
enum group_termination
|
414 |
|
|
{
|
415 |
|
|
current_group,
|
416 |
|
|
previous_group
|
417 |
|
|
};
|
418 |
|
|
|
419 |
|
|
/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
|
420 |
|
|
struct rs6000_cpu_select
|
421 |
|
|
{
|
422 |
|
|
const char *string;
|
423 |
|
|
const char *name;
|
424 |
|
|
int set_tune_p;
|
425 |
|
|
int set_arch_p;
|
426 |
|
|
};
|
427 |
|
|
|
428 |
|
|
extern struct rs6000_cpu_select rs6000_select[];
|
429 |
|
|
|
430 |
|
|
/* Debug support */
|
431 |
|
|
extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
|
432 |
|
|
extern int rs6000_debug_stack; /* debug stack applications */
|
433 |
|
|
extern int rs6000_debug_arg; /* debug argument handling */
|
434 |
|
|
extern int rs6000_debug_reg; /* debug register handling */
|
435 |
|
|
extern int rs6000_debug_addr; /* debug memory addressing */
|
436 |
|
|
extern int rs6000_debug_cost; /* debug rtx_costs */
|
437 |
|
|
|
438 |
|
|
#define TARGET_DEBUG_STACK rs6000_debug_stack
|
439 |
|
|
#define TARGET_DEBUG_ARG rs6000_debug_arg
|
440 |
|
|
#define TARGET_DEBUG_REG rs6000_debug_reg
|
441 |
|
|
#define TARGET_DEBUG_ADDR rs6000_debug_addr
|
442 |
|
|
#define TARGET_DEBUG_COST rs6000_debug_cost
|
443 |
|
|
|
444 |
|
|
extern const char *rs6000_traceback_name; /* Type of traceback table. */
|
445 |
|
|
|
446 |
|
|
/* These are separate from target_flags because we've run out of bits
|
447 |
|
|
there. */
|
448 |
|
|
extern int rs6000_long_double_type_size;
|
449 |
|
|
extern int rs6000_ieeequad;
|
450 |
|
|
extern int rs6000_altivec_abi;
|
451 |
|
|
extern int rs6000_spe_abi;
|
452 |
|
|
extern int rs6000_spe;
|
453 |
|
|
extern int rs6000_float_gprs;
|
454 |
|
|
extern int rs6000_alignment_flags;
|
455 |
|
|
extern const char *rs6000_sched_insert_nops_str;
|
456 |
|
|
extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
|
457 |
|
|
extern int rs6000_xilinx_fpu;
|
458 |
|
|
|
459 |
|
|
/* Describe which vector unit to use for a given machine mode. */
|
460 |
|
|
enum rs6000_vector {
|
461 |
|
|
VECTOR_NONE, /* Type is not a vector or not supported */
|
462 |
|
|
VECTOR_ALTIVEC, /* Use altivec for vector processing */
|
463 |
|
|
VECTOR_VSX, /* Use VSX for vector processing */
|
464 |
|
|
VECTOR_PAIRED, /* Use paired floating point for vectors */
|
465 |
|
|
VECTOR_SPE, /* Use SPE for vector processing */
|
466 |
|
|
VECTOR_OTHER /* Some other vector unit */
|
467 |
|
|
};
|
468 |
|
|
|
469 |
|
|
extern enum rs6000_vector rs6000_vector_unit[];
|
470 |
|
|
|
471 |
|
|
#define VECTOR_UNIT_NONE_P(MODE) \
|
472 |
|
|
(rs6000_vector_unit[(MODE)] == VECTOR_NONE)
|
473 |
|
|
|
474 |
|
|
#define VECTOR_UNIT_VSX_P(MODE) \
|
475 |
|
|
(rs6000_vector_unit[(MODE)] == VECTOR_VSX)
|
476 |
|
|
|
477 |
|
|
#define VECTOR_UNIT_ALTIVEC_P(MODE) \
|
478 |
|
|
(rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
|
479 |
|
|
|
480 |
|
|
#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
|
481 |
|
|
(rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
|
482 |
|
|
|| rs6000_vector_unit[(MODE)] == VECTOR_VSX)
|
483 |
|
|
|
484 |
|
|
/* Describe whether to use VSX loads or Altivec loads. For now, just use the
|
485 |
|
|
same unit as the vector unit we are using, but we may want to migrate to
|
486 |
|
|
using VSX style loads even for types handled by altivec. */
|
487 |
|
|
extern enum rs6000_vector rs6000_vector_mem[];
|
488 |
|
|
|
489 |
|
|
#define VECTOR_MEM_NONE_P(MODE) \
|
490 |
|
|
(rs6000_vector_mem[(MODE)] == VECTOR_NONE)
|
491 |
|
|
|
492 |
|
|
#define VECTOR_MEM_VSX_P(MODE) \
|
493 |
|
|
(rs6000_vector_mem[(MODE)] == VECTOR_VSX)
|
494 |
|
|
|
495 |
|
|
#define VECTOR_MEM_ALTIVEC_P(MODE) \
|
496 |
|
|
(rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
|
497 |
|
|
|
498 |
|
|
#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
|
499 |
|
|
(rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
|
500 |
|
|
|| rs6000_vector_mem[(MODE)] == VECTOR_VSX)
|
501 |
|
|
|
502 |
|
|
/* Return the alignment of a given vector type, which is set based on the
|
503 |
|
|
vector unit use. VSX for instance can load 32 or 64 bit aligned words
|
504 |
|
|
without problems, while Altivec requires 128-bit aligned vectors. */
|
505 |
|
|
extern int rs6000_vector_align[];
|
506 |
|
|
|
507 |
|
|
#define VECTOR_ALIGN(MODE) \
|
508 |
|
|
((rs6000_vector_align[(MODE)] != 0) \
|
509 |
|
|
? rs6000_vector_align[(MODE)] \
|
510 |
|
|
: (int)GET_MODE_BITSIZE ((MODE)))
|
511 |
|
|
|
512 |
|
|
/* Alignment options for fields in structures for sub-targets following
|
513 |
|
|
AIX-like ABI.
|
514 |
|
|
ALIGN_POWER word-aligns FP doubles (default AIX ABI).
|
515 |
|
|
ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
|
516 |
|
|
|
517 |
|
|
Override the macro definitions when compiling libobjc to avoid undefined
|
518 |
|
|
reference to rs6000_alignment_flags due to library's use of GCC alignment
|
519 |
|
|
macros which use the macros below. */
|
520 |
|
|
|
521 |
|
|
#ifndef IN_TARGET_LIBS
|
522 |
|
|
#define MASK_ALIGN_POWER 0x00000000
|
523 |
|
|
#define MASK_ALIGN_NATURAL 0x00000001
|
524 |
|
|
#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
|
525 |
|
|
#else
|
526 |
|
|
#define TARGET_ALIGN_NATURAL 0
|
527 |
|
|
#endif
|
528 |
|
|
|
529 |
|
|
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
|
530 |
|
|
#define TARGET_IEEEQUAD rs6000_ieeequad
|
531 |
|
|
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
|
532 |
|
|
#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
|
533 |
|
|
|
534 |
|
|
#define TARGET_SPE_ABI 0
|
535 |
|
|
#define TARGET_SPE 0
|
536 |
|
|
#define TARGET_E500 0
|
537 |
|
|
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
|
538 |
|
|
#define TARGET_FPRS 1
|
539 |
|
|
#define TARGET_E500_SINGLE 0
|
540 |
|
|
#define TARGET_E500_DOUBLE 0
|
541 |
|
|
#define CHECK_E500_OPTIONS do { } while (0)
|
542 |
|
|
|
543 |
|
|
/* E500 processors only support plain "sync", not lwsync. */
|
544 |
|
|
#define TARGET_NO_LWSYNC TARGET_E500
|
545 |
|
|
|
546 |
|
|
/* Sometimes certain combinations of command options do not make sense
|
547 |
|
|
on a particular target machine. You can define a macro
|
548 |
|
|
`OVERRIDE_OPTIONS' to take account of this. This macro, if
|
549 |
|
|
defined, is executed once just after all the command options have
|
550 |
|
|
been parsed.
|
551 |
|
|
|
552 |
|
|
Do not use this macro to turn on various extra optimizations for
|
553 |
|
|
`-O'. That is what `OPTIMIZATION_OPTIONS' is for.
|
554 |
|
|
|
555 |
|
|
On the RS/6000 this is used to define the target cpu type. */
|
556 |
|
|
|
557 |
|
|
#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
|
558 |
|
|
|
559 |
|
|
/* Define this to change the optimizations performed by default. */
|
560 |
|
|
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
|
561 |
|
|
|
562 |
|
|
/* Show we can debug even without a frame pointer. */
|
563 |
|
|
#define CAN_DEBUG_WITHOUT_FP
|
564 |
|
|
|
565 |
|
|
/* Target pragma. */
|
566 |
|
|
#define REGISTER_TARGET_PRAGMAS() do { \
|
567 |
|
|
c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
|
568 |
|
|
targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
|
569 |
|
|
} while (0)
|
570 |
|
|
|
571 |
|
|
/* Target #defines. */
|
572 |
|
|
#define TARGET_CPU_CPP_BUILTINS() \
|
573 |
|
|
rs6000_cpu_cpp_builtins (pfile)
|
574 |
|
|
|
575 |
|
|
/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
|
576 |
|
|
we're compiling for. Some configurations may need to override it. */
|
577 |
|
|
#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
|
578 |
|
|
do \
|
579 |
|
|
{ \
|
580 |
|
|
if (BYTES_BIG_ENDIAN) \
|
581 |
|
|
{ \
|
582 |
|
|
builtin_define ("__BIG_ENDIAN__"); \
|
583 |
|
|
builtin_define ("_BIG_ENDIAN"); \
|
584 |
|
|
builtin_assert ("machine=bigendian"); \
|
585 |
|
|
} \
|
586 |
|
|
else \
|
587 |
|
|
{ \
|
588 |
|
|
builtin_define ("__LITTLE_ENDIAN__"); \
|
589 |
|
|
builtin_define ("_LITTLE_ENDIAN"); \
|
590 |
|
|
builtin_assert ("machine=littleendian"); \
|
591 |
|
|
} \
|
592 |
|
|
} \
|
593 |
|
|
while (0)
|
594 |
|
|
|
595 |
|
|
/* Target machine storage layout. */
|
596 |
|
|
|
597 |
|
|
/* Define this macro if it is advisable to hold scalars in registers
|
598 |
|
|
in a wider mode than that declared by the program. In such cases,
|
599 |
|
|
the value is constrained to be within the bounds of the declared
|
600 |
|
|
type, but kept valid in the wider mode. The signedness of the
|
601 |
|
|
extension may differ from that of the type. */
|
602 |
|
|
|
603 |
|
|
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
|
604 |
|
|
if (GET_MODE_CLASS (MODE) == MODE_INT \
|
605 |
|
|
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
|
606 |
|
|
(MODE) = TARGET_32BIT ? SImode : DImode;
|
607 |
|
|
|
608 |
|
|
/* Define this if most significant bit is lowest numbered
|
609 |
|
|
in instructions that operate on numbered bit-fields. */
|
610 |
|
|
/* That is true on RS/6000. */
|
611 |
|
|
#define BITS_BIG_ENDIAN 1
|
612 |
|
|
|
613 |
|
|
/* Define this if most significant byte of a word is the lowest numbered. */
|
614 |
|
|
/* That is true on RS/6000. */
|
615 |
|
|
#define BYTES_BIG_ENDIAN 1
|
616 |
|
|
|
617 |
|
|
/* Define this if most significant word of a multiword number is lowest
|
618 |
|
|
numbered.
|
619 |
|
|
|
620 |
|
|
For RS/6000 we can decide arbitrarily since there are no machine
|
621 |
|
|
instructions for them. Might as well be consistent with bits and bytes. */
|
622 |
|
|
#define WORDS_BIG_ENDIAN 1
|
623 |
|
|
|
624 |
|
|
#define MAX_BITS_PER_WORD 64
|
625 |
|
|
|
626 |
|
|
/* Width of a word, in units (bytes). */
|
627 |
|
|
#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
|
628 |
|
|
#ifdef IN_LIBGCC2
|
629 |
|
|
#define MIN_UNITS_PER_WORD UNITS_PER_WORD
|
630 |
|
|
#else
|
631 |
|
|
#define MIN_UNITS_PER_WORD 4
|
632 |
|
|
#endif
|
633 |
|
|
#define UNITS_PER_FP_WORD 8
|
634 |
|
|
#define UNITS_PER_ALTIVEC_WORD 16
|
635 |
|
|
#define UNITS_PER_VSX_WORD 16
|
636 |
|
|
#define UNITS_PER_SPE_WORD 8
|
637 |
|
|
#define UNITS_PER_PAIRED_WORD 8
|
638 |
|
|
|
639 |
|
|
/* Type used for ptrdiff_t, as a string used in a declaration. */
|
640 |
|
|
#define PTRDIFF_TYPE "int"
|
641 |
|
|
|
642 |
|
|
/* Type used for size_t, as a string used in a declaration. */
|
643 |
|
|
#define SIZE_TYPE "long unsigned int"
|
644 |
|
|
|
645 |
|
|
/* Type used for wchar_t, as a string used in a declaration. */
|
646 |
|
|
#define WCHAR_TYPE "short unsigned int"
|
647 |
|
|
|
648 |
|
|
/* Width of wchar_t in bits. */
|
649 |
|
|
#define WCHAR_TYPE_SIZE 16
|
650 |
|
|
|
651 |
|
|
/* A C expression for the size in bits of the type `short' on the
|
652 |
|
|
target machine. If you don't define this, the default is half a
|
653 |
|
|
word. (If this would be less than one storage unit, it is
|
654 |
|
|
rounded up to one unit.) */
|
655 |
|
|
#define SHORT_TYPE_SIZE 16
|
656 |
|
|
|
657 |
|
|
/* A C expression for the size in bits of the type `int' on the
|
658 |
|
|
target machine. If you don't define this, the default is one
|
659 |
|
|
word. */
|
660 |
|
|
#define INT_TYPE_SIZE 32
|
661 |
|
|
|
662 |
|
|
/* A C expression for the size in bits of the type `long' on the
|
663 |
|
|
target machine. If you don't define this, the default is one
|
664 |
|
|
word. */
|
665 |
|
|
#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
|
666 |
|
|
|
667 |
|
|
/* A C expression for the size in bits of the type `long long' on the
|
668 |
|
|
target machine. If you don't define this, the default is two
|
669 |
|
|
words. */
|
670 |
|
|
#define LONG_LONG_TYPE_SIZE 64
|
671 |
|
|
|
672 |
|
|
/* A C expression for the size in bits of the type `float' on the
|
673 |
|
|
target machine. If you don't define this, the default is one
|
674 |
|
|
word. */
|
675 |
|
|
#define FLOAT_TYPE_SIZE 32
|
676 |
|
|
|
677 |
|
|
/* A C expression for the size in bits of the type `double' on the
|
678 |
|
|
target machine. If you don't define this, the default is two
|
679 |
|
|
words. */
|
680 |
|
|
#define DOUBLE_TYPE_SIZE 64
|
681 |
|
|
|
682 |
|
|
/* A C expression for the size in bits of the type `long double' on
|
683 |
|
|
the target machine. If you don't define this, the default is two
|
684 |
|
|
words. */
|
685 |
|
|
#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
|
686 |
|
|
|
687 |
|
|
/* Define this to set long double type size to use in libgcc2.c, which can
|
688 |
|
|
not depend on target_flags. */
|
689 |
|
|
#ifdef __LONG_DOUBLE_128__
|
690 |
|
|
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
|
691 |
|
|
#else
|
692 |
|
|
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
|
693 |
|
|
#endif
|
694 |
|
|
|
695 |
|
|
/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
|
696 |
|
|
#define WIDEST_HARDWARE_FP_SIZE 64
|
697 |
|
|
|
698 |
|
|
/* Width in bits of a pointer.
|
699 |
|
|
See also the macro `Pmode' defined below. */
|
700 |
|
|
extern unsigned rs6000_pointer_size;
|
701 |
|
|
#define POINTER_SIZE rs6000_pointer_size
|
702 |
|
|
|
703 |
|
|
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
|
704 |
|
|
#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
|
705 |
|
|
|
706 |
|
|
/* Boundary (in *bits*) on which stack pointer should be aligned. */
|
707 |
|
|
#define STACK_BOUNDARY \
|
708 |
|
|
((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
|
709 |
|
|
? 64 : 128)
|
710 |
|
|
|
711 |
|
|
/* Allocation boundary (in *bits*) for the code of a function. */
|
712 |
|
|
#define FUNCTION_BOUNDARY 32
|
713 |
|
|
|
714 |
|
|
/* No data type wants to be aligned rounder than this. */
|
715 |
|
|
#define BIGGEST_ALIGNMENT 128
|
716 |
|
|
|
717 |
|
|
/* A C expression to compute the alignment for a variables in the
|
718 |
|
|
local store. TYPE is the data type, and ALIGN is the alignment
|
719 |
|
|
that the object would ordinarily have. */
|
720 |
|
|
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
|
721 |
|
|
DATA_ALIGNMENT (TYPE, ALIGN)
|
722 |
|
|
|
723 |
|
|
/* Alignment of field after `int : 0' in a structure. */
|
724 |
|
|
#define EMPTY_FIELD_BOUNDARY 32
|
725 |
|
|
|
726 |
|
|
/* Every structure's size must be a multiple of this. */
|
727 |
|
|
#define STRUCTURE_SIZE_BOUNDARY 8
|
728 |
|
|
|
729 |
|
|
/* Return 1 if a structure or array containing FIELD should be
|
730 |
|
|
accessed using `BLKMODE'.
|
731 |
|
|
|
732 |
|
|
For the SPE, simd types are V2SI, and gcc can be tempted to put the
|
733 |
|
|
entire thing in a DI and use subregs to access the internals.
|
734 |
|
|
store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
|
735 |
|
|
back-end. Because a single GPR can hold a V2SI, but not a DI, the
|
736 |
|
|
best thing to do is set structs to BLKmode and avoid Severe Tire
|
737 |
|
|
Damage.
|
738 |
|
|
|
739 |
|
|
On e500 v2, DF and DI modes suffer from the same anomaly. DF can
|
740 |
|
|
fit into 1, whereas DI still needs two. */
|
741 |
|
|
#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
|
742 |
|
|
((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
|
743 |
|
|
|| (TARGET_E500_DOUBLE && (MODE) == DFmode))
|
744 |
|
|
|
745 |
|
|
/* A bit-field declared as `int' forces `int' alignment for the struct. */
|
746 |
|
|
#define PCC_BITFIELD_TYPE_MATTERS 1
|
747 |
|
|
|
748 |
|
|
/* Make strings word-aligned so strcpy from constants will be faster.
|
749 |
|
|
Make vector constants quadword aligned. */
|
750 |
|
|
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
|
751 |
|
|
(TREE_CODE (EXP) == STRING_CST \
|
752 |
|
|
&& (STRICT_ALIGNMENT || !optimize_size) \
|
753 |
|
|
&& (ALIGN) < BITS_PER_WORD \
|
754 |
|
|
? BITS_PER_WORD \
|
755 |
|
|
: (ALIGN))
|
756 |
|
|
|
757 |
|
|
/* Make arrays of chars word-aligned for the same reasons.
|
758 |
|
|
Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
|
759 |
|
|
64 bits. */
|
760 |
|
|
#define DATA_ALIGNMENT(TYPE, ALIGN) \
|
761 |
|
|
(TREE_CODE (TYPE) == VECTOR_TYPE \
|
762 |
|
|
? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
|
763 |
|
|
|| (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
|
764 |
|
|
? 64 : 128) \
|
765 |
|
|
: ((TARGET_E500_DOUBLE \
|
766 |
|
|
&& TREE_CODE (TYPE) == REAL_TYPE \
|
767 |
|
|
&& TYPE_MODE (TYPE) == DFmode) \
|
768 |
|
|
? 64 \
|
769 |
|
|
: (TREE_CODE (TYPE) == ARRAY_TYPE \
|
770 |
|
|
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
|
771 |
|
|
&& (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
|
772 |
|
|
|
773 |
|
|
/* Nonzero if move instructions will actually fail to work
|
774 |
|
|
when given unaligned data. */
|
775 |
|
|
#define STRICT_ALIGNMENT 0
|
776 |
|
|
|
777 |
|
|
/* Define this macro to be the value 1 if unaligned accesses have a cost
|
778 |
|
|
many times greater than aligned accesses, for example if they are
|
779 |
|
|
emulated in a trap handler. */
|
780 |
|
|
/* Altivec vector memory instructions simply ignore the low bits; SPE vector
|
781 |
|
|
memory instructions trap on unaligned accesses; VSX memory instructions are
|
782 |
|
|
aligned to 4 or 8 bytes. */
|
783 |
|
|
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
|
784 |
|
|
(STRICT_ALIGNMENT \
|
785 |
|
|
|| (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
|
786 |
|
|
|| (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
|
787 |
|
|
|| (MODE) == DImode) \
|
788 |
|
|
&& (ALIGN) < 32) \
|
789 |
|
|
|| (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
|
790 |
|
|
|
791 |
|
|
|
792 |
|
|
/* Standard register usage. */
|
793 |
|
|
|
794 |
|
|
/* Number of actual hardware registers.
|
795 |
|
|
The hardware registers are assigned numbers for the compiler
|
796 |
|
|
from 0 to just below FIRST_PSEUDO_REGISTER.
|
797 |
|
|
All registers that the compiler knows about must be given numbers,
|
798 |
|
|
even those that are not normally considered general registers.
|
799 |
|
|
|
800 |
|
|
RS/6000 has 32 fixed-point registers, 32 floating-point registers,
|
801 |
|
|
an MQ register, a count register, a link register, and 8 condition
|
802 |
|
|
register fields, which we view here as separate registers. AltiVec
|
803 |
|
|
adds 32 vector registers and a VRsave register.
|
804 |
|
|
|
805 |
|
|
In addition, the difference between the frame and argument pointers is
|
806 |
|
|
a function of the number of registers saved, so we need to have a
|
807 |
|
|
register for AP that will later be eliminated in favor of SP or FP.
|
808 |
|
|
This is a normal register, but it is fixed.
|
809 |
|
|
|
810 |
|
|
We also create a pseudo register for float/int conversions, that will
|
811 |
|
|
really represent the memory location used. It is represented here as
|
812 |
|
|
a register, in order to work around problems in allocating stack storage
|
813 |
|
|
in inline functions.
|
814 |
|
|
|
815 |
|
|
Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
|
816 |
|
|
pointer, which is eventually eliminated in favor of SP or FP. */
|
817 |
|
|
|
818 |
|
|
#define FIRST_PSEUDO_REGISTER 114
|
819 |
|
|
|
820 |
|
|
/* This must be included for pre gcc 3.0 glibc compatibility. */
|
821 |
|
|
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
|
822 |
|
|
|
823 |
|
|
/* Add 32 dwarf columns for synthetic SPE registers. */
|
824 |
|
|
#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
|
825 |
|
|
|
826 |
|
|
/* The SPE has an additional 32 synthetic registers, with DWARF debug
|
827 |
|
|
info numbering for these registers starting at 1200. While eh_frame
|
828 |
|
|
register numbering need not be the same as the debug info numbering,
|
829 |
|
|
we choose to number these regs for eh_frame at 1200 too. This allows
|
830 |
|
|
future versions of the rs6000 backend to add hard registers and
|
831 |
|
|
continue to use the gcc hard register numbering for eh_frame. If the
|
832 |
|
|
extra SPE registers in eh_frame were numbered starting from the
|
833 |
|
|
current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
|
834 |
|
|
changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
|
835 |
|
|
avoid invalidating older SPE eh_frame info.
|
836 |
|
|
|
837 |
|
|
We must map them here to avoid huge unwinder tables mostly consisting
|
838 |
|
|
of unused space. */
|
839 |
|
|
#define DWARF_REG_TO_UNWIND_COLUMN(r) \
|
840 |
|
|
((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
|
841 |
|
|
|
842 |
|
|
/* Use standard DWARF numbering for DWARF debugging information. */
|
843 |
|
|
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
|
844 |
|
|
|
845 |
|
|
/* Use gcc hard register numbering for eh_frame. */
|
846 |
|
|
#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
|
847 |
|
|
|
848 |
|
|
/* Map register numbers held in the call frame info that gcc has
|
849 |
|
|
collected using DWARF_FRAME_REGNUM to those that should be output in
|
850 |
|
|
.debug_frame and .eh_frame. We continue to use gcc hard reg numbers
|
851 |
|
|
for .eh_frame, but use the numbers mandated by the various ABIs for
|
852 |
|
|
.debug_frame. rs6000_emit_prologue has translated any combination of
|
853 |
|
|
CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
|
854 |
|
|
the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
|
855 |
|
|
#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
|
856 |
|
|
((FOR_EH) ? (REGNO) \
|
857 |
|
|
: (REGNO) == CR2_REGNO ? 64 \
|
858 |
|
|
: DBX_REGISTER_NUMBER (REGNO))
|
859 |
|
|
|
860 |
|
|
/* 1 for registers that have pervasive standard uses
|
861 |
|
|
and are not available for the register allocator.
|
862 |
|
|
|
863 |
|
|
On RS/6000, r1 is used for the stack. On Darwin, r2 is available
|
864 |
|
|
as a local register; for all other OS's r2 is the TOC pointer.
|
865 |
|
|
|
866 |
|
|
cr5 is not supposed to be used.
|
867 |
|
|
|
868 |
|
|
On System V implementations, r13 is fixed and not available for use. */
|
869 |
|
|
|
870 |
|
|
#define FIXED_REGISTERS \
|
871 |
|
|
{0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
|
872 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
873 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
874 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
875 |
|
|
0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
|
876 |
|
|
/* AltiVec registers. */ \
|
877 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
878 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
879 |
|
|
1, 1 \
|
880 |
|
|
, 1, 1, 1 \
|
881 |
|
|
}
|
882 |
|
|
|
883 |
|
|
/* 1 for registers not available across function calls.
|
884 |
|
|
These must include the FIXED_REGISTERS and also any
|
885 |
|
|
registers that can be used without being saved.
|
886 |
|
|
The latter must include the registers where values are returned
|
887 |
|
|
and the register where structure-value addresses are passed.
|
888 |
|
|
Aside from that, you can include as many other registers as you like. */
|
889 |
|
|
|
890 |
|
|
#define CALL_USED_REGISTERS \
|
891 |
|
|
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
|
892 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
893 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
|
894 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
895 |
|
|
1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
|
896 |
|
|
/* AltiVec registers. */ \
|
897 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
898 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
899 |
|
|
1, 1 \
|
900 |
|
|
, 1, 1, 1 \
|
901 |
|
|
}
|
902 |
|
|
|
903 |
|
|
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
|
904 |
|
|
the entire set of `FIXED_REGISTERS' be included.
|
905 |
|
|
(`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
|
906 |
|
|
This macro is optional. If not specified, it defaults to the value
|
907 |
|
|
of `CALL_USED_REGISTERS'. */
|
908 |
|
|
|
909 |
|
|
#define CALL_REALLY_USED_REGISTERS \
|
910 |
|
|
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
|
911 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
912 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
|
913 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
914 |
|
|
1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
|
915 |
|
|
/* AltiVec registers. */ \
|
916 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
917 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
918 |
|
|
0, 0 \
|
919 |
|
|
, 0, 0, 0 \
|
920 |
|
|
}
|
921 |
|
|
|
922 |
|
|
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
|
923 |
|
|
|
924 |
|
|
#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
|
925 |
|
|
#define FIRST_SAVED_FP_REGNO (14+32)
|
926 |
|
|
#define FIRST_SAVED_GP_REGNO 13
|
927 |
|
|
|
928 |
|
|
/* List the order in which to allocate registers. Each register must be
|
929 |
|
|
listed once, even those in FIXED_REGISTERS.
|
930 |
|
|
|
931 |
|
|
We allocate in the following order:
|
932 |
|
|
fp0 (not saved or used for anything)
|
933 |
|
|
fp13 - fp2 (not saved; incoming fp arg registers)
|
934 |
|
|
fp1 (not saved; return value)
|
935 |
|
|
fp31 - fp14 (saved; order given to save least number)
|
936 |
|
|
cr7, cr6 (not saved or special)
|
937 |
|
|
cr1 (not saved, but used for FP operations)
|
938 |
|
|
cr0 (not saved, but used for arithmetic operations)
|
939 |
|
|
cr4, cr3, cr2 (saved)
|
940 |
|
|
r0 (not saved; cannot be base reg)
|
941 |
|
|
r9 (not saved; best for TImode)
|
942 |
|
|
r11, r10, r8-r4 (not saved; highest used first to make less conflict)
|
943 |
|
|
r3 (not saved; return value register)
|
944 |
|
|
r31 - r13 (saved; order given to save least number)
|
945 |
|
|
r12 (not saved; if used for DImode or DFmode would use r13)
|
946 |
|
|
mq (not saved; best to use it if we can)
|
947 |
|
|
ctr (not saved; when we have the choice ctr is better)
|
948 |
|
|
lr (saved)
|
949 |
|
|
cr5, r1, r2, ap, xer (fixed)
|
950 |
|
|
v0 - v1 (not saved or used for anything)
|
951 |
|
|
v13 - v3 (not saved; incoming vector arg registers)
|
952 |
|
|
v2 (not saved; incoming vector arg reg; return value)
|
953 |
|
|
v19 - v14 (not saved or used for anything)
|
954 |
|
|
v31 - v20 (saved; order given to save least number)
|
955 |
|
|
vrsave, vscr (fixed)
|
956 |
|
|
spe_acc, spefscr (fixed)
|
957 |
|
|
sfp (fixed)
|
958 |
|
|
*/
|
959 |
|
|
|
960 |
|
|
#if FIXED_R2 == 1
|
961 |
|
|
#define MAYBE_R2_AVAILABLE
|
962 |
|
|
#define MAYBE_R2_FIXED 2,
|
963 |
|
|
#else
|
964 |
|
|
#define MAYBE_R2_AVAILABLE 2,
|
965 |
|
|
#define MAYBE_R2_FIXED
|
966 |
|
|
#endif
|
967 |
|
|
|
968 |
|
|
#define REG_ALLOC_ORDER \
|
969 |
|
|
{32, \
|
970 |
|
|
45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
|
971 |
|
|
33, \
|
972 |
|
|
63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
|
973 |
|
|
50, 49, 48, 47, 46, \
|
974 |
|
|
75, 74, 69, 68, 72, 71, 70, \
|
975 |
|
|
0, MAYBE_R2_AVAILABLE \
|
976 |
|
|
9, 11, 10, 8, 7, 6, 5, 4, \
|
977 |
|
|
3, \
|
978 |
|
|
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
|
979 |
|
|
18, 17, 16, 15, 14, 13, 12, \
|
980 |
|
|
64, 66, 65, \
|
981 |
|
|
73, 1, MAYBE_R2_FIXED 67, 76, \
|
982 |
|
|
/* AltiVec registers. */ \
|
983 |
|
|
77, 78, \
|
984 |
|
|
90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
|
985 |
|
|
79, \
|
986 |
|
|
96, 95, 94, 93, 92, 91, \
|
987 |
|
|
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
|
988 |
|
|
109, 110, \
|
989 |
|
|
111, 112, 113 \
|
990 |
|
|
}
|
991 |
|
|
|
992 |
|
|
/* True if register is floating-point. */
|
993 |
|
|
#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
|
994 |
|
|
|
995 |
|
|
/* True if register is a condition register. */
|
996 |
|
|
#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
|
997 |
|
|
|
998 |
|
|
/* True if register is a condition register, but not cr0. */
|
999 |
|
|
#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
|
1000 |
|
|
|
1001 |
|
|
/* True if register is an integer register. */
|
1002 |
|
|
#define INT_REGNO_P(N) \
|
1003 |
|
|
((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
|
1004 |
|
|
|
1005 |
|
|
/* SPE SIMD registers are just the GPRs. */
|
1006 |
|
|
#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
|
1007 |
|
|
|
1008 |
|
|
/* PAIRED SIMD registers are just the FPRs. */
|
1009 |
|
|
#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
|
1010 |
|
|
|
1011 |
|
|
/* True if register is the XER register. */
|
1012 |
|
|
#define XER_REGNO_P(N) ((N) == XER_REGNO)
|
1013 |
|
|
|
1014 |
|
|
/* True if register is an AltiVec register. */
|
1015 |
|
|
#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
|
1016 |
|
|
|
1017 |
|
|
/* True if register is a VSX register. */
|
1018 |
|
|
#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
|
1019 |
|
|
|
1020 |
|
|
/* Alternate name for any vector register supporting floating point, no matter
|
1021 |
|
|
which instruction set(s) are available. */
|
1022 |
|
|
#define VFLOAT_REGNO_P(N) \
|
1023 |
|
|
(ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
|
1024 |
|
|
|
1025 |
|
|
/* Alternate name for any vector register supporting integer, no matter which
|
1026 |
|
|
instruction set(s) are available. */
|
1027 |
|
|
#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
|
1028 |
|
|
|
1029 |
|
|
/* Alternate name for any vector register supporting logical operations, no
|
1030 |
|
|
matter which instruction set(s) are available. */
|
1031 |
|
|
#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
|
1032 |
|
|
|
1033 |
|
|
/* Return number of consecutive hard regs needed starting at reg REGNO
|
1034 |
|
|
to hold something of mode MODE. */
|
1035 |
|
|
|
1036 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
|
1037 |
|
|
|
1038 |
|
|
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
|
1039 |
|
|
(((TARGET_32BIT && TARGET_POWERPC64 \
|
1040 |
|
|
&& (GET_MODE_SIZE (MODE) > 4) \
|
1041 |
|
|
&& INT_REGNO_P (REGNO)) ? 1 : 0) \
|
1042 |
|
|
|| (TARGET_VSX && FP_REGNO_P (REGNO) \
|
1043 |
|
|
&& GET_MODE_SIZE (MODE) > 8))
|
1044 |
|
|
|
1045 |
|
|
#define VSX_VECTOR_MODE(MODE) \
|
1046 |
|
|
((MODE) == V4SFmode \
|
1047 |
|
|
|| (MODE) == V2DFmode) \
|
1048 |
|
|
|
1049 |
|
|
#define VSX_SCALAR_MODE(MODE) \
|
1050 |
|
|
((MODE) == DFmode)
|
1051 |
|
|
|
1052 |
|
|
#define VSX_MODE(MODE) \
|
1053 |
|
|
(VSX_VECTOR_MODE (MODE) \
|
1054 |
|
|
|| VSX_SCALAR_MODE (MODE))
|
1055 |
|
|
|
1056 |
|
|
#define VSX_MOVE_MODE(MODE) \
|
1057 |
|
|
(VSX_VECTOR_MODE (MODE) \
|
1058 |
|
|
|| VSX_SCALAR_MODE (MODE) \
|
1059 |
|
|
|| ALTIVEC_VECTOR_MODE (MODE) \
|
1060 |
|
|
|| (MODE) == TImode)
|
1061 |
|
|
|
1062 |
|
|
#define ALTIVEC_VECTOR_MODE(MODE) \
|
1063 |
|
|
((MODE) == V16QImode \
|
1064 |
|
|
|| (MODE) == V8HImode \
|
1065 |
|
|
|| (MODE) == V4SFmode \
|
1066 |
|
|
|| (MODE) == V4SImode)
|
1067 |
|
|
|
1068 |
|
|
#define SPE_VECTOR_MODE(MODE) \
|
1069 |
|
|
((MODE) == V4HImode \
|
1070 |
|
|
|| (MODE) == V2SFmode \
|
1071 |
|
|
|| (MODE) == V1DImode \
|
1072 |
|
|
|| (MODE) == V2SImode)
|
1073 |
|
|
|
1074 |
|
|
#define PAIRED_VECTOR_MODE(MODE) \
|
1075 |
|
|
((MODE) == V2SFmode)
|
1076 |
|
|
|
1077 |
|
|
#define UNITS_PER_SIMD_WORD(MODE) \
|
1078 |
|
|
(TARGET_VSX ? UNITS_PER_VSX_WORD \
|
1079 |
|
|
: (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
|
1080 |
|
|
: (TARGET_SPE ? UNITS_PER_SPE_WORD \
|
1081 |
|
|
: (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \
|
1082 |
|
|
: UNITS_PER_WORD))))
|
1083 |
|
|
|
1084 |
|
|
/* Value is TRUE if hard register REGNO can hold a value of
|
1085 |
|
|
machine-mode MODE. */
|
1086 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
1087 |
|
|
rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
|
1088 |
|
|
|
1089 |
|
|
/* Value is 1 if it is a good idea to tie two pseudo registers
|
1090 |
|
|
when one has mode MODE1 and one has mode MODE2.
|
1091 |
|
|
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
|
1092 |
|
|
for any hard reg, then this must be 0 for correct output. */
|
1093 |
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
1094 |
|
|
(SCALAR_FLOAT_MODE_P (MODE1) \
|
1095 |
|
|
? SCALAR_FLOAT_MODE_P (MODE2) \
|
1096 |
|
|
: SCALAR_FLOAT_MODE_P (MODE2) \
|
1097 |
|
|
? SCALAR_FLOAT_MODE_P (MODE1) \
|
1098 |
|
|
: GET_MODE_CLASS (MODE1) == MODE_CC \
|
1099 |
|
|
? GET_MODE_CLASS (MODE2) == MODE_CC \
|
1100 |
|
|
: GET_MODE_CLASS (MODE2) == MODE_CC \
|
1101 |
|
|
? GET_MODE_CLASS (MODE1) == MODE_CC \
|
1102 |
|
|
: SPE_VECTOR_MODE (MODE1) \
|
1103 |
|
|
? SPE_VECTOR_MODE (MODE2) \
|
1104 |
|
|
: SPE_VECTOR_MODE (MODE2) \
|
1105 |
|
|
? SPE_VECTOR_MODE (MODE1) \
|
1106 |
|
|
: ALTIVEC_VECTOR_MODE (MODE1) \
|
1107 |
|
|
? ALTIVEC_VECTOR_MODE (MODE2) \
|
1108 |
|
|
: ALTIVEC_VECTOR_MODE (MODE2) \
|
1109 |
|
|
? ALTIVEC_VECTOR_MODE (MODE1) \
|
1110 |
|
|
: VSX_VECTOR_MODE (MODE1) \
|
1111 |
|
|
? VSX_VECTOR_MODE (MODE2) \
|
1112 |
|
|
: VSX_VECTOR_MODE (MODE2) \
|
1113 |
|
|
? VSX_VECTOR_MODE (MODE1) \
|
1114 |
|
|
: 1)
|
1115 |
|
|
|
1116 |
|
|
/* Post-reload, we can't use any new AltiVec registers, as we already
|
1117 |
|
|
emitted the vrsave mask. */
|
1118 |
|
|
|
1119 |
|
|
#define HARD_REGNO_RENAME_OK(SRC, DST) \
|
1120 |
|
|
(! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
|
1121 |
|
|
|
1122 |
|
|
/* A C expression returning the cost of moving data from a register of class
|
1123 |
|
|
CLASS1 to one of CLASS2. */
|
1124 |
|
|
|
1125 |
|
|
#define REGISTER_MOVE_COST rs6000_register_move_cost
|
1126 |
|
|
|
1127 |
|
|
/* A C expressions returning the cost of moving data of MODE from a register to
|
1128 |
|
|
or from memory. */
|
1129 |
|
|
|
1130 |
|
|
#define MEMORY_MOVE_COST rs6000_memory_move_cost
|
1131 |
|
|
|
1132 |
|
|
/* Specify the cost of a branch insn; roughly the number of extra insns that
|
1133 |
|
|
should be added to avoid a branch.
|
1134 |
|
|
|
1135 |
|
|
Set this to 3 on the RS/6000 since that is roughly the average cost of an
|
1136 |
|
|
unscheduled conditional branch. */
|
1137 |
|
|
|
1138 |
|
|
#define BRANCH_COST(speed_p, predictable_p) 3
|
1139 |
|
|
|
1140 |
|
|
/* Override BRANCH_COST heuristic which empirically produces worse
|
1141 |
|
|
performance for removing short circuiting from the logical ops. */
|
1142 |
|
|
|
1143 |
|
|
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
|
1144 |
|
|
|
1145 |
|
|
/* A fixed register used at epilogue generation to address SPE registers
|
1146 |
|
|
with negative offsets. The 64-bit load/store instructions on the SPE
|
1147 |
|
|
only take positive offsets (and small ones at that), so we need to
|
1148 |
|
|
reserve a register for consing up negative offsets. */
|
1149 |
|
|
|
1150 |
|
|
#define FIXED_SCRATCH 0
|
1151 |
|
|
|
1152 |
|
|
/* Define this macro to change register usage conditional on target
|
1153 |
|
|
flags. */
|
1154 |
|
|
|
1155 |
|
|
#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
|
1156 |
|
|
|
1157 |
|
|
/* Specify the registers used for certain standard purposes.
|
1158 |
|
|
The values of these macros are register numbers. */
|
1159 |
|
|
|
1160 |
|
|
/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
|
1161 |
|
|
/* #define PC_REGNUM */
|
1162 |
|
|
|
1163 |
|
|
/* Register to use for pushing function arguments. */
|
1164 |
|
|
#define STACK_POINTER_REGNUM 1
|
1165 |
|
|
|
1166 |
|
|
/* Base register for access to local variables of the function. */
|
1167 |
|
|
#define HARD_FRAME_POINTER_REGNUM 31
|
1168 |
|
|
|
1169 |
|
|
/* Base register for access to local variables of the function. */
|
1170 |
|
|
#define FRAME_POINTER_REGNUM 113
|
1171 |
|
|
|
1172 |
|
|
/* Base register for access to arguments of the function. */
|
1173 |
|
|
#define ARG_POINTER_REGNUM 67
|
1174 |
|
|
|
1175 |
|
|
/* Place to put static chain when calling a function that requires it. */
|
1176 |
|
|
#define STATIC_CHAIN_REGNUM 11
|
1177 |
|
|
|
1178 |
|
|
|
1179 |
|
|
/* Define the classes of registers for register constraints in the
|
1180 |
|
|
machine description. Also define ranges of constants.
|
1181 |
|
|
|
1182 |
|
|
One of the classes must always be named ALL_REGS and include all hard regs.
|
1183 |
|
|
If there is more than one class, another class must be named NO_REGS
|
1184 |
|
|
and contain no registers.
|
1185 |
|
|
|
1186 |
|
|
The name GENERAL_REGS must be the name of a class (or an alias for
|
1187 |
|
|
another name such as ALL_REGS). This is the class of registers
|
1188 |
|
|
that is allowed by "g" or "r" in a register constraint.
|
1189 |
|
|
Also, registers outside this class are allocated only when
|
1190 |
|
|
instructions express preferences for them.
|
1191 |
|
|
|
1192 |
|
|
The classes must be numbered in nondecreasing order; that is,
|
1193 |
|
|
a larger-numbered class must never be contained completely
|
1194 |
|
|
in a smaller-numbered class.
|
1195 |
|
|
|
1196 |
|
|
For any two classes, it is very desirable that there be another
|
1197 |
|
|
class that represents their union. */
|
1198 |
|
|
|
1199 |
|
|
/* The RS/6000 has three types of registers, fixed-point, floating-point, and
|
1200 |
|
|
condition registers, plus three special registers, MQ, CTR, and the link
|
1201 |
|
|
register. AltiVec adds a vector register class. VSX registers overlap the
|
1202 |
|
|
FPR registers and the Altivec registers.
|
1203 |
|
|
|
1204 |
|
|
However, r0 is special in that it cannot be used as a base register.
|
1205 |
|
|
So make a class for registers valid as base registers.
|
1206 |
|
|
|
1207 |
|
|
Also, cr0 is the only condition code register that can be used in
|
1208 |
|
|
arithmetic insns, so make a separate class for it. */
|
1209 |
|
|
|
1210 |
|
|
enum reg_class
|
1211 |
|
|
{
|
1212 |
|
|
NO_REGS,
|
1213 |
|
|
BASE_REGS,
|
1214 |
|
|
GENERAL_REGS,
|
1215 |
|
|
FLOAT_REGS,
|
1216 |
|
|
ALTIVEC_REGS,
|
1217 |
|
|
VSX_REGS,
|
1218 |
|
|
VRSAVE_REGS,
|
1219 |
|
|
VSCR_REGS,
|
1220 |
|
|
SPE_ACC_REGS,
|
1221 |
|
|
SPEFSCR_REGS,
|
1222 |
|
|
NON_SPECIAL_REGS,
|
1223 |
|
|
MQ_REGS,
|
1224 |
|
|
LINK_REGS,
|
1225 |
|
|
CTR_REGS,
|
1226 |
|
|
LINK_OR_CTR_REGS,
|
1227 |
|
|
SPECIAL_REGS,
|
1228 |
|
|
SPEC_OR_GEN_REGS,
|
1229 |
|
|
CR0_REGS,
|
1230 |
|
|
CR_REGS,
|
1231 |
|
|
NON_FLOAT_REGS,
|
1232 |
|
|
XER_REGS,
|
1233 |
|
|
ALL_REGS,
|
1234 |
|
|
LIM_REG_CLASSES
|
1235 |
|
|
};
|
1236 |
|
|
|
1237 |
|
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
1238 |
|
|
|
1239 |
|
|
/* Give names of register classes as strings for dump file. */
|
1240 |
|
|
|
1241 |
|
|
#define REG_CLASS_NAMES \
|
1242 |
|
|
{ \
|
1243 |
|
|
"NO_REGS", \
|
1244 |
|
|
"BASE_REGS", \
|
1245 |
|
|
"GENERAL_REGS", \
|
1246 |
|
|
"FLOAT_REGS", \
|
1247 |
|
|
"ALTIVEC_REGS", \
|
1248 |
|
|
"VSX_REGS", \
|
1249 |
|
|
"VRSAVE_REGS", \
|
1250 |
|
|
"VSCR_REGS", \
|
1251 |
|
|
"SPE_ACC_REGS", \
|
1252 |
|
|
"SPEFSCR_REGS", \
|
1253 |
|
|
"NON_SPECIAL_REGS", \
|
1254 |
|
|
"MQ_REGS", \
|
1255 |
|
|
"LINK_REGS", \
|
1256 |
|
|
"CTR_REGS", \
|
1257 |
|
|
"LINK_OR_CTR_REGS", \
|
1258 |
|
|
"SPECIAL_REGS", \
|
1259 |
|
|
"SPEC_OR_GEN_REGS", \
|
1260 |
|
|
"CR0_REGS", \
|
1261 |
|
|
"CR_REGS", \
|
1262 |
|
|
"NON_FLOAT_REGS", \
|
1263 |
|
|
"XER_REGS", \
|
1264 |
|
|
"ALL_REGS" \
|
1265 |
|
|
}
|
1266 |
|
|
|
1267 |
|
|
/* Define which registers fit in which classes.
|
1268 |
|
|
This is an initializer for a vector of HARD_REG_SET
|
1269 |
|
|
of length N_REG_CLASSES. */
|
1270 |
|
|
|
1271 |
|
|
#define REG_CLASS_CONTENTS \
|
1272 |
|
|
{ \
|
1273 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
|
1274 |
|
|
{ 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
|
1275 |
|
|
{ 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
|
1276 |
|
|
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
|
1277 |
|
|
{ 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
|
1278 |
|
|
{ 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
|
1279 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
|
1280 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
|
1281 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
|
1282 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
|
1283 |
|
|
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
|
1284 |
|
|
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
|
1285 |
|
|
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
|
1286 |
|
|
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
|
1287 |
|
|
{ 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
|
1288 |
|
|
{ 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
|
1289 |
|
|
{ 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
|
1290 |
|
|
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
|
1291 |
|
|
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
|
1292 |
|
|
{ 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
|
1293 |
|
|
{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
|
1294 |
|
|
{ 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
|
1295 |
|
|
}
|
1296 |
|
|
|
1297 |
|
|
/* The following macro defines cover classes for Integrated Register
|
1298 |
|
|
Allocator. Cover classes is a set of non-intersected register
|
1299 |
|
|
classes covering all hard registers used for register allocation
|
1300 |
|
|
purpose. Any move between two registers of a cover class should be
|
1301 |
|
|
cheaper than load or store of the registers. The macro value is
|
1302 |
|
|
array of register classes with LIM_REG_CLASSES used as the end
|
1303 |
|
|
marker.
|
1304 |
|
|
|
1305 |
|
|
We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to
|
1306 |
|
|
account for the Altivec and Floating registers being subsets of the VSX
|
1307 |
|
|
register set. */
|
1308 |
|
|
|
1309 |
|
|
#define IRA_COVER_CLASSES_PRE_VSX \
|
1310 |
|
|
{ \
|
1311 |
|
|
GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \
|
1312 |
|
|
/* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
|
1313 |
|
|
/* MQ_REGS, LINK_REGS, CTR_REGS, */ \
|
1314 |
|
|
CR_REGS, XER_REGS, LIM_REG_CLASSES \
|
1315 |
|
|
}
|
1316 |
|
|
|
1317 |
|
|
#define IRA_COVER_CLASSES_VSX \
|
1318 |
|
|
{ \
|
1319 |
|
|
GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \
|
1320 |
|
|
/* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
|
1321 |
|
|
/* MQ_REGS, LINK_REGS, CTR_REGS, */ \
|
1322 |
|
|
CR_REGS, XER_REGS, LIM_REG_CLASSES \
|
1323 |
|
|
}
|
1324 |
|
|
|
1325 |
|
|
/* The same information, inverted:
|
1326 |
|
|
Return the class number of the smallest class containing
|
1327 |
|
|
reg number REGNO. This could be a conditional expression
|
1328 |
|
|
or could index an array. */
|
1329 |
|
|
|
1330 |
|
|
extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
|
1331 |
|
|
|
1332 |
|
|
#if ENABLE_CHECKING
|
1333 |
|
|
#define REGNO_REG_CLASS(REGNO) \
|
1334 |
|
|
(gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
|
1335 |
|
|
rs6000_regno_regclass[(REGNO)])
|
1336 |
|
|
|
1337 |
|
|
#else
|
1338 |
|
|
#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
|
1339 |
|
|
#endif
|
1340 |
|
|
|
1341 |
|
|
/* Register classes for various constraints that are based on the target
|
1342 |
|
|
switches. */
|
1343 |
|
|
enum r6000_reg_class_enum {
|
1344 |
|
|
RS6000_CONSTRAINT_d, /* fpr registers for double values */
|
1345 |
|
|
RS6000_CONSTRAINT_f, /* fpr registers for single values */
|
1346 |
|
|
RS6000_CONSTRAINT_v, /* Altivec registers */
|
1347 |
|
|
RS6000_CONSTRAINT_wa, /* Any VSX register */
|
1348 |
|
|
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
|
1349 |
|
|
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
|
1350 |
|
|
RS6000_CONSTRAINT_ws, /* VSX register for DF */
|
1351 |
|
|
RS6000_CONSTRAINT_MAX
|
1352 |
|
|
};
|
1353 |
|
|
|
1354 |
|
|
extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
|
1355 |
|
|
|
1356 |
|
|
/* The class value for index registers, and the one for base regs. */
|
1357 |
|
|
#define INDEX_REG_CLASS GENERAL_REGS
|
1358 |
|
|
#define BASE_REG_CLASS BASE_REGS
|
1359 |
|
|
|
1360 |
|
|
/* Return whether a given register class can hold VSX objects. */
|
1361 |
|
|
#define VSX_REG_CLASS_P(CLASS) \
|
1362 |
|
|
((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
|
1363 |
|
|
|
1364 |
|
|
/* Given an rtx X being reloaded into a reg required to be
|
1365 |
|
|
in class CLASS, return the class of reg to actually use.
|
1366 |
|
|
In general this is just CLASS; but on some machines
|
1367 |
|
|
in some cases it is preferable to use a more restrictive class.
|
1368 |
|
|
|
1369 |
|
|
On the RS/6000, we have to return NO_REGS when we want to reload a
|
1370 |
|
|
floating-point CONST_DOUBLE to force it to be copied to memory.
|
1371 |
|
|
|
1372 |
|
|
We also don't want to reload integer values into floating-point
|
1373 |
|
|
registers if we can at all help it. In fact, this can
|
1374 |
|
|
cause reload to die, if it tries to generate a reload of CTR
|
1375 |
|
|
into a FP register and discovers it doesn't have the memory location
|
1376 |
|
|
required.
|
1377 |
|
|
|
1378 |
|
|
??? Would it be a good idea to have reload do the converse, that is
|
1379 |
|
|
try to reload floating modes into FP registers if possible?
|
1380 |
|
|
*/
|
1381 |
|
|
|
1382 |
|
|
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
|
1383 |
|
|
rs6000_preferred_reload_class_ptr (X, CLASS)
|
1384 |
|
|
|
1385 |
|
|
/* Return the register class of a scratch register needed to copy IN into
|
1386 |
|
|
or out of a register in CLASS in MODE. If it can be done directly,
|
1387 |
|
|
NO_REGS is returned. */
|
1388 |
|
|
|
1389 |
|
|
#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
|
1390 |
|
|
rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
|
1391 |
|
|
|
1392 |
|
|
/* If we are copying between FP or AltiVec registers and anything
|
1393 |
|
|
else, we need a memory location. The exception is when we are
|
1394 |
|
|
targeting ppc64 and the move to/from fpr to gpr instructions
|
1395 |
|
|
are available.*/
|
1396 |
|
|
|
1397 |
|
|
#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
|
1398 |
|
|
rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
|
1399 |
|
|
|
1400 |
|
|
/* For cpus that cannot load/store SDmode values from the 64-bit
|
1401 |
|
|
FP registers without using a full 64-bit load/store, we need
|
1402 |
|
|
to allocate a full 64-bit stack slot for them. */
|
1403 |
|
|
|
1404 |
|
|
#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
|
1405 |
|
|
rs6000_secondary_memory_needed_rtx (MODE)
|
1406 |
|
|
|
1407 |
|
|
/* Return the maximum number of consecutive registers
|
1408 |
|
|
needed to represent mode MODE in a register of class CLASS.
|
1409 |
|
|
|
1410 |
|
|
On RS/6000, this is the size of MODE in words, except in the FP regs, where
|
1411 |
|
|
a single reg is enough for two words, unless we have VSX, where the FP
|
1412 |
|
|
registers can hold 128 bits. */
|
1413 |
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
|
1414 |
|
|
|
1415 |
|
|
/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
|
1416 |
|
|
|
1417 |
|
|
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
|
1418 |
|
|
rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
|
1419 |
|
|
|
1420 |
|
|
/* Stack layout; function entry, exit and calling. */
|
1421 |
|
|
|
1422 |
|
|
/* Enumeration to give which calling sequence to use. */
|
1423 |
|
|
enum rs6000_abi {
|
1424 |
|
|
ABI_NONE,
|
1425 |
|
|
ABI_AIX, /* IBM's AIX */
|
1426 |
|
|
ABI_V4, /* System V.4/eabi */
|
1427 |
|
|
ABI_DARWIN /* Apple's Darwin (OS X kernel) */
|
1428 |
|
|
};
|
1429 |
|
|
|
1430 |
|
|
extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
|
1431 |
|
|
|
1432 |
|
|
/* Define this if pushing a word on the stack
|
1433 |
|
|
makes the stack pointer a smaller address. */
|
1434 |
|
|
#define STACK_GROWS_DOWNWARD
|
1435 |
|
|
|
1436 |
|
|
/* Offsets recorded in opcodes are a multiple of this alignment factor. */
|
1437 |
|
|
#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
|
1438 |
|
|
|
1439 |
|
|
/* Define this to nonzero if the nominal address of the stack frame
|
1440 |
|
|
is at the high-address end of the local variables;
|
1441 |
|
|
that is, each additional local variable allocated
|
1442 |
|
|
goes at a more negative offset in the frame.
|
1443 |
|
|
|
1444 |
|
|
On the RS/6000, we grow upwards, from the area after the outgoing
|
1445 |
|
|
arguments. */
|
1446 |
|
|
#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
|
1447 |
|
|
|
1448 |
|
|
/* Size of the outgoing register save area */
|
1449 |
|
|
#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
|
1450 |
|
|
|| DEFAULT_ABI == ABI_DARWIN) \
|
1451 |
|
|
? (TARGET_64BIT ? 64 : 32) \
|
1452 |
|
|
: 0)
|
1453 |
|
|
|
1454 |
|
|
/* Size of the fixed area on the stack */
|
1455 |
|
|
#define RS6000_SAVE_AREA \
|
1456 |
|
|
(((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
|
1457 |
|
|
<< (TARGET_64BIT ? 1 : 0))
|
1458 |
|
|
|
1459 |
|
|
/* MEM representing address to save the TOC register */
|
1460 |
|
|
#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
|
1461 |
|
|
plus_constant (stack_pointer_rtx, \
|
1462 |
|
|
(TARGET_32BIT ? 20 : 40)))
|
1463 |
|
|
|
1464 |
|
|
/* Align an address */
|
1465 |
|
|
#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
|
1466 |
|
|
|
1467 |
|
|
/* Offset within stack frame to start allocating local variables at.
|
1468 |
|
|
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
|
1469 |
|
|
first local allocated. Otherwise, it is the offset to the BEGINNING
|
1470 |
|
|
of the first local allocated.
|
1471 |
|
|
|
1472 |
|
|
On the RS/6000, the frame pointer is the same as the stack pointer,
|
1473 |
|
|
except for dynamic allocations. So we start after the fixed area and
|
1474 |
|
|
outgoing parameter area. */
|
1475 |
|
|
|
1476 |
|
|
#define STARTING_FRAME_OFFSET \
|
1477 |
|
|
(FRAME_GROWS_DOWNWARD \
|
1478 |
|
|
? 0 \
|
1479 |
|
|
: (RS6000_ALIGN (crtl->outgoing_args_size, \
|
1480 |
|
|
(TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
|
1481 |
|
|
+ RS6000_SAVE_AREA))
|
1482 |
|
|
|
1483 |
|
|
/* Offset from the stack pointer register to an item dynamically
|
1484 |
|
|
allocated on the stack, e.g., by `alloca'.
|
1485 |
|
|
|
1486 |
|
|
The default value for this macro is `STACK_POINTER_OFFSET' plus the
|
1487 |
|
|
length of the outgoing arguments. The default is correct for most
|
1488 |
|
|
machines. See `function.c' for details. */
|
1489 |
|
|
#define STACK_DYNAMIC_OFFSET(FUNDECL) \
|
1490 |
|
|
(RS6000_ALIGN (crtl->outgoing_args_size, \
|
1491 |
|
|
(TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
|
1492 |
|
|
+ (STACK_POINTER_OFFSET))
|
1493 |
|
|
|
1494 |
|
|
/* If we generate an insn to push BYTES bytes,
|
1495 |
|
|
this says how many the stack pointer really advances by.
|
1496 |
|
|
On RS/6000, don't define this because there are no push insns. */
|
1497 |
|
|
/* #define PUSH_ROUNDING(BYTES) */
|
1498 |
|
|
|
1499 |
|
|
/* Offset of first parameter from the argument pointer register value.
|
1500 |
|
|
On the RS/6000, we define the argument pointer to the start of the fixed
|
1501 |
|
|
area. */
|
1502 |
|
|
#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
|
1503 |
|
|
|
1504 |
|
|
/* Offset from the argument pointer register value to the top of
|
1505 |
|
|
stack. This is different from FIRST_PARM_OFFSET because of the
|
1506 |
|
|
register save area. */
|
1507 |
|
|
#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
|
1508 |
|
|
|
1509 |
|
|
/* Define this if stack space is still allocated for a parameter passed
|
1510 |
|
|
in a register. The value is the number of bytes allocated to this
|
1511 |
|
|
area. */
|
1512 |
|
|
#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
|
1513 |
|
|
|
1514 |
|
|
/* Define this if the above stack space is to be considered part of the
|
1515 |
|
|
space allocated by the caller. */
|
1516 |
|
|
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
|
1517 |
|
|
|
1518 |
|
|
/* This is the difference between the logical top of stack and the actual sp.
|
1519 |
|
|
|
1520 |
|
|
For the RS/6000, sp points past the fixed area. */
|
1521 |
|
|
#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
|
1522 |
|
|
|
1523 |
|
|
/* Define this if the maximum size of all the outgoing args is to be
|
1524 |
|
|
accumulated and pushed during the prologue. The amount can be
|
1525 |
|
|
found in the variable crtl->outgoing_args_size. */
|
1526 |
|
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
1527 |
|
|
|
1528 |
|
|
/* Value is the number of bytes of arguments automatically
|
1529 |
|
|
popped when returning from a subroutine call.
|
1530 |
|
|
FUNDECL is the declaration node of the function (as a tree),
|
1531 |
|
|
FUNTYPE is the data type of the function (as a tree),
|
1532 |
|
|
or for a library call it is an identifier node for the subroutine name.
|
1533 |
|
|
SIZE is the number of bytes of arguments passed on the stack. */
|
1534 |
|
|
|
1535 |
|
|
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
|
1536 |
|
|
|
1537 |
|
|
/* Define how to find the value returned by a library function
|
1538 |
|
|
assuming the value has mode MODE. */
|
1539 |
|
|
|
1540 |
|
|
#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
|
1541 |
|
|
|
1542 |
|
|
/* DRAFT_V4_STRUCT_RET defaults off. */
|
1543 |
|
|
#define DRAFT_V4_STRUCT_RET 0
|
1544 |
|
|
|
1545 |
|
|
/* Let TARGET_RETURN_IN_MEMORY control what happens. */
|
1546 |
|
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
1547 |
|
|
|
1548 |
|
|
/* Mode of stack savearea.
|
1549 |
|
|
FUNCTION is VOIDmode because calling convention maintains SP.
|
1550 |
|
|
BLOCK needs Pmode for SP.
|
1551 |
|
|
NONLOCAL needs twice Pmode to maintain both backchain and SP. */
|
1552 |
|
|
#define STACK_SAVEAREA_MODE(LEVEL) \
|
1553 |
|
|
(LEVEL == SAVE_FUNCTION ? VOIDmode \
|
1554 |
|
|
: LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
|
1555 |
|
|
|
1556 |
|
|
/* Minimum and maximum general purpose registers used to hold arguments. */
|
1557 |
|
|
#define GP_ARG_MIN_REG 3
|
1558 |
|
|
#define GP_ARG_MAX_REG 10
|
1559 |
|
|
#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
|
1560 |
|
|
|
1561 |
|
|
/* Minimum and maximum floating point registers used to hold arguments. */
|
1562 |
|
|
#define FP_ARG_MIN_REG 33
|
1563 |
|
|
#define FP_ARG_AIX_MAX_REG 45
|
1564 |
|
|
#define FP_ARG_V4_MAX_REG 40
|
1565 |
|
|
#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
|
1566 |
|
|
|| DEFAULT_ABI == ABI_DARWIN) \
|
1567 |
|
|
? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
|
1568 |
|
|
#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
|
1569 |
|
|
|
1570 |
|
|
/* Minimum and maximum AltiVec registers used to hold arguments. */
|
1571 |
|
|
#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
|
1572 |
|
|
#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
|
1573 |
|
|
#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
|
1574 |
|
|
|
1575 |
|
|
/* Return registers */
|
1576 |
|
|
#define GP_ARG_RETURN GP_ARG_MIN_REG
|
1577 |
|
|
#define FP_ARG_RETURN FP_ARG_MIN_REG
|
1578 |
|
|
#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
|
1579 |
|
|
|
1580 |
|
|
/* Flags for the call/call_value rtl operations set up by function_arg */
|
1581 |
|
|
#define CALL_NORMAL 0x00000000 /* no special processing */
|
1582 |
|
|
/* Bits in 0x00000001 are unused. */
|
1583 |
|
|
#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
|
1584 |
|
|
#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
|
1585 |
|
|
#define CALL_LONG 0x00000008 /* always call indirect */
|
1586 |
|
|
#define CALL_LIBCALL 0x00000010 /* libcall */
|
1587 |
|
|
|
1588 |
|
|
/* We don't have prologue and epilogue functions to save/restore
|
1589 |
|
|
everything for most ABIs. */
|
1590 |
|
|
#define WORLD_SAVE_P(INFO) 0
|
1591 |
|
|
|
1592 |
|
|
/* 1 if N is a possible register number for a function value
|
1593 |
|
|
as seen by the caller.
|
1594 |
|
|
|
1595 |
|
|
On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
|
1596 |
|
|
#define FUNCTION_VALUE_REGNO_P(N) \
|
1597 |
|
|
((N) == GP_ARG_RETURN \
|
1598 |
|
|
|| ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
|
1599 |
|
|
|| ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
|
1600 |
|
|
|
1601 |
|
|
/* 1 if N is a possible register number for function argument passing.
|
1602 |
|
|
On RS/6000, these are r3-r10 and fp1-fp13.
|
1603 |
|
|
On AltiVec, v2 - v13 are used for passing vectors. */
|
1604 |
|
|
#define FUNCTION_ARG_REGNO_P(N) \
|
1605 |
|
|
((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
|
1606 |
|
|
|| ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
|
1607 |
|
|
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
|
1608 |
|
|
|| ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
|
1609 |
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS))
|
1610 |
|
|
|
1611 |
|
|
/* Define a data type for recording info about an argument list
|
1612 |
|
|
during the scan of that argument list. This data type should
|
1613 |
|
|
hold all necessary information about the function itself
|
1614 |
|
|
and about the args processed so far, enough to enable macros
|
1615 |
|
|
such as FUNCTION_ARG to determine where the next arg should go.
|
1616 |
|
|
|
1617 |
|
|
On the RS/6000, this is a structure. The first element is the number of
|
1618 |
|
|
total argument words, the second is used to store the next
|
1619 |
|
|
floating-point register number, and the third says how many more args we
|
1620 |
|
|
have prototype types for.
|
1621 |
|
|
|
1622 |
|
|
For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
|
1623 |
|
|
the next available GP register, `fregno' is the next available FP
|
1624 |
|
|
register, and `words' is the number of words used on the stack.
|
1625 |
|
|
|
1626 |
|
|
The varargs/stdarg support requires that this structure's size
|
1627 |
|
|
be a multiple of sizeof(int). */
|
1628 |
|
|
|
1629 |
|
|
typedef struct rs6000_args
|
1630 |
|
|
{
|
1631 |
|
|
int words; /* # words used for passing GP registers */
|
1632 |
|
|
int fregno; /* next available FP register */
|
1633 |
|
|
int vregno; /* next available AltiVec register */
|
1634 |
|
|
int nargs_prototype; /* # args left in the current prototype */
|
1635 |
|
|
int prototype; /* Whether a prototype was defined */
|
1636 |
|
|
int stdarg; /* Whether function is a stdarg function. */
|
1637 |
|
|
int call_cookie; /* Do special things for this call */
|
1638 |
|
|
int sysv_gregno; /* next available GP register */
|
1639 |
|
|
int intoffset; /* running offset in struct (darwin64) */
|
1640 |
|
|
int use_stack; /* any part of struct on stack (darwin64) */
|
1641 |
|
|
int named; /* false for varargs params */
|
1642 |
|
|
} CUMULATIVE_ARGS;
|
1643 |
|
|
|
1644 |
|
|
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
1645 |
|
|
for a call to a function whose data type is FNTYPE.
|
1646 |
|
|
For a library call, FNTYPE is 0. */
|
1647 |
|
|
|
1648 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
1649 |
|
|
init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
|
1650 |
|
|
|
1651 |
|
|
/* Similar, but when scanning the definition of a procedure. We always
|
1652 |
|
|
set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
|
1653 |
|
|
|
1654 |
|
|
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
|
1655 |
|
|
init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
|
1656 |
|
|
|
1657 |
|
|
/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
|
1658 |
|
|
|
1659 |
|
|
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
|
1660 |
|
|
init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
|
1661 |
|
|
|
1662 |
|
|
/* Update the data in CUM to advance over an argument
|
1663 |
|
|
of mode MODE and data type TYPE.
|
1664 |
|
|
(TYPE is null for libcalls where that information may not be available.) */
|
1665 |
|
|
|
1666 |
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
1667 |
|
|
function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
|
1668 |
|
|
|
1669 |
|
|
/* Determine where to put an argument to a function.
|
1670 |
|
|
Value is zero to push the argument on the stack,
|
1671 |
|
|
or a hard register in which to store the argument.
|
1672 |
|
|
|
1673 |
|
|
MODE is the argument's machine mode.
|
1674 |
|
|
TYPE is the data type of the argument (as a tree).
|
1675 |
|
|
This is null for libcalls where that information may
|
1676 |
|
|
not be available.
|
1677 |
|
|
CUM is a variable of type CUMULATIVE_ARGS which gives info about
|
1678 |
|
|
the preceding args and about the function being called.
|
1679 |
|
|
NAMED is nonzero if this argument is a named parameter
|
1680 |
|
|
(otherwise it is an extra parameter matching an ellipsis).
|
1681 |
|
|
|
1682 |
|
|
On RS/6000 the first eight words of non-FP are normally in registers
|
1683 |
|
|
and the rest are pushed. The first 13 FP args are in registers.
|
1684 |
|
|
|
1685 |
|
|
If this is floating-point and no prototype is specified, we use
|
1686 |
|
|
both an FP and integer register (or possibly FP reg and stack). Library
|
1687 |
|
|
functions (when TYPE is zero) always have the proper types for args,
|
1688 |
|
|
so we can pass the FP value just in one register. emit_library_function
|
1689 |
|
|
doesn't support EXPR_LIST anyway. */
|
1690 |
|
|
|
1691 |
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
1692 |
|
|
function_arg (&CUM, MODE, TYPE, NAMED)
|
1693 |
|
|
|
1694 |
|
|
/* If defined, a C expression which determines whether, and in which
|
1695 |
|
|
direction, to pad out an argument with extra space. The value
|
1696 |
|
|
should be of type `enum direction': either `upward' to pad above
|
1697 |
|
|
the argument, `downward' to pad below, or `none' to inhibit
|
1698 |
|
|
padding. */
|
1699 |
|
|
|
1700 |
|
|
#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
|
1701 |
|
|
|
1702 |
|
|
/* If defined, a C expression that gives the alignment boundary, in bits,
|
1703 |
|
|
of an argument with the specified mode and type. If it is not defined,
|
1704 |
|
|
PARM_BOUNDARY is used for all arguments. */
|
1705 |
|
|
|
1706 |
|
|
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
|
1707 |
|
|
function_arg_boundary (MODE, TYPE)
|
1708 |
|
|
|
1709 |
|
|
#define PAD_VARARGS_DOWN \
|
1710 |
|
|
(FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
|
1711 |
|
|
|
1712 |
|
|
/* Output assembler code to FILE to increment profiler label # LABELNO
|
1713 |
|
|
for profiling a function entry. */
|
1714 |
|
|
|
1715 |
|
|
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
1716 |
|
|
output_function_profiler ((FILE), (LABELNO));
|
1717 |
|
|
|
1718 |
|
|
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
1719 |
|
|
the stack pointer does not matter. No definition is equivalent to
|
1720 |
|
|
always zero.
|
1721 |
|
|
|
1722 |
|
|
On the RS/6000, this is nonzero because we can restore the stack from
|
1723 |
|
|
its backpointer, which we maintain. */
|
1724 |
|
|
#define EXIT_IGNORE_STACK 1
|
1725 |
|
|
|
1726 |
|
|
/* Define this macro as a C expression that is nonzero for registers
|
1727 |
|
|
that are used by the epilogue or the return' pattern. The stack
|
1728 |
|
|
and frame pointer registers are already be assumed to be used as
|
1729 |
|
|
needed. */
|
1730 |
|
|
|
1731 |
|
|
#define EPILOGUE_USES(REGNO) \
|
1732 |
|
|
((reload_completed && (REGNO) == LR_REGNO) \
|
1733 |
|
|
|| (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
|
1734 |
|
|
|| (crtl->calls_eh_return \
|
1735 |
|
|
&& TARGET_AIX \
|
1736 |
|
|
&& (REGNO) == 2))
|
1737 |
|
|
|
1738 |
|
|
|
1739 |
|
|
/* Length in units of the trampoline for entering a nested function. */
|
1740 |
|
|
|
1741 |
|
|
#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
|
1742 |
|
|
|
1743 |
|
|
/* Definitions for __builtin_return_address and __builtin_frame_address.
|
1744 |
|
|
__builtin_return_address (0) should give link register (65), enable
|
1745 |
|
|
this. */
|
1746 |
|
|
/* This should be uncommented, so that the link register is used, but
|
1747 |
|
|
currently this would result in unmatched insns and spilling fixed
|
1748 |
|
|
registers so we'll leave it for another day. When these problems are
|
1749 |
|
|
taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
|
1750 |
|
|
(mrs) */
|
1751 |
|
|
/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
|
1752 |
|
|
|
1753 |
|
|
/* Number of bytes into the frame return addresses can be found. See
|
1754 |
|
|
rs6000_stack_info in rs6000.c for more information on how the different
|
1755 |
|
|
abi's store the return address. */
|
1756 |
|
|
#define RETURN_ADDRESS_OFFSET \
|
1757 |
|
|
((DEFAULT_ABI == ABI_AIX \
|
1758 |
|
|
|| DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
|
1759 |
|
|
(DEFAULT_ABI == ABI_V4) ? 4 : \
|
1760 |
|
|
(internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
|
1761 |
|
|
|
1762 |
|
|
/* The current return address is in link register (65). The return address
|
1763 |
|
|
of anything farther back is accessed normally at an offset of 8 from the
|
1764 |
|
|
frame pointer. */
|
1765 |
|
|
#define RETURN_ADDR_RTX(COUNT, FRAME) \
|
1766 |
|
|
(rs6000_return_addr (COUNT, FRAME))
|
1767 |
|
|
|
1768 |
|
|
|
1769 |
|
|
/* Definitions for register eliminations.
|
1770 |
|
|
|
1771 |
|
|
We have two registers that can be eliminated on the RS/6000. First, the
|
1772 |
|
|
frame pointer register can often be eliminated in favor of the stack
|
1773 |
|
|
pointer register. Secondly, the argument pointer register can always be
|
1774 |
|
|
eliminated; it is replaced with either the stack or frame pointer.
|
1775 |
|
|
|
1776 |
|
|
In addition, we use the elimination mechanism to see if r30 is needed
|
1777 |
|
|
Initially we assume that it isn't. If it is, we spill it. This is done
|
1778 |
|
|
by making it an eliminable register. We replace it with itself so that
|
1779 |
|
|
if it isn't needed, then existing uses won't be modified. */
|
1780 |
|
|
|
1781 |
|
|
/* This is an array of structures. Each structure initializes one pair
|
1782 |
|
|
of eliminable registers. The "from" register number is given first,
|
1783 |
|
|
followed by "to". Eliminations of the same "from" register are listed
|
1784 |
|
|
in order of preference. */
|
1785 |
|
|
#define ELIMINABLE_REGS \
|
1786 |
|
|
{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
1787 |
|
|
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
1788 |
|
|
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
1789 |
|
|
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
1790 |
|
|
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
1791 |
|
|
{ RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
|
1792 |
|
|
|
1793 |
|
|
/* Define the offset between two registers, one to be eliminated, and the other
|
1794 |
|
|
its replacement, at the start of a routine. */
|
1795 |
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
1796 |
|
|
((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
|
1797 |
|
|
|
1798 |
|
|
/* Addressing modes, and classification of registers for them. */
|
1799 |
|
|
|
1800 |
|
|
#define HAVE_PRE_DECREMENT 1
|
1801 |
|
|
#define HAVE_PRE_INCREMENT 1
|
1802 |
|
|
#define HAVE_PRE_MODIFY_DISP 1
|
1803 |
|
|
#define HAVE_PRE_MODIFY_REG 1
|
1804 |
|
|
|
1805 |
|
|
/* Macros to check register numbers against specific register classes. */
|
1806 |
|
|
|
1807 |
|
|
/* These assume that REGNO is a hard or pseudo reg number.
|
1808 |
|
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
1809 |
|
|
or a pseudo reg currently allocated to a suitable hard reg.
|
1810 |
|
|
Since they use reg_renumber, they are safe only once reg_renumber
|
1811 |
|
|
has been allocated, which happens in local-alloc.c. */
|
1812 |
|
|
|
1813 |
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
1814 |
|
|
((REGNO) < FIRST_PSEUDO_REGISTER \
|
1815 |
|
|
? (REGNO) <= 31 || (REGNO) == 67 \
|
1816 |
|
|
|| (REGNO) == FRAME_POINTER_REGNUM \
|
1817 |
|
|
: (reg_renumber[REGNO] >= 0 \
|
1818 |
|
|
&& (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
|
1819 |
|
|
|| reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
|
1820 |
|
|
|
1821 |
|
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
1822 |
|
|
((REGNO) < FIRST_PSEUDO_REGISTER \
|
1823 |
|
|
? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
|
1824 |
|
|
|| (REGNO) == FRAME_POINTER_REGNUM \
|
1825 |
|
|
: (reg_renumber[REGNO] > 0 \
|
1826 |
|
|
&& (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
|
1827 |
|
|
|| reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
|
1828 |
|
|
|
1829 |
|
|
/* Nonzero if X is a hard reg that can be used as an index
|
1830 |
|
|
or if it is a pseudo reg in the non-strict case. */
|
1831 |
|
|
#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
|
1832 |
|
|
((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|
1833 |
|
|
|| REGNO_OK_FOR_INDEX_P (REGNO (X)))
|
1834 |
|
|
|
1835 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg
|
1836 |
|
|
or if it is a pseudo reg in the non-strict case. */
|
1837 |
|
|
#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
|
1838 |
|
|
((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|
1839 |
|
|
|| REGNO_OK_FOR_BASE_P (REGNO (X)))
|
1840 |
|
|
|
1841 |
|
|
|
1842 |
|
|
/* Maximum number of registers that can appear in a valid memory address. */
|
1843 |
|
|
|
1844 |
|
|
#define MAX_REGS_PER_ADDRESS 2
|
1845 |
|
|
|
1846 |
|
|
/* Recognize any constant value that is a valid address. */
|
1847 |
|
|
|
1848 |
|
|
#define CONSTANT_ADDRESS_P(X) \
|
1849 |
|
|
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|
1850 |
|
|
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
|
1851 |
|
|
|| GET_CODE (X) == HIGH)
|
1852 |
|
|
|
1853 |
|
|
/* Nonzero if the constant value X is a legitimate general operand.
|
1854 |
|
|
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
|
1855 |
|
|
|
1856 |
|
|
On the RS/6000, all integer constants are acceptable, most won't be valid
|
1857 |
|
|
for particular insns, though. Only easy FP constants are
|
1858 |
|
|
acceptable. */
|
1859 |
|
|
|
1860 |
|
|
#define LEGITIMATE_CONSTANT_P(X) \
|
1861 |
|
|
(((GET_CODE (X) != CONST_DOUBLE \
|
1862 |
|
|
&& GET_CODE (X) != CONST_VECTOR) \
|
1863 |
|
|
|| GET_MODE (X) == VOIDmode \
|
1864 |
|
|
|| (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
|
1865 |
|
|
|| easy_fp_constant (X, GET_MODE (X)) \
|
1866 |
|
|
|| easy_vector_constant (X, GET_MODE (X))) \
|
1867 |
|
|
&& !rs6000_tls_referenced_p (X))
|
1868 |
|
|
|
1869 |
|
|
#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
|
1870 |
|
|
#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
|
1871 |
|
|
&& EASY_VECTOR_15((n) >> 1) \
|
1872 |
|
|
&& ((n) & 1) == 0)
|
1873 |
|
|
|
1874 |
|
|
#define EASY_VECTOR_MSB(n,mode) \
|
1875 |
|
|
(((unsigned HOST_WIDE_INT)n) == \
|
1876 |
|
|
((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
|
1877 |
|
|
|
1878 |
|
|
|
1879 |
|
|
/* Try a machine-dependent way of reloading an illegitimate address
|
1880 |
|
|
operand. If we find one, push the reload and jump to WIN. This
|
1881 |
|
|
macro is used in only one place: `find_reloads_address' in reload.c.
|
1882 |
|
|
|
1883 |
|
|
Implemented on rs6000 by rs6000_legitimize_reload_address.
|
1884 |
|
|
Note that (X) is evaluated twice; this is safe in current usage. */
|
1885 |
|
|
|
1886 |
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
1887 |
|
|
do { \
|
1888 |
|
|
int win; \
|
1889 |
|
|
(X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
|
1890 |
|
|
(int)(TYPE), (IND_LEVELS), &win); \
|
1891 |
|
|
if ( win ) \
|
1892 |
|
|
goto WIN; \
|
1893 |
|
|
} while (0)
|
1894 |
|
|
|
1895 |
|
|
/* Go to LABEL if ADDR (a legitimate address expression)
|
1896 |
|
|
has an effect that depends on the machine mode it is used for. */
|
1897 |
|
|
|
1898 |
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
|
1899 |
|
|
do { \
|
1900 |
|
|
if (rs6000_mode_dependent_address_ptr (ADDR)) \
|
1901 |
|
|
goto LABEL; \
|
1902 |
|
|
} while (0)
|
1903 |
|
|
|
1904 |
|
|
#define FIND_BASE_TERM rs6000_find_base_term
|
1905 |
|
|
|
1906 |
|
|
/* The register number of the register used to address a table of
|
1907 |
|
|
static data addresses in memory. In some cases this register is
|
1908 |
|
|
defined by a processor's "application binary interface" (ABI).
|
1909 |
|
|
When this macro is defined, RTL is generated for this register
|
1910 |
|
|
once, as with the stack pointer and frame pointer registers. If
|
1911 |
|
|
this macro is not defined, it is up to the machine-dependent files
|
1912 |
|
|
to allocate such a register (if necessary). */
|
1913 |
|
|
|
1914 |
|
|
#define RS6000_PIC_OFFSET_TABLE_REGNUM 30
|
1915 |
|
|
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
|
1916 |
|
|
|
1917 |
|
|
#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
|
1918 |
|
|
|
1919 |
|
|
/* Define this macro if the register defined by
|
1920 |
|
|
`PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
|
1921 |
|
|
this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
|
1922 |
|
|
|
1923 |
|
|
/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
|
1924 |
|
|
|
1925 |
|
|
/* A C expression that is nonzero if X is a legitimate immediate
|
1926 |
|
|
operand on the target machine when generating position independent
|
1927 |
|
|
code. You can assume that X satisfies `CONSTANT_P', so you need
|
1928 |
|
|
not check this. You can also assume FLAG_PIC is true, so you need
|
1929 |
|
|
not check it either. You need not define this macro if all
|
1930 |
|
|
constants (including `SYMBOL_REF') can be immediate operands when
|
1931 |
|
|
generating position independent code. */
|
1932 |
|
|
|
1933 |
|
|
/* #define LEGITIMATE_PIC_OPERAND_P (X) */
|
1934 |
|
|
|
1935 |
|
|
/* Define this if some processing needs to be done immediately before
|
1936 |
|
|
emitting code for an insn. */
|
1937 |
|
|
|
1938 |
|
|
#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
|
1939 |
|
|
rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
|
1940 |
|
|
|
1941 |
|
|
/* Specify the machine mode that this machine uses
|
1942 |
|
|
for the index in the tablejump instruction. */
|
1943 |
|
|
#define CASE_VECTOR_MODE SImode
|
1944 |
|
|
|
1945 |
|
|
/* Define as C expression which evaluates to nonzero if the tablejump
|
1946 |
|
|
instruction expects the table to contain offsets from the address of the
|
1947 |
|
|
table.
|
1948 |
|
|
Do not define this if the table should contain absolute addresses. */
|
1949 |
|
|
#define CASE_VECTOR_PC_RELATIVE 1
|
1950 |
|
|
|
1951 |
|
|
/* Define this as 1 if `char' should by default be signed; else as 0. */
|
1952 |
|
|
#define DEFAULT_SIGNED_CHAR 0
|
1953 |
|
|
|
1954 |
|
|
/* This flag, if defined, says the same insns that convert to a signed fixnum
|
1955 |
|
|
also convert validly to an unsigned one. */
|
1956 |
|
|
|
1957 |
|
|
/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
|
1958 |
|
|
|
1959 |
|
|
/* An integer expression for the size in bits of the largest integer machine
|
1960 |
|
|
mode that should actually be used. */
|
1961 |
|
|
|
1962 |
|
|
/* Allow pairs of registers to be used, which is the intent of the default. */
|
1963 |
|
|
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
|
1964 |
|
|
|
1965 |
|
|
/* Max number of bytes we can move from memory to memory
|
1966 |
|
|
in one reasonably fast instruction. */
|
1967 |
|
|
#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
|
1968 |
|
|
#define MAX_MOVE_MAX 8
|
1969 |
|
|
|
1970 |
|
|
/* Nonzero if access to memory by bytes is no faster than for words.
|
1971 |
|
|
Also nonzero if doing byte operations (specifically shifts) in registers
|
1972 |
|
|
is undesirable. */
|
1973 |
|
|
#define SLOW_BYTE_ACCESS 1
|
1974 |
|
|
|
1975 |
|
|
/* Define if operations between registers always perform the operation
|
1976 |
|
|
on the full register even if a narrower mode is specified. */
|
1977 |
|
|
#define WORD_REGISTER_OPERATIONS
|
1978 |
|
|
|
1979 |
|
|
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
|
1980 |
|
|
will either zero-extend or sign-extend. The value of this macro should
|
1981 |
|
|
be the code that says which one of the two operations is implicitly
|
1982 |
|
|
done, UNKNOWN if none. */
|
1983 |
|
|
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
|
1984 |
|
|
|
1985 |
|
|
/* Define if loading short immediate values into registers sign extends. */
|
1986 |
|
|
#define SHORT_IMMEDIATES_SIGN_EXTEND
|
1987 |
|
|
|
1988 |
|
|
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
1989 |
|
|
is done just by pretending it is already truncated. */
|
1990 |
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
1991 |
|
|
|
1992 |
|
|
/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
|
1993 |
|
|
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
|
1994 |
|
|
((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
|
1995 |
|
|
|
1996 |
|
|
/* The CTZ patterns return -1 for input of zero. */
|
1997 |
|
|
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
|
1998 |
|
|
|
1999 |
|
|
/* Specify the machine mode that pointers have.
|
2000 |
|
|
After generation of rtl, the compiler makes no further distinction
|
2001 |
|
|
between pointers and any other objects of this machine mode. */
|
2002 |
|
|
extern unsigned rs6000_pmode;
|
2003 |
|
|
#define Pmode ((enum machine_mode)rs6000_pmode)
|
2004 |
|
|
|
2005 |
|
|
/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
|
2006 |
|
|
#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
|
2007 |
|
|
|
2008 |
|
|
/* Mode of a function address in a call instruction (for indexing purposes).
|
2009 |
|
|
Doesn't matter on RS/6000. */
|
2010 |
|
|
#define FUNCTION_MODE SImode
|
2011 |
|
|
|
2012 |
|
|
/* Define this if addresses of constant functions
|
2013 |
|
|
shouldn't be put through pseudo regs where they can be cse'd.
|
2014 |
|
|
Desirable on machines where ordinary constants are expensive
|
2015 |
|
|
but a CALL with constant address is cheap. */
|
2016 |
|
|
#define NO_FUNCTION_CSE
|
2017 |
|
|
|
2018 |
|
|
/* Define this to be nonzero if shift instructions ignore all but the low-order
|
2019 |
|
|
few bits.
|
2020 |
|
|
|
2021 |
|
|
The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
|
2022 |
|
|
have been dropped from the PowerPC architecture. */
|
2023 |
|
|
|
2024 |
|
|
#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
|
2025 |
|
|
|
2026 |
|
|
/* Adjust the length of an INSN. LENGTH is the currently-computed length and
|
2027 |
|
|
should be adjusted to reflect any required changes. This macro is used when
|
2028 |
|
|
there is some systematic length adjustment required that would be difficult
|
2029 |
|
|
to express in the length attribute. */
|
2030 |
|
|
|
2031 |
|
|
/* #define ADJUST_INSN_LENGTH(X,LENGTH) */
|
2032 |
|
|
|
2033 |
|
|
/* Given a comparison code (EQ, NE, etc.) and the first operand of a
|
2034 |
|
|
COMPARE, return the mode to be used for the comparison. For
|
2035 |
|
|
floating-point, CCFPmode should be used. CCUNSmode should be used
|
2036 |
|
|
for unsigned comparisons. CCEQmode should be used when we are
|
2037 |
|
|
doing an inequality comparison on the result of a
|
2038 |
|
|
comparison. CCmode should be used in all other cases. */
|
2039 |
|
|
|
2040 |
|
|
#define SELECT_CC_MODE(OP,X,Y) \
|
2041 |
|
|
(SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
|
2042 |
|
|
: (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
|
2043 |
|
|
: (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
|
2044 |
|
|
? CCEQmode : CCmode))
|
2045 |
|
|
|
2046 |
|
|
/* Can the condition code MODE be safely reversed? This is safe in
|
2047 |
|
|
all cases on this port, because at present it doesn't use the
|
2048 |
|
|
trapping FP comparisons (fcmpo). */
|
2049 |
|
|
#define REVERSIBLE_CC_MODE(MODE) 1
|
2050 |
|
|
|
2051 |
|
|
/* Given a condition code and a mode, return the inverse condition. */
|
2052 |
|
|
#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
|
2053 |
|
|
|
2054 |
|
|
|
2055 |
|
|
/* Control the assembler format that we output. */
|
2056 |
|
|
|
2057 |
|
|
/* A C string constant describing how to begin a comment in the target
|
2058 |
|
|
assembler language. The compiler assumes that the comment will end at
|
2059 |
|
|
the end of the line. */
|
2060 |
|
|
#define ASM_COMMENT_START " #"
|
2061 |
|
|
|
2062 |
|
|
/* Flag to say the TOC is initialized */
|
2063 |
|
|
extern int toc_initialized;
|
2064 |
|
|
|
2065 |
|
|
/* Macro to output a special constant pool entry. Go to WIN if we output
|
2066 |
|
|
it. Otherwise, it is written the usual way.
|
2067 |
|
|
|
2068 |
|
|
On the RS/6000, toc entries are handled this way. */
|
2069 |
|
|
|
2070 |
|
|
#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
|
2071 |
|
|
{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
|
2072 |
|
|
{ \
|
2073 |
|
|
output_toc (FILE, X, LABELNO, MODE); \
|
2074 |
|
|
goto WIN; \
|
2075 |
|
|
} \
|
2076 |
|
|
}
|
2077 |
|
|
|
2078 |
|
|
#ifdef HAVE_GAS_WEAK
|
2079 |
|
|
#define RS6000_WEAK 1
|
2080 |
|
|
#else
|
2081 |
|
|
#define RS6000_WEAK 0
|
2082 |
|
|
#endif
|
2083 |
|
|
|
2084 |
|
|
#if RS6000_WEAK
|
2085 |
|
|
/* Used in lieu of ASM_WEAKEN_LABEL. */
|
2086 |
|
|
#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
|
2087 |
|
|
do \
|
2088 |
|
|
{ \
|
2089 |
|
|
fputs ("\t.weak\t", (FILE)); \
|
2090 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
|
2091 |
|
|
if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
|
2092 |
|
|
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
|
2093 |
|
|
{ \
|
2094 |
|
|
if (TARGET_XCOFF) \
|
2095 |
|
|
fputs ("[DS]", (FILE)); \
|
2096 |
|
|
fputs ("\n\t.weak\t.", (FILE)); \
|
2097 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
|
2098 |
|
|
} \
|
2099 |
|
|
fputc ('\n', (FILE)); \
|
2100 |
|
|
if (VAL) \
|
2101 |
|
|
{ \
|
2102 |
|
|
ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
|
2103 |
|
|
if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
|
2104 |
|
|
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
|
2105 |
|
|
{ \
|
2106 |
|
|
fputs ("\t.set\t.", (FILE)); \
|
2107 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
|
2108 |
|
|
fputs (",.", (FILE)); \
|
2109 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
|
2110 |
|
|
fputc ('\n', (FILE)); \
|
2111 |
|
|
} \
|
2112 |
|
|
} \
|
2113 |
|
|
} \
|
2114 |
|
|
while (0)
|
2115 |
|
|
#endif
|
2116 |
|
|
|
2117 |
|
|
#if HAVE_GAS_WEAKREF
|
2118 |
|
|
#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
|
2119 |
|
|
do \
|
2120 |
|
|
{ \
|
2121 |
|
|
fputs ("\t.weakref\t", (FILE)); \
|
2122 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
|
2123 |
|
|
fputs (", ", (FILE)); \
|
2124 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
|
2125 |
|
|
if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
|
2126 |
|
|
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
|
2127 |
|
|
{ \
|
2128 |
|
|
fputs ("\n\t.weakref\t.", (FILE)); \
|
2129 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
|
2130 |
|
|
fputs (", .", (FILE)); \
|
2131 |
|
|
RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
|
2132 |
|
|
} \
|
2133 |
|
|
fputc ('\n', (FILE)); \
|
2134 |
|
|
} while (0)
|
2135 |
|
|
#endif
|
2136 |
|
|
|
2137 |
|
|
/* This implements the `alias' attribute. */
|
2138 |
|
|
#undef ASM_OUTPUT_DEF_FROM_DECLS
|
2139 |
|
|
#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
|
2140 |
|
|
do \
|
2141 |
|
|
{ \
|
2142 |
|
|
const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
|
2143 |
|
|
const char *name = IDENTIFIER_POINTER (TARGET); \
|
2144 |
|
|
if (TREE_CODE (DECL) == FUNCTION_DECL \
|
2145 |
|
|
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
|
2146 |
|
|
{ \
|
2147 |
|
|
if (TREE_PUBLIC (DECL)) \
|
2148 |
|
|
{ \
|
2149 |
|
|
if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
|
2150 |
|
|
{ \
|
2151 |
|
|
fputs ("\t.globl\t.", FILE); \
|
2152 |
|
|
RS6000_OUTPUT_BASENAME (FILE, alias); \
|
2153 |
|
|
putc ('\n', FILE); \
|
2154 |
|
|
} \
|
2155 |
|
|
} \
|
2156 |
|
|
else if (TARGET_XCOFF) \
|
2157 |
|
|
{ \
|
2158 |
|
|
fputs ("\t.lglobl\t.", FILE); \
|
2159 |
|
|
RS6000_OUTPUT_BASENAME (FILE, alias); \
|
2160 |
|
|
putc ('\n', FILE); \
|
2161 |
|
|
} \
|
2162 |
|
|
fputs ("\t.set\t.", FILE); \
|
2163 |
|
|
RS6000_OUTPUT_BASENAME (FILE, alias); \
|
2164 |
|
|
fputs (",.", FILE); \
|
2165 |
|
|
RS6000_OUTPUT_BASENAME (FILE, name); \
|
2166 |
|
|
fputc ('\n', FILE); \
|
2167 |
|
|
} \
|
2168 |
|
|
ASM_OUTPUT_DEF (FILE, alias, name); \
|
2169 |
|
|
} \
|
2170 |
|
|
while (0)
|
2171 |
|
|
|
2172 |
|
|
#define TARGET_ASM_FILE_START rs6000_file_start
|
2173 |
|
|
|
2174 |
|
|
/* Output to assembler file text saying following lines
|
2175 |
|
|
may contain character constants, extra white space, comments, etc. */
|
2176 |
|
|
|
2177 |
|
|
#define ASM_APP_ON ""
|
2178 |
|
|
|
2179 |
|
|
/* Output to assembler file text saying following lines
|
2180 |
|
|
no longer contain unusual constructs. */
|
2181 |
|
|
|
2182 |
|
|
#define ASM_APP_OFF ""
|
2183 |
|
|
|
2184 |
|
|
/* How to refer to registers in assembler output.
|
2185 |
|
|
This sequence is indexed by compiler's hard-register-number (see above). */
|
2186 |
|
|
|
2187 |
|
|
extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
|
2188 |
|
|
|
2189 |
|
|
#define REGISTER_NAMES \
|
2190 |
|
|
{ \
|
2191 |
|
|
&rs6000_reg_names[ 0][0], /* r0 */ \
|
2192 |
|
|
&rs6000_reg_names[ 1][0], /* r1 */ \
|
2193 |
|
|
&rs6000_reg_names[ 2][0], /* r2 */ \
|
2194 |
|
|
&rs6000_reg_names[ 3][0], /* r3 */ \
|
2195 |
|
|
&rs6000_reg_names[ 4][0], /* r4 */ \
|
2196 |
|
|
&rs6000_reg_names[ 5][0], /* r5 */ \
|
2197 |
|
|
&rs6000_reg_names[ 6][0], /* r6 */ \
|
2198 |
|
|
&rs6000_reg_names[ 7][0], /* r7 */ \
|
2199 |
|
|
&rs6000_reg_names[ 8][0], /* r8 */ \
|
2200 |
|
|
&rs6000_reg_names[ 9][0], /* r9 */ \
|
2201 |
|
|
&rs6000_reg_names[10][0], /* r10 */ \
|
2202 |
|
|
&rs6000_reg_names[11][0], /* r11 */ \
|
2203 |
|
|
&rs6000_reg_names[12][0], /* r12 */ \
|
2204 |
|
|
&rs6000_reg_names[13][0], /* r13 */ \
|
2205 |
|
|
&rs6000_reg_names[14][0], /* r14 */ \
|
2206 |
|
|
&rs6000_reg_names[15][0], /* r15 */ \
|
2207 |
|
|
&rs6000_reg_names[16][0], /* r16 */ \
|
2208 |
|
|
&rs6000_reg_names[17][0], /* r17 */ \
|
2209 |
|
|
&rs6000_reg_names[18][0], /* r18 */ \
|
2210 |
|
|
&rs6000_reg_names[19][0], /* r19 */ \
|
2211 |
|
|
&rs6000_reg_names[20][0], /* r20 */ \
|
2212 |
|
|
&rs6000_reg_names[21][0], /* r21 */ \
|
2213 |
|
|
&rs6000_reg_names[22][0], /* r22 */ \
|
2214 |
|
|
&rs6000_reg_names[23][0], /* r23 */ \
|
2215 |
|
|
&rs6000_reg_names[24][0], /* r24 */ \
|
2216 |
|
|
&rs6000_reg_names[25][0], /* r25 */ \
|
2217 |
|
|
&rs6000_reg_names[26][0], /* r26 */ \
|
2218 |
|
|
&rs6000_reg_names[27][0], /* r27 */ \
|
2219 |
|
|
&rs6000_reg_names[28][0], /* r28 */ \
|
2220 |
|
|
&rs6000_reg_names[29][0], /* r29 */ \
|
2221 |
|
|
&rs6000_reg_names[30][0], /* r30 */ \
|
2222 |
|
|
&rs6000_reg_names[31][0], /* r31 */ \
|
2223 |
|
|
\
|
2224 |
|
|
&rs6000_reg_names[32][0], /* fr0 */ \
|
2225 |
|
|
&rs6000_reg_names[33][0], /* fr1 */ \
|
2226 |
|
|
&rs6000_reg_names[34][0], /* fr2 */ \
|
2227 |
|
|
&rs6000_reg_names[35][0], /* fr3 */ \
|
2228 |
|
|
&rs6000_reg_names[36][0], /* fr4 */ \
|
2229 |
|
|
&rs6000_reg_names[37][0], /* fr5 */ \
|
2230 |
|
|
&rs6000_reg_names[38][0], /* fr6 */ \
|
2231 |
|
|
&rs6000_reg_names[39][0], /* fr7 */ \
|
2232 |
|
|
&rs6000_reg_names[40][0], /* fr8 */ \
|
2233 |
|
|
&rs6000_reg_names[41][0], /* fr9 */ \
|
2234 |
|
|
&rs6000_reg_names[42][0], /* fr10 */ \
|
2235 |
|
|
&rs6000_reg_names[43][0], /* fr11 */ \
|
2236 |
|
|
&rs6000_reg_names[44][0], /* fr12 */ \
|
2237 |
|
|
&rs6000_reg_names[45][0], /* fr13 */ \
|
2238 |
|
|
&rs6000_reg_names[46][0], /* fr14 */ \
|
2239 |
|
|
&rs6000_reg_names[47][0], /* fr15 */ \
|
2240 |
|
|
&rs6000_reg_names[48][0], /* fr16 */ \
|
2241 |
|
|
&rs6000_reg_names[49][0], /* fr17 */ \
|
2242 |
|
|
&rs6000_reg_names[50][0], /* fr18 */ \
|
2243 |
|
|
&rs6000_reg_names[51][0], /* fr19 */ \
|
2244 |
|
|
&rs6000_reg_names[52][0], /* fr20 */ \
|
2245 |
|
|
&rs6000_reg_names[53][0], /* fr21 */ \
|
2246 |
|
|
&rs6000_reg_names[54][0], /* fr22 */ \
|
2247 |
|
|
&rs6000_reg_names[55][0], /* fr23 */ \
|
2248 |
|
|
&rs6000_reg_names[56][0], /* fr24 */ \
|
2249 |
|
|
&rs6000_reg_names[57][0], /* fr25 */ \
|
2250 |
|
|
&rs6000_reg_names[58][0], /* fr26 */ \
|
2251 |
|
|
&rs6000_reg_names[59][0], /* fr27 */ \
|
2252 |
|
|
&rs6000_reg_names[60][0], /* fr28 */ \
|
2253 |
|
|
&rs6000_reg_names[61][0], /* fr29 */ \
|
2254 |
|
|
&rs6000_reg_names[62][0], /* fr30 */ \
|
2255 |
|
|
&rs6000_reg_names[63][0], /* fr31 */ \
|
2256 |
|
|
\
|
2257 |
|
|
&rs6000_reg_names[64][0], /* mq */ \
|
2258 |
|
|
&rs6000_reg_names[65][0], /* lr */ \
|
2259 |
|
|
&rs6000_reg_names[66][0], /* ctr */ \
|
2260 |
|
|
&rs6000_reg_names[67][0], /* ap */ \
|
2261 |
|
|
\
|
2262 |
|
|
&rs6000_reg_names[68][0], /* cr0 */ \
|
2263 |
|
|
&rs6000_reg_names[69][0], /* cr1 */ \
|
2264 |
|
|
&rs6000_reg_names[70][0], /* cr2 */ \
|
2265 |
|
|
&rs6000_reg_names[71][0], /* cr3 */ \
|
2266 |
|
|
&rs6000_reg_names[72][0], /* cr4 */ \
|
2267 |
|
|
&rs6000_reg_names[73][0], /* cr5 */ \
|
2268 |
|
|
&rs6000_reg_names[74][0], /* cr6 */ \
|
2269 |
|
|
&rs6000_reg_names[75][0], /* cr7 */ \
|
2270 |
|
|
\
|
2271 |
|
|
&rs6000_reg_names[76][0], /* xer */ \
|
2272 |
|
|
\
|
2273 |
|
|
&rs6000_reg_names[77][0], /* v0 */ \
|
2274 |
|
|
&rs6000_reg_names[78][0], /* v1 */ \
|
2275 |
|
|
&rs6000_reg_names[79][0], /* v2 */ \
|
2276 |
|
|
&rs6000_reg_names[80][0], /* v3 */ \
|
2277 |
|
|
&rs6000_reg_names[81][0], /* v4 */ \
|
2278 |
|
|
&rs6000_reg_names[82][0], /* v5 */ \
|
2279 |
|
|
&rs6000_reg_names[83][0], /* v6 */ \
|
2280 |
|
|
&rs6000_reg_names[84][0], /* v7 */ \
|
2281 |
|
|
&rs6000_reg_names[85][0], /* v8 */ \
|
2282 |
|
|
&rs6000_reg_names[86][0], /* v9 */ \
|
2283 |
|
|
&rs6000_reg_names[87][0], /* v10 */ \
|
2284 |
|
|
&rs6000_reg_names[88][0], /* v11 */ \
|
2285 |
|
|
&rs6000_reg_names[89][0], /* v12 */ \
|
2286 |
|
|
&rs6000_reg_names[90][0], /* v13 */ \
|
2287 |
|
|
&rs6000_reg_names[91][0], /* v14 */ \
|
2288 |
|
|
&rs6000_reg_names[92][0], /* v15 */ \
|
2289 |
|
|
&rs6000_reg_names[93][0], /* v16 */ \
|
2290 |
|
|
&rs6000_reg_names[94][0], /* v17 */ \
|
2291 |
|
|
&rs6000_reg_names[95][0], /* v18 */ \
|
2292 |
|
|
&rs6000_reg_names[96][0], /* v19 */ \
|
2293 |
|
|
&rs6000_reg_names[97][0], /* v20 */ \
|
2294 |
|
|
&rs6000_reg_names[98][0], /* v21 */ \
|
2295 |
|
|
&rs6000_reg_names[99][0], /* v22 */ \
|
2296 |
|
|
&rs6000_reg_names[100][0], /* v23 */ \
|
2297 |
|
|
&rs6000_reg_names[101][0], /* v24 */ \
|
2298 |
|
|
&rs6000_reg_names[102][0], /* v25 */ \
|
2299 |
|
|
&rs6000_reg_names[103][0], /* v26 */ \
|
2300 |
|
|
&rs6000_reg_names[104][0], /* v27 */ \
|
2301 |
|
|
&rs6000_reg_names[105][0], /* v28 */ \
|
2302 |
|
|
&rs6000_reg_names[106][0], /* v29 */ \
|
2303 |
|
|
&rs6000_reg_names[107][0], /* v30 */ \
|
2304 |
|
|
&rs6000_reg_names[108][0], /* v31 */ \
|
2305 |
|
|
&rs6000_reg_names[109][0], /* vrsave */ \
|
2306 |
|
|
&rs6000_reg_names[110][0], /* vscr */ \
|
2307 |
|
|
&rs6000_reg_names[111][0], /* spe_acc */ \
|
2308 |
|
|
&rs6000_reg_names[112][0], /* spefscr */ \
|
2309 |
|
|
&rs6000_reg_names[113][0], /* sfp */ \
|
2310 |
|
|
}
|
2311 |
|
|
|
2312 |
|
|
/* Table of additional register names to use in user input. */
|
2313 |
|
|
|
2314 |
|
|
#define ADDITIONAL_REGISTER_NAMES \
|
2315 |
|
|
{{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
|
2316 |
|
|
{"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
|
2317 |
|
|
{"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
|
2318 |
|
|
{"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
|
2319 |
|
|
{"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
|
2320 |
|
|
{"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
|
2321 |
|
|
{"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
|
2322 |
|
|
{"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
|
2323 |
|
|
{"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
|
2324 |
|
|
{"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
|
2325 |
|
|
{"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
|
2326 |
|
|
{"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
|
2327 |
|
|
{"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
|
2328 |
|
|
{"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
|
2329 |
|
|
{"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
|
2330 |
|
|
{"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
|
2331 |
|
|
{"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
|
2332 |
|
|
{"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
|
2333 |
|
|
{"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
|
2334 |
|
|
{"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
|
2335 |
|
|
{"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
|
2336 |
|
|
{"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
|
2337 |
|
|
{"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
|
2338 |
|
|
{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
|
2339 |
|
|
{"vrsave", 109}, {"vscr", 110}, \
|
2340 |
|
|
{"spe_acc", 111}, {"spefscr", 112}, \
|
2341 |
|
|
/* no additional names for: mq, lr, ctr, ap */ \
|
2342 |
|
|
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
|
2343 |
|
|
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
|
2344 |
|
|
{"cc", 68}, {"sp", 1}, {"toc", 2}, \
|
2345 |
|
|
/* VSX registers overlaid on top of FR, Altivec registers */ \
|
2346 |
|
|
{"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
|
2347 |
|
|
{"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
|
2348 |
|
|
{"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
|
2349 |
|
|
{"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
|
2350 |
|
|
{"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
|
2351 |
|
|
{"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
|
2352 |
|
|
{"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
|
2353 |
|
|
{"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
|
2354 |
|
|
{"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
|
2355 |
|
|
{"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
|
2356 |
|
|
{"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
|
2357 |
|
|
{"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
|
2358 |
|
|
{"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
|
2359 |
|
|
{"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
|
2360 |
|
|
{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
|
2361 |
|
|
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
|
2362 |
|
|
|
2363 |
|
|
/* Text to write out after a CALL that may be replaced by glue code by
|
2364 |
|
|
the loader. This depends on the AIX version. */
|
2365 |
|
|
#define RS6000_CALL_GLUE "cror 31,31,31"
|
2366 |
|
|
|
2367 |
|
|
/* This is how to output an element of a case-vector that is relative. */
|
2368 |
|
|
|
2369 |
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
2370 |
|
|
do { char buf[100]; \
|
2371 |
|
|
fputs ("\t.long ", FILE); \
|
2372 |
|
|
ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
|
2373 |
|
|
assemble_name (FILE, buf); \
|
2374 |
|
|
putc ('-', FILE); \
|
2375 |
|
|
ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
|
2376 |
|
|
assemble_name (FILE, buf); \
|
2377 |
|
|
putc ('\n', FILE); \
|
2378 |
|
|
} while (0)
|
2379 |
|
|
|
2380 |
|
|
/* This is how to output an assembler line
|
2381 |
|
|
that says to advance the location counter
|
2382 |
|
|
to a multiple of 2**LOG bytes. */
|
2383 |
|
|
|
2384 |
|
|
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
2385 |
|
|
if ((LOG) != 0) \
|
2386 |
|
|
fprintf (FILE, "\t.align %d\n", (LOG))
|
2387 |
|
|
|
2388 |
|
|
/* Pick up the return address upon entry to a procedure. Used for
|
2389 |
|
|
dwarf2 unwind information. This also enables the table driven
|
2390 |
|
|
mechanism. */
|
2391 |
|
|
|
2392 |
|
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
|
2393 |
|
|
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
|
2394 |
|
|
|
2395 |
|
|
/* Describe how we implement __builtin_eh_return. */
|
2396 |
|
|
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
|
2397 |
|
|
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
|
2398 |
|
|
|
2399 |
|
|
/* Print operand X (an rtx) in assembler syntax to file FILE.
|
2400 |
|
|
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
|
2401 |
|
|
For `%' followed by punctuation, CODE is the punctuation and X is null. */
|
2402 |
|
|
|
2403 |
|
|
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
|
2404 |
|
|
|
2405 |
|
|
/* Define which CODE values are valid. */
|
2406 |
|
|
|
2407 |
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
|
2408 |
|
|
((CODE) == '.' || (CODE) == '&')
|
2409 |
|
|
|
2410 |
|
|
/* Print a memory address as an operand to reference that memory location. */
|
2411 |
|
|
|
2412 |
|
|
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
|
2413 |
|
|
|
2414 |
|
|
#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
|
2415 |
|
|
do \
|
2416 |
|
|
if (!rs6000_output_addr_const_extra (STREAM, X)) \
|
2417 |
|
|
goto FAIL; \
|
2418 |
|
|
while (0)
|
2419 |
|
|
|
2420 |
|
|
/* uncomment for disabling the corresponding default options */
|
2421 |
|
|
/* #define MACHINE_no_sched_interblock */
|
2422 |
|
|
/* #define MACHINE_no_sched_speculative */
|
2423 |
|
|
/* #define MACHINE_no_sched_speculative_load */
|
2424 |
|
|
|
2425 |
|
|
/* General flags. */
|
2426 |
|
|
extern int flag_pic;
|
2427 |
|
|
extern int optimize;
|
2428 |
|
|
extern int flag_expensive_optimizations;
|
2429 |
|
|
extern int frame_pointer_needed;
|
2430 |
|
|
|
2431 |
|
|
/* Classification of the builtin functions to properly set the declaration tree
|
2432 |
|
|
flags. */
|
2433 |
|
|
enum rs6000_btc
|
2434 |
|
|
{
|
2435 |
|
|
RS6000_BTC_MISC, /* assume builtin can do anything */
|
2436 |
|
|
RS6000_BTC_CONST, /* builtin is a 'const' function. */
|
2437 |
|
|
RS6000_BTC_PURE, /* builtin is a 'pure' function. */
|
2438 |
|
|
RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */
|
2439 |
|
|
};
|
2440 |
|
|
|
2441 |
|
|
/* Convenience macros to document the instruction type. */
|
2442 |
|
|
#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */
|
2443 |
|
|
#define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */
|
2444 |
|
|
|
2445 |
|
|
#undef RS6000_BUILTIN
|
2446 |
|
|
#undef RS6000_BUILTIN_EQUATE
|
2447 |
|
|
#define RS6000_BUILTIN(NAME, TYPE) NAME,
|
2448 |
|
|
#define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE,
|
2449 |
|
|
|
2450 |
|
|
enum rs6000_builtins
|
2451 |
|
|
{
|
2452 |
|
|
#include "rs6000-builtin.def"
|
2453 |
|
|
|
2454 |
|
|
RS6000_BUILTIN_COUNT
|
2455 |
|
|
};
|
2456 |
|
|
|
2457 |
|
|
#undef RS6000_BUILTIN
|
2458 |
|
|
#undef RS6000_BUILTIN_EQUATE
|
2459 |
|
|
|
2460 |
|
|
enum rs6000_builtin_type_index
|
2461 |
|
|
{
|
2462 |
|
|
RS6000_BTI_NOT_OPAQUE,
|
2463 |
|
|
RS6000_BTI_opaque_V2SI,
|
2464 |
|
|
RS6000_BTI_opaque_V2SF,
|
2465 |
|
|
RS6000_BTI_opaque_p_V2SI,
|
2466 |
|
|
RS6000_BTI_opaque_V4SI,
|
2467 |
|
|
RS6000_BTI_V16QI,
|
2468 |
|
|
RS6000_BTI_V2SI,
|
2469 |
|
|
RS6000_BTI_V2SF,
|
2470 |
|
|
RS6000_BTI_V2DI,
|
2471 |
|
|
RS6000_BTI_V2DF,
|
2472 |
|
|
RS6000_BTI_V4HI,
|
2473 |
|
|
RS6000_BTI_V4SI,
|
2474 |
|
|
RS6000_BTI_V4SF,
|
2475 |
|
|
RS6000_BTI_V8HI,
|
2476 |
|
|
RS6000_BTI_unsigned_V16QI,
|
2477 |
|
|
RS6000_BTI_unsigned_V8HI,
|
2478 |
|
|
RS6000_BTI_unsigned_V4SI,
|
2479 |
|
|
RS6000_BTI_unsigned_V2DI,
|
2480 |
|
|
RS6000_BTI_bool_char, /* __bool char */
|
2481 |
|
|
RS6000_BTI_bool_short, /* __bool short */
|
2482 |
|
|
RS6000_BTI_bool_int, /* __bool int */
|
2483 |
|
|
RS6000_BTI_bool_long, /* __bool long */
|
2484 |
|
|
RS6000_BTI_pixel, /* __pixel */
|
2485 |
|
|
RS6000_BTI_bool_V16QI, /* __vector __bool char */
|
2486 |
|
|
RS6000_BTI_bool_V8HI, /* __vector __bool short */
|
2487 |
|
|
RS6000_BTI_bool_V4SI, /* __vector __bool int */
|
2488 |
|
|
RS6000_BTI_bool_V2DI, /* __vector __bool long */
|
2489 |
|
|
RS6000_BTI_pixel_V8HI, /* __vector __pixel */
|
2490 |
|
|
RS6000_BTI_long, /* long_integer_type_node */
|
2491 |
|
|
RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
|
2492 |
|
|
RS6000_BTI_INTQI, /* intQI_type_node */
|
2493 |
|
|
RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
|
2494 |
|
|
RS6000_BTI_INTHI, /* intHI_type_node */
|
2495 |
|
|
RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
|
2496 |
|
|
RS6000_BTI_INTSI, /* intSI_type_node */
|
2497 |
|
|
RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
|
2498 |
|
|
RS6000_BTI_INTDI, /* intDI_type_node */
|
2499 |
|
|
RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
|
2500 |
|
|
RS6000_BTI_float, /* float_type_node */
|
2501 |
|
|
RS6000_BTI_double, /* double_type_node */
|
2502 |
|
|
RS6000_BTI_void, /* void_type_node */
|
2503 |
|
|
RS6000_BTI_MAX
|
2504 |
|
|
};
|
2505 |
|
|
|
2506 |
|
|
|
2507 |
|
|
#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
|
2508 |
|
|
#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
|
2509 |
|
|
#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
|
2510 |
|
|
#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
|
2511 |
|
|
#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
|
2512 |
|
|
#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
|
2513 |
|
|
#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
|
2514 |
|
|
#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
|
2515 |
|
|
#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
|
2516 |
|
|
#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
|
2517 |
|
|
#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
|
2518 |
|
|
#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
|
2519 |
|
|
#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
|
2520 |
|
|
#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
|
2521 |
|
|
#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
|
2522 |
|
|
#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
|
2523 |
|
|
#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
|
2524 |
|
|
#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
|
2525 |
|
|
#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
|
2526 |
|
|
#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
|
2527 |
|
|
#define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
|
2528 |
|
|
#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
|
2529 |
|
|
#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
|
2530 |
|
|
#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
|
2531 |
|
|
#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
|
2532 |
|
|
#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
|
2533 |
|
|
#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
|
2534 |
|
|
|
2535 |
|
|
#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
|
2536 |
|
|
#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
|
2537 |
|
|
#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
|
2538 |
|
|
#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
|
2539 |
|
|
#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
|
2540 |
|
|
#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
|
2541 |
|
|
#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
|
2542 |
|
|
#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
|
2543 |
|
|
#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
|
2544 |
|
|
#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
|
2545 |
|
|
#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
|
2546 |
|
|
#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
|
2547 |
|
|
#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
|
2548 |
|
|
|
2549 |
|
|
extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
|
2550 |
|
|
extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
|
2551 |
|
|
|