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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [rs6000/] [rs64.md] - Blame information for rev 328

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1 282 jeremybenn 
;; Scheduling description for IBM RS64 processors.
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;;   Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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(define_automaton "rs64,rs64fp")
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(define_cpu_unit "iu_rs64" "rs64")
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(define_cpu_unit "mciu_rs64" "rs64")
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(define_cpu_unit "fpu_rs64" "rs64fp")
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(define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
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;; RS64a 64-bit IU, LSU, FPU, BPU
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(define_insn_reservation "rs64a-load" 2
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  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-store" 2
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  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-fpload" 3
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  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-llsc" 2
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  (and (eq_attr "type" "load_l,store_c")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-integer" 1
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  (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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                        var_shift_rotate,cntlz,exts,isel")
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       (eq_attr "cpu" "rs64a"))
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  "iu_rs64")
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(define_insn_reservation "rs64a-two" 1
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  (and (eq_attr "type" "two")
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       (eq_attr "cpu" "rs64a"))
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  "iu_rs64,iu_rs64")
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(define_insn_reservation "rs64a-three" 1
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  (and (eq_attr "type" "three")
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       (eq_attr "cpu" "rs64a"))
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  "iu_rs64,iu_rs64,iu_rs64")
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(define_insn_reservation "rs64a-imul" 20
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  (and (eq_attr "type" "imul,imul_compare")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64*13")
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(define_insn_reservation "rs64a-imul2" 12
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  (and (eq_attr "type" "imul2")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64*5")
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(define_insn_reservation "rs64a-imul3" 8
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  (and (eq_attr "type" "imul3")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64*2")
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(define_insn_reservation "rs64a-lmul" 34
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  (and (eq_attr "type" "lmul,lmul_compare")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64*34")
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(define_insn_reservation "rs64a-idiv" 66
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  (and (eq_attr "type" "idiv")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64*66")
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(define_insn_reservation "rs64a-ldiv" 66
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  (and (eq_attr "type" "ldiv")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64*66")
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(define_insn_reservation "rs64a-compare" 3
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  (and (eq_attr "type" "cmp,fast_compare,compare,\
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                delayed_compare,var_delayed_compare")
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       (eq_attr "cpu" "rs64a"))
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  "iu_rs64,nothing,bpu_rs64")
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(define_insn_reservation "rs64a-fpcompare" 5
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  (and (eq_attr "type" "fpcompare")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64,fpu_rs64,bpu_rs64")
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(define_insn_reservation "rs64a-fp" 4
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  (and (eq_attr "type" "fp,dmul")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64,fpu_rs64")
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(define_insn_reservation "rs64a-sdiv" 31
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  (and (eq_attr "type" "sdiv,ddiv")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64,fpu_rs64*31")
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(define_insn_reservation "rs64a-sqrt" 49
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  (and (eq_attr "type" "ssqrt,dsqrt")
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       (eq_attr "cpu" "rs64a"))
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  "mciu_rs64,fpu_rs64*49")
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(define_insn_reservation "rs64a-mfcr" 2
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  (and (eq_attr "type" "mfcr")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-mtcr" 3
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  (and (eq_attr "type" "mtcr")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-mtjmpr" 3
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  (and (eq_attr "type" "mtjmpr")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-mfjmpr" 2
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  (and (eq_attr "type" "mfjmpr")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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(define_insn_reservation "rs64a-jmpreg" 1
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  (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
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       (eq_attr "cpu" "rs64a"))
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  "bpu_rs64")
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(define_insn_reservation "rs64a-isync" 6
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  (and (eq_attr "type" "isync")
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       (eq_attr "cpu" "rs64a"))
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  "bpu_rs64")
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(define_insn_reservation "rs64a-sync" 1
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  (and (eq_attr "type" "sync")
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       (eq_attr "cpu" "rs64a"))
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  "lsu_rs64")
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