OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [rs6000/] [vector.md] - Blame information for rev 282

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
;; Expander definitions for vector support between altivec & vsx.  No
2
;; instructions are in this file, this file provides the generic vector
3
;; expander, and the actual vector instructions will be in altivec.md and
4
;; vsx.md
5
 
6
;; Copyright (C) 2009, 2010
7
;; Free Software Foundation, Inc.
8
;; Contributed by Michael Meissner 
9
 
10
;; This file is part of GCC.
11
 
12
;; GCC is free software; you can redistribute it and/or modify it
13
;; under the terms of the GNU General Public License as published
14
;; by the Free Software Foundation; either version 3, or (at your
15
;; option) any later version.
16
 
17
;; GCC is distributed in the hope that it will be useful, but WITHOUT
18
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
20
;; License for more details.
21
 
22
;; You should have received a copy of the GNU General Public License
23
;; along with GCC; see the file COPYING3.  If not see
24
;; .
25
 
26
 
27
;; Vector int modes
28
(define_mode_iterator VEC_I [V16QI V8HI V4SI])
29
 
30
;; Vector float modes
31
(define_mode_iterator VEC_F [V4SF V2DF])
32
 
33
;; Vector arithmetic modes
34
(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])
35
 
36
;; Vector modes that need alginment via permutes
37
(define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
38
 
39
;; Vector logical modes
40
(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
41
 
42
;; Vector modes for moves.  Don't do TImode here.
43
(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])
44
 
45
;; Vector modes for types that don't need a realignment under VSX
46
(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])
47
 
48
;; Vector comparison modes
49
(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])
50
 
51
;; Vector init/extract modes
52
(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
53
 
54
;; Vector modes for 64-bit base types
55
(define_mode_iterator VEC_64 [V2DI V2DF])
56
 
57
;; Vector reload iterator
58
(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
59
 
60
;; Base type from vector mode
61
(define_mode_attr VEC_base [(V16QI "QI")
62
                            (V8HI  "HI")
63
                            (V4SI  "SI")
64
                            (V2DI  "DI")
65
                            (V4SF  "SF")
66
                            (V2DF  "DF")
67
                            (TI    "TI")])
68
 
69
;; Same size integer type for floating point data
70
(define_mode_attr VEC_int [(V4SF  "v4si")
71
                           (V2DF  "v2di")])
72
 
73
(define_mode_attr VEC_INT [(V4SF  "V4SI")
74
                           (V2DF  "V2DI")])
75
 
76
;; constants for unspec
77
(define_constants
78
  [(UNSPEC_PREDICATE    400)])
79
 
80
 
81
;; Vector move instructions.
82
(define_expand "mov"
83
  [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
84
        (match_operand:VEC_M 1 "any_operand" ""))]
85
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
86
{
87
  if (can_create_pseudo_p ())
88
    {
89
      if (CONSTANT_P (operands[1])
90
          && !easy_vector_constant (operands[1], mode))
91
        operands[1] = force_const_mem (mode, operands[1]);
92
 
93
      else if (!vlogical_operand (operands[0], mode)
94
               && !vlogical_operand (operands[1], mode))
95
        operands[1] = force_reg (mode, operands[1]);
96
    }
97
})
98
 
99
;; Generic vector floating point load/store instructions.  These will match
100
;; insns defined in vsx.md or altivec.md depending on the switches.
101
(define_expand "vector_load_"
102
  [(set (match_operand:VEC_M 0 "vfloat_operand" "")
103
        (match_operand:VEC_M 1 "memory_operand" ""))]
104
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
105
  "")
106
 
107
(define_expand "vector_store_"
108
  [(set (match_operand:VEC_M 0 "memory_operand" "")
109
        (match_operand:VEC_M 1 "vfloat_operand" ""))]
110
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
111
  "")
112
 
113
;; Splits if a GPR register was chosen for the move
114
(define_split
115
  [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
116
        (match_operand:VEC_L 1 "input_operand" ""))]
117
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
118
   && reload_completed
119
   && gpr_or_gpr_p (operands[0], operands[1])"
120
  [(pc)]
121
{
122
  rs6000_split_multireg_move (operands[0], operands[1]);
123
  DONE;
124
})
125
 
126
 
127
;; Reload patterns for vector operations.  We may need an addtional base
128
;; register to convert the reg+offset addressing to reg+reg for vector
129
;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
130
;; register for gpr registers.
131
(define_expand "reload___store"
132
  [(parallel [(match_operand:VEC_R 0 "memory_operand" "m")
133
              (match_operand:VEC_R 1 "gpc_reg_operand" "r")
134
              (match_operand:P 2 "register_operand" "=&b")])]
135
  ""
136
{
137
  rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
138
  DONE;
139
})
140
 
141
(define_expand "reload___load"
142
  [(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r")
143
              (match_operand:VEC_R 1 "memory_operand" "m")
144
              (match_operand:P 2 "register_operand" "=&b")])]
145
  ""
146
{
147
  rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
148
  DONE;
149
})
150
 
151
;; Reload sometimes tries to move the address to a GPR, and can generate
152
;; invalid RTL for addresses involving AND -16.  Allow addresses involving
153
;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
154
 
155
(define_insn_and_split "*vec_reload_and_plus_"
156
  [(set (match_operand:P 0 "gpc_reg_operand" "=b")
157
        (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
158
                       (match_operand:P 2 "reg_or_cint_operand" "rI"))
159
               (const_int -16)))]
160
  "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
161
  "#"
162
  "&& reload_completed"
163
  [(set (match_dup 0)
164
        (plus:P (match_dup 1)
165
                (match_dup 2)))
166
   (parallel [(set (match_dup 0)
167
                   (and:P (match_dup 0)
168
                          (const_int -16)))
169
              (clobber:CC (scratch:CC))])])
170
 
171
;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16
172
;; address to a register because there is no clobber of a (scratch), so we add
173
;; it here.
174
(define_insn_and_split "*vec_reload_and_reg_"
175
  [(set (match_operand:P 0 "gpc_reg_operand" "=b")
176
        (and:P (match_operand:P 1 "gpc_reg_operand" "r")
177
               (const_int -16)))]
178
  "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
179
  "#"
180
  "&& reload_completed"
181
  [(parallel [(set (match_dup 0)
182
                   (and:P (match_dup 1)
183
                          (const_int -16)))
184
              (clobber:CC (scratch:CC))])])
185
 
186
;; Generic floating point vector arithmetic support
187
(define_expand "add3"
188
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
189
        (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
190
                    (match_operand:VEC_F 2 "vfloat_operand" "")))]
191
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
192
  "")
193
 
194
(define_expand "sub3"
195
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
196
        (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
197
                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
198
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
199
  "")
200
 
201
(define_expand "mul3"
202
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
203
        (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
204
                    (match_operand:VEC_F 2 "vfloat_operand" "")))]
205
  "(VECTOR_UNIT_VSX_P (mode)
206
    || (VECTOR_UNIT_ALTIVEC_P (mode) && TARGET_FUSED_MADD))"
207
  "
208
{
209
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
210
    {
211
      emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
212
      DONE;
213
    }
214
}")
215
 
216
(define_expand "div3"
217
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
218
        (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
219
                   (match_operand:VEC_F 2 "vfloat_operand" "")))]
220
  "VECTOR_UNIT_VSX_P (mode)"
221
  "")
222
 
223
(define_expand "neg2"
224
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
225
        (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
226
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
227
  "
228
{
229
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
230
    {
231
      emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
232
      DONE;
233
    }
234
}")
235
 
236
(define_expand "abs2"
237
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
238
        (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
239
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
240
  "
241
{
242
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
243
    {
244
      emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
245
      DONE;
246
    }
247
}")
248
 
249
(define_expand "smin3"
250
  [(set (match_operand:VEC_F 0 "register_operand" "")
251
        (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
252
                    (match_operand:VEC_F 2 "register_operand" "")))]
253
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
254
  "")
255
 
256
(define_expand "smax3"
257
  [(set (match_operand:VEC_F 0 "register_operand" "")
258
        (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
259
                    (match_operand:VEC_F 2 "register_operand" "")))]
260
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
261
  "")
262
 
263
 
264
(define_expand "sqrt2"
265
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
266
        (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
267
  "VECTOR_UNIT_VSX_P (mode)"
268
  "")
269
 
270
(define_expand "ftrunc2"
271
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
272
        (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
273
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
274
  "")
275
 
276
(define_expand "vector_ceil2"
277
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
278
        (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
279
                      UNSPEC_FRIP))]
280
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
281
  "")
282
 
283
(define_expand "vector_floor2"
284
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
285
        (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
286
                      UNSPEC_FRIM))]
287
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
288
  "")
289
 
290
(define_expand "vector_btrunc2"
291
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
292
        (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
293
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
294
  "")
295
 
296
(define_expand "vector_copysign3"
297
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
298
        (if_then_else:VEC_F
299
         (ge:VEC_F (match_operand:VEC_F 2 "vfloat_operand" "")
300
                   (match_dup 3))
301
         (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" ""))
302
         (neg:VEC_F (abs:VEC_F (match_dup 1)))))]
303
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
304
  "
305
{
306
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
307
    {
308
      emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
309
                                             operands[2]));
310
      DONE;
311
    }
312
 
313
  operands[3] = CONST0_RTX (mode);
314
}")
315
 
316
 
317
;; Vector comparisons
318
(define_expand "vcond"
319
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
320
        (if_then_else:VEC_F
321
         (match_operator 3 "comparison_operator"
322
                         [(match_operand:VEC_F 4 "vfloat_operand" "")
323
                          (match_operand:VEC_F 5 "vfloat_operand" "")])
324
         (match_operand:VEC_F 1 "vfloat_operand" "")
325
         (match_operand:VEC_F 2 "vfloat_operand" "")))]
326
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
327
  "
328
{
329
  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
330
                                    operands[3], operands[4], operands[5]))
331
    DONE;
332
  else
333
    FAIL;
334
}")
335
 
336
(define_expand "vcond"
337
  [(set (match_operand:VEC_I 0 "vint_operand" "")
338
        (if_then_else:VEC_I
339
         (match_operator 3 "comparison_operator"
340
                         [(match_operand:VEC_I 4 "vint_operand" "")
341
                          (match_operand:VEC_I 5 "vint_operand" "")])
342
         (match_operand:VEC_I 1 "vint_operand" "")
343
         (match_operand:VEC_I 2 "vint_operand" "")))]
344
  "VECTOR_UNIT_ALTIVEC_P (mode)"
345
  "
346
{
347
  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
348
                                    operands[3], operands[4], operands[5]))
349
    DONE;
350
  else
351
    FAIL;
352
}")
353
 
354
(define_expand "vcondu"
355
  [(set (match_operand:VEC_I 0 "vint_operand" "")
356
        (if_then_else:VEC_I
357
         (match_operator 3 "comparison_operator"
358
                         [(match_operand:VEC_I 4 "vint_operand" "")
359
                          (match_operand:VEC_I 5 "vint_operand" "")])
360
         (match_operand:VEC_I 1 "vint_operand" "")
361
         (match_operand:VEC_I 2 "vint_operand" "")))]
362
  "VECTOR_UNIT_ALTIVEC_P (mode)"
363
  "
364
{
365
  if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
366
                                    operands[3], operands[4], operands[5]))
367
    DONE;
368
  else
369
    FAIL;
370
}")
371
 
372
(define_expand "vector_eq"
373
  [(set (match_operand:VEC_C 0 "vlogical_operand" "")
374
        (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
375
                  (match_operand:VEC_C 2 "vlogical_operand" "")))]
376
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
377
  "")
378
 
379
(define_expand "vector_gt"
380
  [(set (match_operand:VEC_C 0 "vlogical_operand" "")
381
        (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
382
                  (match_operand:VEC_C 2 "vlogical_operand" "")))]
383
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
384
  "")
385
 
386
(define_expand "vector_ge"
387
  [(set (match_operand:VEC_C 0 "vlogical_operand" "")
388
        (ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
389
                  (match_operand:VEC_C 2 "vlogical_operand" "")))]
390
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
391
  "")
392
 
393
(define_expand "vector_gtu"
394
  [(set (match_operand:VEC_I 0 "vint_operand" "")
395
        (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
396
                   (match_operand:VEC_I 2 "vint_operand" "")))]
397
  "VECTOR_UNIT_ALTIVEC_P (mode)"
398
  "")
399
 
400
(define_expand "vector_geu"
401
  [(set (match_operand:VEC_I 0 "vint_operand" "")
402
        (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
403
                   (match_operand:VEC_I 2 "vint_operand" "")))]
404
  "VECTOR_UNIT_ALTIVEC_P (mode)"
405
  "")
406
 
407
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
408
;; which is in the reverse order that we want
409
(define_expand "vector_select_"
410
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
411
        (if_then_else:VEC_L
412
         (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
413
                (const_int 0))
414
         (match_operand:VEC_L 2 "vlogical_operand" "")
415
         (match_operand:VEC_L 1 "vlogical_operand" "")))]
416
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
417
  "")
418
 
419
(define_expand "vector_select__uns"
420
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
421
        (if_then_else:VEC_L
422
         (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
423
                   (const_int 0))
424
         (match_operand:VEC_L 2 "vlogical_operand" "")
425
         (match_operand:VEC_L 1 "vlogical_operand" "")))]
426
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
427
  "")
428
 
429
;; Expansions that compare vectors producing a vector result and a predicate,
430
;; setting CR6 to indicate a combined status
431
(define_expand "vector_eq__p"
432
  [(parallel
433
    [(set (reg:CC 74)
434
          (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
435
                             (match_operand:VEC_A 2 "vlogical_operand" ""))]
436
                     UNSPEC_PREDICATE))
437
     (set (match_operand:VEC_A 0 "vlogical_operand" "")
438
          (eq:VEC_A (match_dup 1)
439
                    (match_dup 2)))])]
440
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
441
  "")
442
 
443
(define_expand "vector_gt__p"
444
  [(parallel
445
    [(set (reg:CC 74)
446
          (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
447
                             (match_operand:VEC_A 2 "vlogical_operand" ""))]
448
                     UNSPEC_PREDICATE))
449
     (set (match_operand:VEC_A 0 "vlogical_operand" "")
450
          (gt:VEC_A (match_dup 1)
451
                    (match_dup 2)))])]
452
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
453
  "")
454
 
455
(define_expand "vector_ge__p"
456
  [(parallel
457
    [(set (reg:CC 74)
458
          (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
459
                             (match_operand:VEC_F 2 "vfloat_operand" ""))]
460
                     UNSPEC_PREDICATE))
461
     (set (match_operand:VEC_F 0 "vfloat_operand" "")
462
          (ge:VEC_F (match_dup 1)
463
                    (match_dup 2)))])]
464
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
465
  "")
466
 
467
(define_expand "vector_gtu__p"
468
  [(parallel
469
    [(set (reg:CC 74)
470
          (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
471
                              (match_operand:VEC_I 2 "vint_operand" ""))]
472
                     UNSPEC_PREDICATE))
473
     (set (match_operand:VEC_I 0 "vlogical_operand" "")
474
          (gtu:VEC_I (match_dup 1)
475
                     (match_dup 2)))])]
476
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
477
  "")
478
 
479
;; AltiVec/VSX predicates.
480
 
481
(define_expand "cr6_test_for_zero"
482
  [(set (match_operand:SI 0 "register_operand" "=r")
483
        (eq:SI (reg:CC 74)
484
               (const_int 0)))]
485
  "TARGET_ALTIVEC || TARGET_VSX"
486
  "")
487
 
488
(define_expand "cr6_test_for_zero_reverse"
489
  [(set (match_operand:SI 0 "register_operand" "=r")
490
        (eq:SI (reg:CC 74)
491
               (const_int 0)))
492
   (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
493
  "TARGET_ALTIVEC || TARGET_VSX"
494
  "")
495
 
496
(define_expand "cr6_test_for_lt"
497
  [(set (match_operand:SI 0 "register_operand" "=r")
498
        (lt:SI (reg:CC 74)
499
               (const_int 0)))]
500
  "TARGET_ALTIVEC || TARGET_VSX"
501
  "")
502
 
503
(define_expand "cr6_test_for_lt_reverse"
504
  [(set (match_operand:SI 0 "register_operand" "=r")
505
        (lt:SI (reg:CC 74)
506
               (const_int 0)))
507
   (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
508
  "TARGET_ALTIVEC || TARGET_VSX"
509
  "")
510
 
511
 
512
;; Vector logical instructions
513
(define_expand "xor3"
514
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
515
        (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
516
                   (match_operand:VEC_L 2 "vlogical_operand" "")))]
517
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
518
  "")
519
 
520
(define_expand "ior3"
521
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
522
        (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
523
                   (match_operand:VEC_L 2 "vlogical_operand" "")))]
524
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
525
  "")
526
 
527
(define_expand "and3"
528
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
529
        (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
530
                   (match_operand:VEC_L 2 "vlogical_operand" "")))]
531
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
532
  "")
533
 
534
(define_expand "one_cmpl2"
535
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
536
        (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
537
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
538
  "")
539
 
540
(define_expand "nor3"
541
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
542
        (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
543
                              (match_operand:VEC_L 2 "vlogical_operand" ""))))]
544
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
545
  "")
546
 
547
(define_expand "andc3"
548
  [(set (match_operand:VEC_L 0 "vlogical_operand" "")
549
        (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))
550
                   (match_operand:VEC_L 1 "vlogical_operand" "")))]
551
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
552
  "")
553
 
554
;; Same size conversions
555
(define_expand "float2"
556
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
557
        (float:VEC_F (match_operand: 1 "vint_operand" "")))]
558
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
559
  "
560
{
561
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
562
    {
563
      emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
564
      DONE;
565
    }
566
}")
567
 
568
(define_expand "unsigned_float2"
569
  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
570
        (unsigned_float:VEC_F (match_operand: 1 "vint_operand" "")))]
571
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
572
  "
573
{
574
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
575
    {
576
      emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
577
      DONE;
578
    }
579
}")
580
 
581
(define_expand "fix_trunc2"
582
  [(set (match_operand: 0 "vint_operand" "")
583
        (fix: (match_operand:VEC_F 1 "vfloat_operand" "")))]
584
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
585
  "
586
{
587
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
588
    {
589
      emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
590
      DONE;
591
    }
592
}")
593
 
594
(define_expand "fixuns_trunc2"
595
  [(set (match_operand: 0 "vint_operand" "")
596
        (unsigned_fix: (match_operand:VEC_F 1 "vfloat_operand" "")))]
597
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
598
  "
599
{
600
  if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
601
    {
602
      emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
603
      DONE;
604
    }
605
}")
606
 
607
 
608
;; Vector initialization, set, extract
609
(define_expand "vec_init"
610
  [(match_operand:VEC_E 0 "vlogical_operand" "")
611
   (match_operand:VEC_E 1 "" "")]
612
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
613
{
614
  rs6000_expand_vector_init (operands[0], operands[1]);
615
  DONE;
616
})
617
 
618
(define_expand "vec_set"
619
  [(match_operand:VEC_E 0 "vlogical_operand" "")
620
   (match_operand: 1 "register_operand" "")
621
   (match_operand 2 "const_int_operand" "")]
622
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
623
{
624
  rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
625
  DONE;
626
})
627
 
628
(define_expand "vec_extract"
629
  [(match_operand: 0 "register_operand" "")
630
   (match_operand:VEC_E 1 "vlogical_operand" "")
631
   (match_operand 2 "const_int_operand" "")]
632
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
633
{
634
  rs6000_expand_vector_extract (operands[0], operands[1],
635
                                INTVAL (operands[2]));
636
  DONE;
637
})
638
 
639
;; Interleave patterns
640
(define_expand "vec_interleave_highv4sf"
641
  [(set (match_operand:V4SF 0 "vfloat_operand" "")
642
        (vec_merge:V4SF
643
         (vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
644
                          (parallel [(const_int 0)
645
                                     (const_int 2)
646
                                     (const_int 1)
647
                                     (const_int 3)]))
648
         (vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
649
                          (parallel [(const_int 2)
650
                                     (const_int 0)
651
                                     (const_int 3)
652
                                     (const_int 1)]))
653
         (const_int 5)))]
654
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
655
  "")
656
 
657
(define_expand "vec_interleave_lowv4sf"
658
  [(set (match_operand:V4SF 0 "vfloat_operand" "")
659
        (vec_merge:V4SF
660
         (vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
661
                          (parallel [(const_int 2)
662
                                     (const_int 0)
663
                                     (const_int 3)
664
                                     (const_int 1)]))
665
         (vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
666
                          (parallel [(const_int 0)
667
                                     (const_int 2)
668
                                     (const_int 1)
669
                                     (const_int 3)]))
670
         (const_int 5)))]
671
  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
672
  "")
673
 
674
(define_expand "vec_interleave_high"
675
  [(set (match_operand:VEC_64 0 "vfloat_operand" "")
676
        (vec_concat:VEC_64
677
         (vec_select: (match_operand:VEC_64 1 "vfloat_operand" "")
678
                                (parallel [(const_int 0)]))
679
         (vec_select: (match_operand:VEC_64 2 "vfloat_operand" "")
680
                                (parallel [(const_int 0)]))))]
681
  "VECTOR_UNIT_VSX_P (mode)"
682
  "")
683
 
684
(define_expand "vec_interleave_low"
685
  [(set (match_operand:VEC_64 0 "vfloat_operand" "")
686
        (vec_concat:VEC_64
687
         (vec_select: (match_operand:VEC_64 1 "vfloat_operand" "")
688
                                (parallel [(const_int 1)]))
689
         (vec_select: (match_operand:VEC_64 2 "vfloat_operand" "")
690
                                (parallel [(const_int 1)]))))]
691
  "VECTOR_UNIT_VSX_P (mode)"
692
  "")
693
 
694
 
695
;; Convert double word types to single word types
696
(define_expand "vec_pack_trunc_v2df"
697
  [(match_operand:V4SF 0 "vfloat_operand" "")
698
   (match_operand:V2DF 1 "vfloat_operand" "")
699
   (match_operand:V2DF 2 "vfloat_operand" "")]
700
  "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
701
{
702
  rtx r1 = gen_reg_rtx (V4SFmode);
703
  rtx r2 = gen_reg_rtx (V4SFmode);
704
 
705
  emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
706
  emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
707
  emit_insn (gen_vec_extract_evenv4sf (operands[0], r1, r2));
708
  DONE;
709
})
710
 
711
(define_expand "vec_pack_sfix_trunc_v2df"
712
  [(match_operand:V4SI 0 "vint_operand" "")
713
   (match_operand:V2DF 1 "vfloat_operand" "")
714
   (match_operand:V2DF 2 "vfloat_operand" "")]
715
  "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
716
{
717
  rtx r1 = gen_reg_rtx (V4SImode);
718
  rtx r2 = gen_reg_rtx (V4SImode);
719
 
720
  emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
721
  emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
722
  emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
723
  DONE;
724
})
725
 
726
(define_expand "vec_pack_ufix_trunc_v2df"
727
  [(match_operand:V4SI 0 "vint_operand" "")
728
   (match_operand:V2DF 1 "vfloat_operand" "")
729
   (match_operand:V2DF 2 "vfloat_operand" "")]
730
  "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
731
{
732
  rtx r1 = gen_reg_rtx (V4SImode);
733
  rtx r2 = gen_reg_rtx (V4SImode);
734
 
735
  emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
736
  emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
737
  emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
738
  DONE;
739
})
740
 
741
;; Convert single word types to double word
742
(define_expand "vec_unpacks_hi_v4sf"
743
  [(match_operand:V2DF 0 "vfloat_operand" "")
744
   (match_operand:V4SF 1 "vfloat_operand" "")]
745
  "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
746
{
747
  rtx reg = gen_reg_rtx (V4SFmode);
748
 
749
  emit_insn (gen_vec_interleave_highv4sf (reg, operands[1], operands[1]));
750
  emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
751
  DONE;
752
})
753
 
754
(define_expand "vec_unpacks_lo_v4sf"
755
  [(match_operand:V2DF 0 "vfloat_operand" "")
756
   (match_operand:V4SF 1 "vfloat_operand" "")]
757
  "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
758
{
759
  rtx reg = gen_reg_rtx (V4SFmode);
760
 
761
  emit_insn (gen_vec_interleave_lowv4sf (reg, operands[1], operands[1]));
762
  emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
763
  DONE;
764
})
765
 
766
(define_expand "vec_unpacks_float_hi_v4si"
767
  [(match_operand:V2DF 0 "vfloat_operand" "")
768
   (match_operand:V4SI 1 "vint_operand" "")]
769
  "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
770
{
771
  rtx reg = gen_reg_rtx (V4SImode);
772
 
773
  emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
774
  emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
775
  DONE;
776
})
777
 
778
(define_expand "vec_unpacks_float_lo_v4si"
779
  [(match_operand:V2DF 0 "vfloat_operand" "")
780
   (match_operand:V4SI 1 "vint_operand" "")]
781
  "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
782
{
783
  rtx reg = gen_reg_rtx (V4SImode);
784
 
785
  emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
786
  emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
787
  DONE;
788
})
789
 
790
(define_expand "vec_unpacku_float_hi_v4si"
791
  [(match_operand:V2DF 0 "vfloat_operand" "")
792
   (match_operand:V4SI 1 "vint_operand" "")]
793
  "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
794
{
795
  rtx reg = gen_reg_rtx (V4SImode);
796
 
797
  emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
798
  emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
799
  DONE;
800
})
801
 
802
(define_expand "vec_unpacku_float_lo_v4si"
803
  [(match_operand:V2DF 0 "vfloat_operand" "")
804
   (match_operand:V4SI 1 "vint_operand" "")]
805
  "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
806
{
807
  rtx reg = gen_reg_rtx (V4SImode);
808
 
809
  emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
810
  emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
811
  DONE;
812
})
813
 
814
 
815
;; Align vector loads with a permute.
816
(define_expand "vec_realign_load_"
817
  [(match_operand:VEC_K 0 "vlogical_operand" "")
818
   (match_operand:VEC_K 1 "vlogical_operand" "")
819
   (match_operand:VEC_K 2 "vlogical_operand" "")
820
   (match_operand:V16QI 3 "vlogical_operand" "")]
821
  "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
822
{
823
  emit_insn (gen_altivec_vperm_ (operands[0], operands[1], operands[2],
824
                                       operands[3]));
825
  DONE;
826
})
827
 
828
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
829
;; since the load already handles it.
830
(define_expand "movmisalign"
831
 [(set (match_operand:VEC_N 0 "vfloat_operand" "")
832
       (match_operand:VEC_N 1 "vfloat_operand" ""))]
833
 "VECTOR_MEM_VSX_P (mode) && TARGET_ALLOW_MOVMISALIGN"
834
 "")
835
 
836
 
837
;; Vector shift left in bits.  Currently supported ony for shift
838
;; amounts that can be expressed as byte shifts (divisible by 8).
839
;; General shift amounts can be supported using vslo + vsl. We're
840
;; not expecting to see these yet (the vectorizer currently
841
;; generates only shifts divisible by byte_size).
842
(define_expand "vec_shl_"
843
  [(match_operand:VEC_L 0 "vlogical_operand" "")
844
   (match_operand:VEC_L 1 "vlogical_operand" "")
845
   (match_operand:QI 2 "reg_or_short_operand" "")]
846
  "TARGET_ALTIVEC"
847
  "
848
{
849
  rtx bitshift = operands[2];
850
  rtx shift;
851
  rtx insn;
852
  HOST_WIDE_INT bitshift_val;
853
  HOST_WIDE_INT byteshift_val;
854
 
855
  if (! CONSTANT_P (bitshift))
856
    FAIL;
857
  bitshift_val = INTVAL (bitshift);
858
  if (bitshift_val & 0x7)
859
    FAIL;
860
  byteshift_val = bitshift_val >> 3;
861
  if (TARGET_VSX && (byteshift_val & 0x3) == 0)
862
    {
863
      shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
864
      insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1],
865
                                     shift);
866
    }
867
  else
868
    {
869
      shift = gen_rtx_CONST_INT (QImode, byteshift_val);
870
      insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
871
                                        shift);
872
    }
873
 
874
  emit_insn (insn);
875
  DONE;
876
}")
877
 
878
;; Vector shift right in bits. Currently supported ony for shift
879
;; amounts that can be expressed as byte shifts (divisible by 8).
880
;; General shift amounts can be supported using vsro + vsr. We're
881
;; not expecting to see these yet (the vectorizer currently
882
;; generates only shifts divisible by byte_size).
883
(define_expand "vec_shr_"
884
  [(match_operand:VEC_L 0 "vlogical_operand" "")
885
   (match_operand:VEC_L 1 "vlogical_operand" "")
886
   (match_operand:QI 2 "reg_or_short_operand" "")]
887
  "TARGET_ALTIVEC"
888
  "
889
{
890
  rtx bitshift = operands[2];
891
  rtx shift;
892
  rtx insn;
893
  HOST_WIDE_INT bitshift_val;
894
  HOST_WIDE_INT byteshift_val;
895
 
896
  if (! CONSTANT_P (bitshift))
897
    FAIL;
898
  bitshift_val = INTVAL (bitshift);
899
  if (bitshift_val & 0x7)
900
    FAIL;
901
  byteshift_val = 16 - (bitshift_val >> 3);
902
  if (TARGET_VSX && (byteshift_val & 0x3) == 0)
903
    {
904
      shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
905
      insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1],
906
                                     shift);
907
    }
908
  else
909
    {
910
      shift = gen_rtx_CONST_INT (QImode, byteshift_val);
911
      insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
912
                                        shift);
913
    }
914
 
915
  emit_insn (insn);
916
  DONE;
917
}")
918
 
919
;; Expanders for rotate each element in a vector
920
(define_expand "vrotl3"
921
  [(set (match_operand:VEC_I 0 "vint_operand" "")
922
        (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
923
                      (match_operand:VEC_I 2 "vint_operand" "")))]
924
  "TARGET_ALTIVEC"
925
  "")
926
 
927
;; Expanders for arithmetic shift left on each vector element
928
(define_expand "vashl3"
929
  [(set (match_operand:VEC_I 0 "vint_operand" "")
930
        (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
931
                      (match_operand:VEC_I 2 "vint_operand" "")))]
932
  "TARGET_ALTIVEC"
933
  "")
934
 
935
;; Expanders for logical shift right on each vector element
936
(define_expand "vlshr3"
937
  [(set (match_operand:VEC_I 0 "vint_operand" "")
938
        (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
939
                        (match_operand:VEC_I 2 "vint_operand" "")))]
940
  "TARGET_ALTIVEC"
941
  "")
942
 
943
;; Expanders for arithmetic shift right on each vector element
944
(define_expand "vashr3"
945
  [(set (match_operand:VEC_I 0 "vint_operand" "")
946
        (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
947
                        (match_operand:VEC_I 2 "vint_operand" "")))]
948
  "TARGET_ALTIVEC"
949
  "")
950
 
951
;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
952
 
953
(define_expand "absv2sf2"
954
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
955
        (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
956
  "TARGET_PAIRED_FLOAT || TARGET_SPE"
957
  "")
958
 
959
(define_expand "negv2sf2"
960
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
961
        (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
962
  "TARGET_PAIRED_FLOAT || TARGET_SPE"
963
  "")
964
 
965
(define_expand "addv2sf3"
966
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
967
        (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
968
                   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
969
  "TARGET_PAIRED_FLOAT || TARGET_SPE"
970
  "
971
{
972
  if (TARGET_SPE)
973
    {
974
      /* We need to make a note that we clobber SPEFSCR.  */
975
      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
976
 
977
      XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
978
                                         gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
979
      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
980
      emit_insn (par);
981
      DONE;
982
    }
983
}")
984
 
985
(define_expand "subv2sf3"
986
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
987
        (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
988
                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
989
  "TARGET_PAIRED_FLOAT || TARGET_SPE"
990
  "
991
{
992
  if (TARGET_SPE)
993
    {
994
      /* We need to make a note that we clobber SPEFSCR.  */
995
      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
996
 
997
      XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
998
                                         gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
999
      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1000
      emit_insn (par);
1001
      DONE;
1002
    }
1003
}")
1004
 
1005
(define_expand "mulv2sf3"
1006
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1007
        (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1008
                   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1009
  "TARGET_PAIRED_FLOAT || TARGET_SPE"
1010
  "
1011
{
1012
  if (TARGET_SPE)
1013
    {
1014
      /* We need to make a note that we clobber SPEFSCR.  */
1015
      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1016
 
1017
      XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1018
                                         gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
1019
      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1020
      emit_insn (par);
1021
      DONE;
1022
    }
1023
}")
1024
 
1025
(define_expand "divv2sf3"
1026
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1027
        (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1028
                  (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1029
  "TARGET_PAIRED_FLOAT || TARGET_SPE"
1030
  "
1031
{
1032
  if (TARGET_SPE)
1033
    {
1034
      /* We need to make a note that we clobber SPEFSCR.  */
1035
      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1036
 
1037
      XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1038
                                         gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
1039
      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1040
      emit_insn (par);
1041
      DONE;
1042
    }
1043
}")

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.