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jeremybenn |
;; Scheduling description for z900 (cpu 2064).
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;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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;; Ulrich Weigand (uweigand@de.ibm.com).
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it under
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;; the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 3, or (at your option) any later
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;; version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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;; for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;
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;; References:
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;; The microarchitecture of the IBM eServer z900 processor.
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;; E.M. Schwarz et al.
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;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
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;;
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;; z900 (cpu 2064) pipeline
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;;
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;; dec
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;; --> | <---
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;; LA bypass | agen |
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;; | | |
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;; --- c1 | Load bypass
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;; | |
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;; c2----
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;; |
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;; e1
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;; |
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;; wr
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;; This scheduler description is also used for the g5 and g6.
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(define_automaton "z_ipu")
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(define_cpu_unit "z_e1" "z_ipu")
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(define_cpu_unit "z_wr" "z_ipu")
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(define_insn_reservation "z_la" 1
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "la"))
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"z_e1,z_wr")
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(define_insn_reservation "z_larl" 1
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "larl"))
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"z_e1,z_wr")
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(define_insn_reservation "z_load" 1
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "load"))
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"z_e1,z_wr")
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(define_insn_reservation "z_store" 1
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "store"))
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"z_e1,z_wr")
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(define_insn_reservation "z_sem" 2
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "sem"))
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"z_e1*2,z_wr")
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(define_insn_reservation "z_call" 5
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "jsr"))
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"z_e1*5,z_wr")
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(define_insn_reservation "z_mul" 5
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(and (eq_attr "cpu" "g5,g6,z900")
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(eq_attr "type" "imulsi,imulhi"))
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"z_e1*5,z_wr")
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(define_insn_reservation "z_inf" 10
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(and (eq_attr "cpu" "g5,g6,z900")
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(eq_attr "type" "idiv,imuldi"))
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"z_e1*10,z_wr")
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;; For everything else we check the atype flag.
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(define_insn_reservation "z_int" 1
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(and (eq_attr "cpu" "z900,g5,g6")
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(and (not (eq_attr "type" "la,larl,load,store,jsr"))
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(eq_attr "atype" "reg")))
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"z_e1,z_wr")
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(define_insn_reservation "z_agen" 1
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(and (eq_attr "cpu" "z900,g5,g6")
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(and (not (eq_attr "type" "la,larl,load,store,jsr"))
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(eq_attr "atype" "agen")))
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"z_e1,z_wr")
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;;
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;; s390_agen_dep_p returns 1, if a register is set in the
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;; first insn and used in the dependent insn to form a address.
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;;
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;;
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;; If an instruction uses a register to address memory, it needs
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;; to be set 5 cycles in advance.
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;;
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(define_bypass 5 "z_int,z_agen"
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"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
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;;
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;; A load type instruction uses a bypass to feed the result back
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;; to the address generation pipeline stage.
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;;
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(define_bypass 3 "z_load"
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"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
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;;
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;; A load address type instruction uses a bypass to feed the
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;; result back to the address generation pipeline stage.
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;;
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(define_bypass 2 "z_larl,z_la"
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"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
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