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jeremybenn |
;; Scheduling description for SuperSPARC.
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;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; The SuperSPARC is a tri-issue, which was considered quite parallel
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;; at the time it was released. Much like UltraSPARC-I and UltraSPARC-II
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;; there are two integer units but only one of them may take shifts.
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;;
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;; ??? If SuperSPARC has the same slotting rules as ultrasparc for these
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;; ??? shifts, we should model that.
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(define_automaton "supersparc_0,supersparc_1")
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(define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0")
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(define_cpu_unit "ss_fpalu" "supersparc_0")
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(define_cpu_unit "ss_fpmds" "supersparc_1")
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(define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)")
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(define_insn_reservation "ss_iuload" 1
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "load,sload"))
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"ss_memory")
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;; Ok, fpu loads deliver the result in zero cycles. But we
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;; have to show the ss_memory reservation somehow, thus...
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(define_insn_reservation "ss_fpload" 0
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fpload"))
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"ss_memory")
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(define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt")
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(define_insn_reservation "ss_store" 1
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "store,fpstore"))
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"ss_memory")
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(define_insn_reservation "ss_ialu_shift" 1
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "shift"))
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"ss_shift + ss_iwport")
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(define_insn_reservation "ss_ialu_any" 1
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "load,sload,store,shift,ialu"))
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"ss_iwport")
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(define_insn_reservation "ss_fp_alu" 3
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fp,fpmove,fpcmp"))
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"ss_fpalu, nothing*2")
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(define_insn_reservation "ss_fp_mult" 3
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fpmul"))
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"ss_fpmds, nothing*2")
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(define_insn_reservation "ss_fp_divs" 6
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fpdivs"))
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"ss_fpmds*4, nothing*2")
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(define_insn_reservation "ss_fp_divd" 9
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fpdivd"))
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"ss_fpmds*7, nothing*2")
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(define_insn_reservation "ss_fp_sqrt" 12
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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"ss_fpmds*10, nothing*2")
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(define_insn_reservation "ss_imul" 4
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "imul"))
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"ss_fpmds*4")
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