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jeremybenn |
/* Copyright (C) 2006, 2008, 2009 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This file is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef __SPU_MFCIO_H__
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#define __SPU_MFCIO_H__ 1
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#include <spu_intrinsics.h>
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#ifdef __IN_LIBGCC2
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typedef unsigned long long uint64_t;
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#else
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#include <stdint.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/****************************************************************/
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/* DMA list element structure*/
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/****************************************************************/
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#ifdef __GNUC__
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__extension__
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#endif
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typedef struct mfc_list_element {
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uint64_t notify : 1; /** Stall-and-notify bit */
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uint64_t reserved : 16;
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uint64_t size : 15; /** Transfer size */
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uint64_t eal : 32; /** Lower word of effective address */
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} mfc_list_element_t;
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/****************************************************************/
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/* DMA max/min size definitions. */
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/****************************************************************/
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#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
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#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
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#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
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#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
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#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
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#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
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#define MFC_MIN_DMA_LIST_ELEMENTS 1
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#define MFC_MAX_DMA_LIST_ELEMENTS 2048
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#define MFC_MIN_DMA_LIST_SIZE (MFC_MIN_DMA_LIST_ELEMENTS << 3) /* 8 bytes */
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#define MFC_MAX_DMA_LIST_SIZE (MFC_MAX_DMA_LIST_ELEMENTS << 3) /* 16K bytes */
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/****************************************************************/
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/* MFC DMA command modifiers to identify classes of operations. */
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/****************************************************************/
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/* Note: These commands modifier may be used in conjunction with the base
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command types (i.e. MFC_PUT_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
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to construct the various command permutations. */
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#define MFC_BARRIER_ENABLE 0x0001
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#define MFC_FENCE_ENABLE 0x0002
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#define MFC_LIST_ENABLE 0x0004
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#define MFC_RESULT_ENABLE 0x0010
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/****************************************************************/
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/* MFC DMA Put Commands */
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/****************************************************************/
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#define MFC_PUT_CMD 0x0020
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#define MFC_PUTB_CMD (MFC_PUT_CMD | MFC_BARRIER_ENABLE)
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#define MFC_PUTF_CMD (MFC_PUT_CMD | MFC_FENCE_ENABLE)
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#define MFC_PUTL_CMD (MFC_PUT_CMD | MFC_LIST_ENABLE)
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#define MFC_PUTLB_CMD (MFC_PUTL_CMD | MFC_BARRIER_ENABLE)
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#define MFC_PUTLF_CMD (MFC_PUTL_CMD | MFC_FENCE_ENABLE)
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#define MFC_PUTR_CMD (MFC_PUT_CMD | MFC_RESULT_ENABLE)
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#define MFC_PUTRB_CMD (MFC_PUTR_CMD | MFC_BARRIER_ENABLE)
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#define MFC_PUTRF_CMD (MFC_PUTR_CMD | MFC_FENCE_ENABLE)
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#define MFC_PUTRL_CMD (MFC_PUTR_CMD | MFC_LIST_ENABLE)
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#define MFC_PUTRLB_CMD (MFC_PUTRL_CMD | MFC_BARRIER_ENABLE)
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#define MFC_PUTRLF_CMD (MFC_PUTRL_CMD | MFC_FENCE_ENABLE)
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/****************************************************************/
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/* MFC DMA Get Commands */
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/****************************************************************/
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#define MFC_GET_CMD 0x0040
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#define MFC_GETB_CMD (MFC_GET_CMD | MFC_BARRIER_ENABLE)
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#define MFC_GETF_CMD (MFC_GET_CMD | MFC_FENCE_ENABLE)
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#define MFC_GETL_CMD (MFC_GET_CMD | MFC_LIST_ENABLE)
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#define MFC_GETLB_CMD (MFC_GETL_CMD | MFC_BARRIER_ENABLE)
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#define MFC_GETLF_CMD (MFC_GETL_CMD | MFC_FENCE_ENABLE)
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/****************************************************************/
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/* MFC Synchronization Commands */
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/****************************************************************/
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#define MFC_SNDSIG_CMD 0x00A0
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#define MFC_SNDSIGB_CMD (MFC_SNDSIG_CMD | MFC_BARRIER_ENABLE)
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#define MFC_SNDSIGF_CMD (MFC_SNDSIG_CMD | MFC_FENCE_ENABLE)
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#define MFC_BARRIER_CMD 0x00C0
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#define MFC_EIEIO_CMD 0x00C8
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#define MFC_SYNC_CMD 0x00CC
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/****************************************************************/
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/* MFC Atomic Commands */
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/****************************************************************/
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#define MFC_GETLLAR_CMD 0x00D0
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#define MFC_PUTLLC_CMD 0x00B4
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#define MFC_PUTLLUC_CMD 0x00B0
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#define MFC_PUTQLLUC_CMD 0x00B8
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/****************************************************************/
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/* MFC SL1 Storage Control Commands */
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/****************************************************************/
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#define MFC_SDCRT_CMD 0x0080
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#define MFC_SDCRTST_CMD 0x0081
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#define MFC_SDCRZ_CMD 0x0089
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#define MFC_SDCRST_CMD 0x008D
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#define MFC_SDCRF_CMD 0x008F
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/****************************************************************/
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/* Channel Defines */
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/****************************************************************/
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/* Events Defines for channels
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* 0 (SPU_RdEventStat),
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* 1 (SPU_WrEventMask), and
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* 2 (SPU_WrEventAck).
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*/
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#define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
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#define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
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#define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
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#define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
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#define MFC_DECREMENTER_EVENT 0x00000020
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#define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
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#define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
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#define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
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#define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
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#define MFC_LLR_LOST_EVENT 0x00000400
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#define MFC_PRIV_ATTN_EVENT 0x00000800
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#define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
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/* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */
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#define MFC_TAG_UPDATE_IMMEDIATE 0x0
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#define MFC_TAG_UPDATE_ANY 0x1
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#define MFC_TAG_UPDATE_ALL 0x2
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/* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */
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#define MFC_PUTLLC_STATUS 0x00000001
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#define MFC_PUTLLUC_STATUS 0x00000002
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#define MFC_GETLLAR_STATUS 0x00000004
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/****************************************************************/
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/* Definitions for constructing a 32-bit command word */
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/* including the transfer and replacement class id and the */
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/* command opcode. */
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/****************************************************************/
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#define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd))
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/* Addressing Utilities */
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#define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32)
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#define mfc_ea2l(ea) (unsigned int)(ea)
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#define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\
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si_rotqbyi(si_from_uint(l), -4),\
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si_fsmbi(0x0f0f)))
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#define mfc_ceil128(v) (((v) + 127) & ~127)
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/* MFC DMA */
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#define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD))
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#define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD))
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#define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD))
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#define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD))
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#define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD))
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#define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD))
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/* MFC list DMA */
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#define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD))
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#define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD))
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#define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD))
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#define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD))
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#define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD))
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#define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD))
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/* MFC Atomic Update DMA */
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#define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD))
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#define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD))
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#define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD))
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#define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD))
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/* MFC Synchronization Commands */
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#define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD))
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#define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD))
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#define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD))
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#define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD)
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#define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD))
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#define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD)
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/* MFC SL1 Storage Control Commands */
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#define mfc_sdcrt( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRT_CMD))
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#define mfc_sdcrtst(ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRTST_CMD))
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#define mfc_sdcrz( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRZ_CMD))
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#define mfc_sdcrst( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRST_CMD))
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#define mfc_sdcrf( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRF_CMD))
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/* DMA Queue */
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#define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd)
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/* MFC Tag-Status */
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#define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
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#define mfc_read_tag_mask() spu_readch(MFC_RdTagMask)
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#define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
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#define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE)
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#define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY)
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#define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL)
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#define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate)
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#define mfc_read_tag_status() spu_readch(MFC_RdTagStat)
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#define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status())
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#define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status())
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#define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status())
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#define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat)
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/* MFC List Stall-and-Notify Tag */
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| 248 |
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#define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat)
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| 249 |
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#define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat)
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| 250 |
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#define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
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| 251 |
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| 252 |
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/* Atomic DMA */
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| 253 |
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#define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat)
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| 254 |
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#define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat)
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| 255 |
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|
| 256 |
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/* MFC Multi-source Synchronization */
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| 257 |
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#define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
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| 258 |
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#define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq)
|
| 259 |
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| 260 |
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/* SPU Signal */
|
| 261 |
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#define spu_read_signal1() spu_readch(SPU_RdSigNotify1)
|
| 262 |
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#define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1)
|
| 263 |
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#define spu_read_signal2() spu_readch(SPU_RdSigNotify2)
|
| 264 |
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#define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2)
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| 265 |
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|
| 266 |
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/* SPU/PPE Mailbox */
|
| 267 |
|
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#define spu_read_in_mbox() spu_readch(SPU_RdInMbox)
|
| 268 |
|
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#define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox)
|
| 269 |
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#define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
|
| 270 |
|
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#define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox)
|
| 271 |
|
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#define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
|
| 272 |
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#define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox)
|
| 273 |
|
|
|
| 274 |
|
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/* SPU Decrementer */
|
| 275 |
|
|
#define spu_read_decrementer() spu_readch(SPU_RdDec)
|
| 276 |
|
|
#define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
|
| 277 |
|
|
|
| 278 |
|
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/* SPU Event */
|
| 279 |
|
|
#define spu_read_event_status() spu_readch(SPU_RdEventStat)
|
| 280 |
|
|
#define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat)
|
| 281 |
|
|
#define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
|
| 282 |
|
|
#define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
|
| 283 |
|
|
#define spu_read_event_mask() spu_readch(SPU_RdEventMask)
|
| 284 |
|
|
|
| 285 |
|
|
/* SPU State Management */
|
| 286 |
|
|
#define spu_read_machine_status() spu_readch(SPU_RdMachStat)
|
| 287 |
|
|
#define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
|
| 288 |
|
|
#define spu_read_srr0() spu_readch(SPU_RdSRR0)
|
| 289 |
|
|
|
| 290 |
|
|
/* Interrupt-Safe Critical Sections */
|
| 291 |
|
|
|
| 292 |
|
|
static __inline__ unsigned int mfc_begin_critical_section (void)
|
| 293 |
|
|
__attribute__ ((__always_inline__));
|
| 294 |
|
|
|
| 295 |
|
|
static __inline__ unsigned int
|
| 296 |
|
|
mfc_begin_critical_section (void)
|
| 297 |
|
|
{
|
| 298 |
|
|
#ifdef SPU_MFCIO_INTERRUPT_SAFE
|
| 299 |
|
|
unsigned int __status = spu_read_machine_status ();
|
| 300 |
|
|
spu_idisable ();
|
| 301 |
|
|
return __status;
|
| 302 |
|
|
#else
|
| 303 |
|
|
return 0;
|
| 304 |
|
|
#endif
|
| 305 |
|
|
}
|
| 306 |
|
|
|
| 307 |
|
|
static __inline__ void mfc_end_critical_section (unsigned int)
|
| 308 |
|
|
__attribute__ ((__always_inline__));
|
| 309 |
|
|
|
| 310 |
|
|
static __inline__ void
|
| 311 |
|
|
mfc_end_critical_section (unsigned int __status __attribute__ ((__unused__)))
|
| 312 |
|
|
{
|
| 313 |
|
|
#ifdef SPU_MFCIO_INTERRUPT_SAFE
|
| 314 |
|
|
if (__status & 1)
|
| 315 |
|
|
spu_ienable ();
|
| 316 |
|
|
#endif
|
| 317 |
|
|
}
|
| 318 |
|
|
|
| 319 |
|
|
/* MFC Tag Manager */
|
| 320 |
|
|
|
| 321 |
|
|
#define MFC_TAG_INVALID 0xFFFFFFFF
|
| 322 |
|
|
#define MFC_TAG_VALID 0x00000000
|
| 323 |
|
|
|
| 324 |
|
|
#define mfc_tag_reserve() \
|
| 325 |
|
|
__mfc_tag_reserve()
|
| 326 |
|
|
#define mfc_tag_release(tag) \
|
| 327 |
|
|
__mfc_tag_release((tag))
|
| 328 |
|
|
#define mfc_multi_tag_reserve(nr_tags) \
|
| 329 |
|
|
__mfc_multi_tag_reserve((nr_tags))
|
| 330 |
|
|
#define mfc_multi_tag_release(tag, nr_tags) \
|
| 331 |
|
|
__mfc_multi_tag_release((tag),(nr_tags))
|
| 332 |
|
|
|
| 333 |
|
|
extern unsigned int __mfc_tag_reserve (void);
|
| 334 |
|
|
extern unsigned int __mfc_tag_release (unsigned int);
|
| 335 |
|
|
extern unsigned int __mfc_multi_tag_reserve (unsigned int);
|
| 336 |
|
|
extern unsigned int __mfc_multi_tag_release (unsigned int, unsigned int);
|
| 337 |
|
|
|
| 338 |
|
|
#ifdef __cplusplus
|
| 339 |
|
|
}
|
| 340 |
|
|
#endif
|
| 341 |
|
|
|
| 342 |
|
|
#endif /* __SPU_MFCIO_H__ */
|
