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1 282 jeremybenn
;; Predicate definitions for NEC V850.
2
;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
;;
6
;; GCC is free software; you can redistribute it and/or modify
7
;; it under the terms of the GNU General Public License as published by
8
;; the Free Software Foundation; either version 3, or (at your option)
9
;; any later version.
10
;;
11
;; GCC is distributed in the hope that it will be useful,
12
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
;; GNU General Public License for more details.
15
;;
16
;; You should have received a copy of the GNU General Public License
17
;; along with GCC; see the file COPYING3.  If not see
18
;; .
19
 
20
;; Return true if OP is either a register or 0.
21
 
22
(define_predicate "reg_or_0_operand"
23
  (match_code "reg,subreg,const_int,const_double")
24
{
25
  if (GET_CODE (op) == CONST_INT)
26
    return INTVAL (op) == 0;
27
 
28
  else if (GET_CODE (op) == CONST_DOUBLE)
29
    return CONST_DOUBLE_OK_FOR_G (op);
30
 
31
  else
32
    return register_operand (op, mode);
33
})
34
 
35
;; Return true if OP is either a register or a signed five bit
36
;; integer.
37
 
38
(define_predicate "reg_or_int5_operand"
39
  (match_code "reg,subreg,const_int")
40
{
41
  if (GET_CODE (op) == CONST_INT)
42
    return CONST_OK_FOR_J (INTVAL (op));
43
 
44
  else
45
    return register_operand (op, mode);
46
})
47
 
48
;; Return true if OP is either a register or a signed nine bit
49
;; integer.
50
 
51
(define_predicate "reg_or_int9_operand"
52
  (match_code "reg,subreg,const_int")
53
{
54
  if (GET_CODE (op) == CONST_INT)
55
    return CONST_OK_FOR_O (INTVAL (op));
56
 
57
  return register_operand (op, mode);
58
})
59
 
60
;; Return true if OP is either a register or a const integer.
61
 
62
(define_predicate "reg_or_const_operand"
63
  (match_code "reg,const_int")
64
{
65
  if (GET_CODE (op) == CONST_INT)
66
    return TRUE;
67
 
68
  return register_operand (op, mode);
69
})
70
 
71
;; Return true if OP is a valid call operand.
72
 
73
(define_predicate "call_address_operand"
74
  (match_code "reg,symbol_ref")
75
{
76
  /* Only registers are valid call operands if TARGET_LONG_CALLS.  */
77
  if (TARGET_LONG_CALLS)
78
    return GET_CODE (op) == REG;
79
  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
80
})
81
 
82
;; TODO: Add a comment here.
83
 
84
(define_predicate "movsi_source_operand"
85
  (match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
86
{
87
  /* Some constants, as well as symbolic operands
88
     must be done with HIGH & LO_SUM patterns.  */
89
  if (CONSTANT_P (op)
90
      && GET_CODE (op) != HIGH
91
      && !(GET_CODE (op) == CONST_INT
92
           && (CONST_OK_FOR_J (INTVAL (op))
93
               || CONST_OK_FOR_K (INTVAL (op))
94
               || CONST_OK_FOR_L (INTVAL (op)))))
95
    return special_symbolref_operand (op, mode);
96
  else
97
    return general_operand (op, mode);
98
})
99
 
100
;; TODO: Add a comment here.
101
 
102
(define_predicate "special_symbolref_operand"
103
  (match_code "symbol_ref")
104
{
105
  if (GET_CODE (op) == CONST
106
      && GET_CODE (XEXP (op, 0)) == PLUS
107
      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
108
      && CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))))
109
    op = XEXP (XEXP (op, 0), 0);
110
 
111
  if (GET_CODE (op) == SYMBOL_REF)
112
    return (SYMBOL_REF_FLAGS (op)
113
            & (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
114
 
115
  return FALSE;
116
})
117
 
118
;; TODO: Add a comment here.
119
 
120
(define_predicate "power_of_two_operand"
121
  (match_code "const_int")
122
{
123
  if (GET_CODE (op) != CONST_INT)
124
    return 0;
125
 
126
  if (exact_log2 (INTVAL (op)) == -1)
127
    return 0;
128
  return 1;
129
})
130
 
131
;; Return nonzero if the given RTX is suitable for collapsing into a
132
;; jump to a function prologue.
133
 
134
(define_predicate "pattern_is_ok_for_prologue"
135
  (match_code "parallel")
136
{
137
  int count = XVECLEN (op, 0);
138
  int i;
139
  rtx vector_element;
140
 
141
  /* If there are no registers to save then the function prologue
142
     is not suitable.  */
143
  if (count <= 2)
144
    return 0;
145
 
146
  /* The pattern matching has already established that we are adjusting the
147
     stack and pushing at least one register.  We must now check that the
148
     remaining entries in the vector to make sure that they are also register
149
     pushes, except for the last entry which should be a CLOBBER of r10.
150
 
151
     The test below performs the C equivalent of this machine description
152
     pattern match:
153
 
154
     (set (mem:SI (plus:SI (reg:SI 3)
155
      (match_operand:SI 2 "immediate_operand" "i")))
156
      (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
157
 
158
     */
159
 
160
  for (i = 2; i < count - (TARGET_LONG_CALLS ? 2: 1); i++)
161
    {
162
      rtx dest;
163
      rtx src;
164
      rtx plus;
165
 
166
      vector_element = XVECEXP (op, 0, i);
167
 
168
      if (GET_CODE (vector_element) != SET)
169
        return 0;
170
 
171
      dest = SET_DEST (vector_element);
172
      src = SET_SRC (vector_element);
173
 
174
      if (GET_CODE (dest) != MEM
175
          || GET_MODE (dest) != SImode
176
          || GET_CODE (src) != REG
177
          || GET_MODE (src) != SImode
178
          || ! register_is_ok_for_epilogue (src, SImode))
179
        return 0;
180
 
181
      plus = XEXP (dest, 0);
182
 
183
      if ( GET_CODE (plus) != PLUS
184
          || GET_CODE (XEXP (plus, 0)) != REG
185
          || GET_MODE (XEXP (plus, 0)) != SImode
186
          || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
187
          || GET_CODE (XEXP (plus, 1)) != CONST_INT)
188
        return 0;
189
 
190
      /* If the register is being pushed somewhere other than the stack
191
         space just acquired by the first operand then abandon this quest.
192
         Note: the test is <= because both values are negative.  */
193
      if (INTVAL (XEXP (plus, 1))
194
          <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
195
        {
196
          return 0;
197
        }
198
    }
199
 
200
  /* Make sure that the last entries in the vector are clobbers.  */
201
  for (; i < count; i++)
202
    {
203
      vector_element = XVECEXP (op, 0, i);
204
 
205
      if (GET_CODE (vector_element) != CLOBBER
206
          || GET_CODE (XEXP (vector_element, 0)) != REG
207
          || !(REGNO (XEXP (vector_element, 0)) == 10
208
               || (TARGET_LONG_CALLS ? (REGNO (XEXP (vector_element, 0)) == 11) : 0 )))
209
        return 0;
210
    }
211
 
212
  return 1;
213
})
214
 
215
;; Return nonzero if the given RTX is suitable for collapsing into
216
;; jump to a function epilogue.
217
 
218
(define_predicate "pattern_is_ok_for_epilogue"
219
  (match_code "parallel")
220
{
221
  int count = XVECLEN (op, 0);
222
  int i;
223
 
224
  /* If there are no registers to restore then the function epilogue
225
     is not suitable.  */
226
  if (count <= 2)
227
    return 0;
228
 
229
  /* The pattern matching has already established that we are performing a
230
     function epilogue and that we are popping at least one register.  We must
231
     now check the remaining entries in the vector to make sure that they are
232
     also register pops.  There is no good reason why there should ever be
233
     anything else in this vector, but being paranoid always helps...
234
 
235
     The test below performs the C equivalent of this machine description
236
     pattern match:
237
 
238
        (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
239
          (mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
240
     */
241
 
242
  for (i = 3; i < count; i++)
243
    {
244
      rtx vector_element = XVECEXP (op, 0, i);
245
      rtx dest;
246
      rtx src;
247
      rtx plus;
248
 
249
      if (GET_CODE (vector_element) != SET)
250
        return 0;
251
 
252
      dest = SET_DEST (vector_element);
253
      src = SET_SRC (vector_element);
254
 
255
      if (GET_CODE (dest) != REG
256
          || GET_MODE (dest) != SImode
257
          || ! register_is_ok_for_epilogue (dest, SImode)
258
          || GET_CODE (src) != MEM
259
          || GET_MODE (src) != SImode)
260
        return 0;
261
 
262
      plus = XEXP (src, 0);
263
 
264
      if (GET_CODE (plus) != PLUS
265
          || GET_CODE (XEXP (plus, 0)) != REG
266
          || GET_MODE (XEXP (plus, 0)) != SImode
267
          || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
268
          || GET_CODE (XEXP (plus, 1)) != CONST_INT)
269
        return 0;
270
    }
271
 
272
  return 1;
273
})
274
 
275
;; Return true if the given RTX is a register which can be restored by
276
;; a function epilogue.
277
 
278
(define_predicate "register_is_ok_for_epilogue"
279
  (match_code "reg")
280
{
281
  /* The save/restore routines can only cope with registers 20 - 31.  */
282
  return ((GET_CODE (op) == REG)
283
          && (((REGNO (op) >= 20) && REGNO (op) <= 31)));
284
})
285
 
286
;; Return nonzero if the given RTX is suitable for collapsing into a
287
;; DISPOSE instruction.
288
 
289
(define_predicate "pattern_is_ok_for_dispose"
290
  (match_code "parallel")
291
{
292
  int count = XVECLEN (op, 0);
293
  int i;
294
 
295
  /* If there are no registers to restore then
296
     the dispose instruction is not suitable.  */
297
  if (count <= 2)
298
    return 0;
299
 
300
  /* The pattern matching has already established that we are performing a
301
     function epilogue and that we are popping at least one register.  We must
302
     now check the remaining entries in the vector to make sure that they are
303
     also register pops.  There is no good reason why there should ever be
304
     anything else in this vector, but being paranoid always helps...
305
 
306
     The test below performs the C equivalent of this machine description
307
     pattern match:
308
 
309
        (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
310
          (mem:SI (plus:SI (reg:SI 3)
311
            (match_operand:SI n "immediate_operand" "i"))))
312
     */
313
 
314
  for (i = 3; i < count; i++)
315
    {
316
      rtx vector_element = XVECEXP (op, 0, i);
317
      rtx dest;
318
      rtx src;
319
      rtx plus;
320
 
321
      if (GET_CODE (vector_element) != SET)
322
        return 0;
323
 
324
      dest = SET_DEST (vector_element);
325
      src  = SET_SRC (vector_element);
326
 
327
      if (   GET_CODE (dest) != REG
328
          || GET_MODE (dest) != SImode
329
          || ! register_is_ok_for_epilogue (dest, SImode)
330
          || GET_CODE (src) != MEM
331
          || GET_MODE (src) != SImode)
332
        return 0;
333
 
334
      plus = XEXP (src, 0);
335
 
336
      if (   GET_CODE (plus) != PLUS
337
          || GET_CODE (XEXP (plus, 0)) != REG
338
          || GET_MODE (XEXP (plus, 0)) != SImode
339
          || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
340
          || GET_CODE (XEXP (plus, 1)) != CONST_INT)
341
        return 0;
342
    }
343
 
344
  return 1;
345
})
346
 
347
;; Return nonzero if the given RTX is suitable for collapsing into a
348
;; PREPARE instruction.
349
 
350
(define_predicate "pattern_is_ok_for_prepare"
351
  (match_code "parallel")
352
{
353
  int count = XVECLEN (op, 0);
354
  int i;
355
 
356
  /* If there are no registers to restore then the prepare instruction
357
     is not suitable.  */
358
  if (count <= 1)
359
    return 0;
360
 
361
  /* The pattern matching has already established that we are adjusting the
362
     stack and pushing at least one register.  We must now check that the
363
     remaining entries in the vector to make sure that they are also register
364
     pushes.
365
 
366
     The test below performs the C equivalent of this machine description
367
     pattern match:
368
 
369
     (set (mem:SI (plus:SI (reg:SI 3)
370
       (match_operand:SI 2 "immediate_operand" "i")))
371
         (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
372
 
373
     */
374
 
375
  for (i = 2; i < count; i++)
376
    {
377
      rtx vector_element = XVECEXP (op, 0, i);
378
      rtx dest;
379
      rtx src;
380
      rtx plus;
381
 
382
      if (GET_CODE (vector_element) != SET)
383
        return 0;
384
 
385
      dest = SET_DEST (vector_element);
386
      src  = SET_SRC (vector_element);
387
 
388
      if (   GET_CODE (dest) != MEM
389
          || GET_MODE (dest) != SImode
390
          || GET_CODE (src) != REG
391
          || GET_MODE (src) != SImode
392
          || ! register_is_ok_for_epilogue (src, SImode)
393
             )
394
        return 0;
395
 
396
      plus = XEXP (dest, 0);
397
 
398
      if (   GET_CODE (plus) != PLUS
399
          || GET_CODE (XEXP (plus, 0)) != REG
400
          || GET_MODE (XEXP (plus, 0)) != SImode
401
          || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
402
          || GET_CODE (XEXP (plus, 1)) != CONST_INT)
403
        return 0;
404
 
405
      /* If the register is being pushed somewhere other than the stack
406
         space just acquired by the first operand then abandon this quest.
407
         Note: the test is <= because both values are negative.  */
408
      if (INTVAL (XEXP (plus, 1))
409
          <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
410
        return 0;
411
    }
412
 
413
  return 1;
414
})
415
 
416
;; TODO: Add a comment here.
417
 
418
(define_predicate "not_power_of_two_operand"
419
  (match_code "const_int")
420
{
421
  unsigned int mask;
422
 
423
  if (mode == QImode)
424
    mask = 0xff;
425
  else if (mode == HImode)
426
    mask = 0xffff;
427
  else if (mode == SImode)
428
    mask = 0xffffffff;
429
  else
430
    return 0;
431
 
432
  if (GET_CODE (op) != CONST_INT)
433
    return 0;
434
 
435
  if (exact_log2 (~INTVAL (op) & mask) == -1)
436
    return 0;
437
  return 1;
438
})

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