OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [vax/] [lib1funcs.asm] - Blame information for rev 461

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn
/* Copyright (C) 2009 Free Software Foundation, Inc.
2
   This file is part of GCC.
3
   Contributed by Maciej W. Rozycki .
4
 
5
   This file is free software; you can redistribute it and/or modify it
6
   under the terms of the GNU General Public License as published by the
7
   Free Software Foundation; either version 3, or (at your option) any
8
   later version.
9
 
10
   This file is distributed in the hope that it will be useful, but
11
   WITHOUT ANY WARRANTY; without even the implied warranty of
12
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
   General Public License for more details.
14
 
15
   Under Section 7 of GPL version 3, you are granted additional
16
   permissions described in the GCC Runtime Library Exception, version
17
   3.1, as published by the Free Software Foundation.
18
 
19
   You should have received a copy of the GNU General Public License and
20
   a copy of the GCC Runtime Library Exception along with this program;
21
   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
22
   .  */
23
 
24
#ifdef L_udivsi3
25
        .text
26
        .globl  __udivsi3
27
        .type   __udivsi3, @function
28
__udivsi3:
29
        .word   0
30
        movl    8(%ap), %r1
31
        blss    0f                      /* Check bit #31 of divisor.  */
32
        movl    4(%ap), %r2
33
        blss    1f                      /* Check bit #31 of dividend.  */
34
 
35
        /* Both zero, do a standard division.  */
36
 
37
        divl3   %r1, %r2, %r0
38
        ret
39
 
40
        /* MSB of divisor set, only 1 or 0 may result.  */
41
0:
42
        decl    %r1
43
        clrl    %r0
44
        cmpl    %r1, 4(%ap)
45
        adwc    $0, %r0
46
        ret
47
 
48
        /* MSB of dividend set, do an extended division.  */
49
1:
50
        clrl    %r3
51
        ediv    %r1, %r2, %r0, %r3
52
        ret
53
        .size   __udivsi3, . - __udivsi3
54
        .previous
55
#endif
56
 
57
#ifdef L_umodsi3
58
        .text
59
        .globl  __umodsi3
60
        .type   __umodsi3, @function
61
__umodsi3:
62
        .word   0
63
        movl    8(%ap), %r1
64
        blss    0f                      /* Check bit #31 of divisor.  */
65
        movl    4(%ap), %r2
66
        blss    1f                      /* Check bit #31 of dividend.  */
67
 
68
        /* Both zero, do a standard division.  */
69
 
70
        divl3   %r1, %r2, %r0
71
        mull2   %r0, %r1
72
        subl3   %r1, %r2, %r0
73
        ret
74
 
75
        /* MSB of divisor set, subtract the divisor at most once.  */
76
0:
77
        movl    4(%ap), %r2
78
        clrl    %r0
79
        cmpl    %r2, %r1
80
        sbwc    $0, %r0
81
        bicl2   %r0, %r1
82
        subl3   %r1, %r2, %r0
83
        ret
84
 
85
        /* MSB of dividend set, do an extended division.  */
86
1:
87
        clrl    %r3
88
        ediv    %r1, %r2, %r3, %r0
89
        ret
90
        .size   __umodsi3, . - __umodsi3
91
        .previous
92
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.