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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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jeremybenn |
; Options for the Tensilica Xtensa port of the compiler.
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; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; .
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mconst16
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Target Report Mask(CONST16)
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Use CONST16 instruction to load constants
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mfused-madd
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Target Report Mask(FUSED_MADD)
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Enable fused multiply/add and multiply/subtract FP instructions
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mlongcalls
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Target
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Use indirect CALLXn instructions for large programs
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mtarget-align
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Target
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Automatically align branch targets to reduce branch penalties
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mtext-section-literals
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Target
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Intersperse literal pools with code in the text section
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mserialize-volatile
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Target Report Mask(SERIALIZE_VOLATILE)
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-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions
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