Subversion Repositories openrisc_2011-10-31

/* RTL-based forward propagation pass for GNU compiler.

   Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010

   Free Software Foundation, Inc.

   Contributed by Paolo Bonzini and Steven Bosscher.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under

the terms of the GNU General Public License as published by the Free

Software Foundation; either version 3, or (at your option) any later

version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY

WARRANTY; without even the implied warranty of MERCHANTABILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "toplev.h"

#include "timevar.h"

#include "rtl.h"

#include "tm_p.h"

#include "emit-rtl.h"

#include "insn-config.h"

#include "recog.h"

#include "flags.h"

#include "obstack.h"

#include "basic-block.h"

#include "output.h"

#include "df.h"

#include "target.h"

#include "cfgloop.h"

#include "tree-pass.h"

#include "domwalk.h"

/* This pass does simple forward propagation and simplification when an

   operand of an insn can only come from a single def.  This pass uses

   df.c, so it is global.  However, we only do limited analysis of

   available expressions.

   1) The pass tries to propagate the source of the def into the use,

   and checks if the result is independent of the substituted value.

   For example, the high word of a (zero_extend:DI (reg:SI M)) is always

   zero, independent of the source register.

   In particular, we propagate constants into the use site.  Sometimes

   RTL expansion did not put the constant in the same insn on purpose,

   to satisfy a predicate, and the result will fail to be recognized;

   but this happens rarely and in this case we can still create a

   REG_EQUAL note.  For multi-word operations, this

      (set (subreg:SI (reg:DI 120) 0) (const_int 0))

      (set (subreg:SI (reg:DI 120) 4) (const_int -1))

      (set (subreg:SI (reg:DI 122) 0)

         (ior:SI (subreg:SI (reg:DI 119) 0) (subreg:SI (reg:DI 120) 0)))

      (set (subreg:SI (reg:DI 122) 4)

         (ior:SI (subreg:SI (reg:DI 119) 4) (subreg:SI (reg:DI 120) 4)))

   can be simplified to the much simpler

      (set (subreg:SI (reg:DI 122) 0) (subreg:SI (reg:DI 119)))

      (set (subreg:SI (reg:DI 122) 4) (const_int -1))

   This particular propagation is also effective at putting together

   complex addressing modes.  We are more aggressive inside MEMs, in

   that all definitions are propagated if the use is in a MEM; if the

   result is a valid memory address we check address_cost to decide

   whether the substitution is worthwhile.

   2) The pass propagates register copies.  This is not as effective as

   the copy propagation done by CSE's canon_reg, which works by walking

   the instruction chain, it can help the other transformations.

   We should consider removing this optimization, and instead reorder the

   RTL passes, because GCSE does this transformation too.  With some luck,

   the CSE pass at the end of rest_of_handle_gcse could also go away.

   3) The pass looks for paradoxical subregs that are actually unnecessary.

   Things like this:

     (set (reg:QI 120) (subreg:QI (reg:SI 118) 0))

     (set (reg:QI 121) (subreg:QI (reg:SI 119) 0))

     (set (reg:SI 122) (plus:SI (subreg:SI (reg:QI 120) 0)

                                (subreg:SI (reg:QI 121) 0)))

   are very common on machines that can only do word-sized operations.

   For each use of a paradoxical subreg (subreg:WIDER (reg:NARROW N) 0),

   if it has a single def and it is (subreg:NARROW (reg:WIDE M) 0),

   we can replace the paradoxical subreg with simply (reg:WIDE M).  The

   above will simplify this to

     (set (reg:QI 120) (subreg:QI (reg:SI 118) 0))

     (set (reg:QI 121) (subreg:QI (reg:SI 119) 0))

     (set (reg:SI 122) (plus:SI (reg:SI 118) (reg:SI 119)))

   where the first two insns are now dead.

   We used to use reaching definitions to find which uses have a

   single reaching definition (sounds obvious...), but this is too

   complex a problem in nasty testcases like PR33928.  Now we use the

   multiple definitions problem in df-problems.c.  The similarity

   between that problem and SSA form creation is taken further, in

   that fwprop does a dominator walk to create its chains; however,

   instead of creating a PHI function where multiple definitions meet

   I just punt and record only singleton use-def chains, which is

   all that is needed by fwprop.  */

static int num_changes;

DEF_VEC_P(df_ref);

DEF_VEC_ALLOC_P(df_ref,heap);

static VEC(df_ref,heap) *use_def_ref;

static VEC(df_ref,heap) *reg_defs;

static VEC(df_ref,heap) *reg_defs_stack;

/* The MD bitmaps are trimmed to include only live registers to cut

   memory usage on testcases like insn-recog.c.  Track live registers

   in the basic block and do not perform forward propagation if the

   destination is a dead pseudo occurring in a note.  */

static bitmap local_md;

static bitmap local_lr;

/* Return the only def in USE's use-def chain, or NULL if there is

   more than one def in the chain.  */

static inline df_ref

get_def_for_use (df_ref use)

{

  return VEC_index (df_ref, use_def_ref, DF_REF_ID (use));

}

/* Update the reg_defs vector with non-partial definitions in DEF_REC.

   TOP_FLAG says which artificials uses should be used, when DEF_REC

   is an artificial def vector.  LOCAL_MD is modified as after a

   df_md_simulate_* function; we do more or less the same processing

   done there, so we do not use those functions.  */

#define DF_MD_GEN_FLAGS \

        (DF_REF_PARTIAL | DF_REF_CONDITIONAL | DF_REF_MAY_CLOBBER)

static void

process_defs (df_ref *def_rec, int top_flag)

{

  df_ref def;

  while ((def = *def_rec++) != NULL)

    {

      df_ref curr_def = VEC_index (df_ref, reg_defs, DF_REF_REGNO (def));

      unsigned int dregno;

      if ((DF_REF_FLAGS (def) & DF_REF_AT_TOP) != top_flag)

        continue;

      dregno = DF_REF_REGNO (def);

      if (curr_def)

        VEC_safe_push (df_ref, heap, reg_defs_stack, curr_def);

      else

        {

          /* Do not store anything if "transitioning" from NULL to NULL.  But

             otherwise, push a special entry on the stack to tell the

             leave_block callback that the entry in reg_defs was NULL.  */

          if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS)

            ;

          else

            VEC_safe_push (df_ref, heap, reg_defs_stack, def);

        }

      if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS)

        {

          bitmap_set_bit (local_md, dregno);

          VEC_replace (df_ref, reg_defs, dregno, NULL);

        }

      else

        {

          bitmap_clear_bit (local_md, dregno);

          VEC_replace (df_ref, reg_defs, dregno, def);

        }

    }

}

/* Fill the use_def_ref vector with values for the uses in USE_REC,

   taking reaching definitions info from LOCAL_MD and REG_DEFS.

   TOP_FLAG says which artificials uses should be used, when USE_REC

   is an artificial use vector.  */

static void

process_uses (df_ref *use_rec, int top_flag)

{

  df_ref use;

  while ((use = *use_rec++) != NULL)

    if ((DF_REF_FLAGS (use) & DF_REF_AT_TOP) == top_flag)

      {

        unsigned int uregno = DF_REF_REGNO (use);

        if (VEC_index (df_ref, reg_defs, uregno)

            && !bitmap_bit_p (local_md, uregno)

            && bitmap_bit_p (local_lr, uregno))

          VEC_replace (df_ref, use_def_ref, DF_REF_ID (use),

                       VEC_index (df_ref, reg_defs, uregno));

      }

}

static void

single_def_use_enter_block (struct dom_walk_data *walk_data ATTRIBUTE_UNUSED,

                            basic_block bb)

{

  int bb_index = bb->index;

  struct df_md_bb_info *md_bb_info = df_md_get_bb_info (bb_index);

  struct df_lr_bb_info *lr_bb_info = df_lr_get_bb_info (bb_index);

  rtx insn;

  bitmap_copy (local_md, md_bb_info->in);

  bitmap_copy (local_lr, lr_bb_info->in);

  /* Push a marker for the leave_block callback.  */

  VEC_safe_push (df_ref, heap, reg_defs_stack, NULL);

  process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP);

  process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP);

  df_simulate_initialize_forwards (bb, local_lr);

  FOR_BB_INSNS (bb, insn)

    if (INSN_P (insn))

      {

        unsigned int uid = INSN_UID (insn);

        process_uses (DF_INSN_UID_USES (uid), 0);

        process_uses (DF_INSN_UID_EQ_USES (uid), 0);

        process_defs (DF_INSN_UID_DEFS (uid), 0);

        df_simulate_one_insn_forwards (bb, insn, local_lr);

      }

  process_uses (df_get_artificial_uses (bb_index), 0);

  process_defs (df_get_artificial_defs (bb_index), 0);

}

/* Pop the definitions created in this basic block when leaving its

   dominated parts.  */

static void

single_def_use_leave_block (struct dom_walk_data *walk_data ATTRIBUTE_UNUSED,

                            basic_block bb ATTRIBUTE_UNUSED)

{

  df_ref saved_def;

  while ((saved_def = VEC_pop (df_ref, reg_defs_stack)) != NULL)

    {

      unsigned int dregno = DF_REF_REGNO (saved_def);

      /* See also process_defs.  */

      if (saved_def == VEC_index (df_ref, reg_defs, dregno))

        VEC_replace (df_ref, reg_defs, dregno, NULL);

      else

        VEC_replace (df_ref, reg_defs, dregno, saved_def);

    }

}

/* Build a vector holding the reaching definitions of uses reached by a

   single dominating definition.  */

static void

build_single_def_use_links (void)

{

  struct dom_walk_data walk_data;

  /* We use the multiple definitions problem to compute our restricted

     use-def chains.  */

  df_set_flags (DF_EQ_NOTES);

  df_md_add_problem ();

  df_note_add_problem ();

  df_analyze ();

  df_maybe_reorganize_use_refs (DF_REF_ORDER_BY_INSN_WITH_NOTES);

  use_def_ref = VEC_alloc (df_ref, heap, DF_USES_TABLE_SIZE ());

  VEC_safe_grow_cleared (df_ref, heap, use_def_ref, DF_USES_TABLE_SIZE ());

  reg_defs = VEC_alloc (df_ref, heap, max_reg_num ());

  VEC_safe_grow_cleared (df_ref, heap, reg_defs, max_reg_num ());

  reg_defs_stack = VEC_alloc (df_ref, heap, n_basic_blocks * 10);

  local_md = BITMAP_ALLOC (NULL);

  local_lr = BITMAP_ALLOC (NULL);

  /* Walk the dominator tree looking for single reaching definitions

     dominating the uses.  This is similar to how SSA form is built.  */

  walk_data.dom_direction = CDI_DOMINATORS;

  walk_data.initialize_block_local_data = NULL;

  walk_data.before_dom_children = single_def_use_enter_block;

  walk_data.after_dom_children = single_def_use_leave_block;

  init_walk_dominator_tree (&walk_data);

  walk_dominator_tree (&walk_data, ENTRY_BLOCK_PTR);

  fini_walk_dominator_tree (&walk_data);

  BITMAP_FREE (local_lr);

  BITMAP_FREE (local_md);

  VEC_free (df_ref, heap, reg_defs);

  VEC_free (df_ref, heap, reg_defs_stack);

}

/* Do not try to replace constant addresses or addresses of local and

   argument slots.  These MEM expressions are made only once and inserted

   in many instructions, as well as being used to control symbol table

   output.  It is not safe to clobber them.

   There are some uncommon cases where the address is already in a register

   for some reason, but we cannot take advantage of that because we have

   no easy way to unshare the MEM.  In addition, looking up all stack

   addresses is costly.  */

static bool

can_simplify_addr (rtx addr)

{

  rtx reg;

  if (CONSTANT_ADDRESS_P (addr))

    return false;

  if (GET_CODE (addr) == PLUS)

    reg = XEXP (addr, 0);

  else

    reg = addr;

  return (!REG_P (reg)

          || (REGNO (reg) != FRAME_POINTER_REGNUM

              && REGNO (reg) != HARD_FRAME_POINTER_REGNUM

              && REGNO (reg) != ARG_POINTER_REGNUM));

}

/* Returns a canonical version of X for the address, from the point of view,

   that all multiplications are represented as MULT instead of the multiply

   by a power of 2 being represented as ASHIFT.

   Every ASHIFT we find has been made by simplify_gen_binary and was not

   there before, so it is not shared.  So we can do this in place.  */

static void

canonicalize_address (rtx x)

{

  for (;;)

    switch (GET_CODE (x))

      {

      case ASHIFT:

        if (CONST_INT_P (XEXP (x, 1))

            && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (GET_MODE (x))

            && INTVAL (XEXP (x, 1)) >= 0)

          {

            HOST_WIDE_INT shift = INTVAL (XEXP (x, 1));

            PUT_CODE (x, MULT);

            XEXP (x, 1) = gen_int_mode ((HOST_WIDE_INT) 1 << shift,

                                        GET_MODE (x));

          }

        x = XEXP (x, 0);

        break;

      case PLUS:

        if (GET_CODE (XEXP (x, 0)) == PLUS

            || GET_CODE (XEXP (x, 0)) == ASHIFT

            || GET_CODE (XEXP (x, 0)) == CONST)

          canonicalize_address (XEXP (x, 0));

        x = XEXP (x, 1);

        break;

      case CONST:

        x = XEXP (x, 0);

        break;

      default:

        return;

      }

}

/* OLD is a memory address.  Return whether it is good to use NEW instead,

   for a memory access in the given MODE.  */

static bool

should_replace_address (rtx old_rtx, rtx new_rtx, enum machine_mode mode,

                        addr_space_t as, bool speed)

{

  int gain;

  if (rtx_equal_p (old_rtx, new_rtx)

      || !memory_address_addr_space_p (mode, new_rtx, as))

    return false;

  /* Copy propagation is always ok.  */

  if (REG_P (old_rtx) && REG_P (new_rtx))

    return true;

  /* Prefer the new address if it is less expensive.  */

  gain = (address_cost (old_rtx, mode, as, speed)

          - address_cost (new_rtx, mode, as, speed));

  /* If the addresses have equivalent cost, prefer the new address

     if it has the highest `rtx_cost'.  That has the potential of

     eliminating the most insns without additional costs, and it

     is the same that cse.c used to do.  */

  if (gain == 0)

    gain = rtx_cost (new_rtx, SET, speed) - rtx_cost (old_rtx, SET, speed);

  return (gain > 0);

}

/* Flags for the last parameter of propagate_rtx_1.  */

enum {

  /* If PR_CAN_APPEAR is true, propagate_rtx_1 always returns true;

     if it is false, propagate_rtx_1 returns false if, for at least

     one occurrence OLD, it failed to collapse the result to a constant.

     For example, (mult:M (reg:M A) (minus:M (reg:M B) (reg:M A))) may

     collapse to zero if replacing (reg:M B) with (reg:M A).

     PR_CAN_APPEAR is disregarded inside MEMs: in that case,

     propagate_rtx_1 just tries to make cheaper and valid memory

     addresses.  */

  PR_CAN_APPEAR = 1,

  /* If PR_HANDLE_MEM is not set, propagate_rtx_1 won't attempt any replacement

     outside memory addresses.  This is needed because propagate_rtx_1 does

     not do any analysis on memory; thus it is very conservative and in general

     it will fail if non-read-only MEMs are found in the source expression.

     PR_HANDLE_MEM is set when the source of the propagation was not

     another MEM.  Then, it is safe not to treat non-read-only MEMs as

     ``opaque'' objects.  */

  PR_HANDLE_MEM = 2,

  /* Set when costs should be optimized for speed.  */

  PR_OPTIMIZE_FOR_SPEED = 4

};

/* Replace all occurrences of OLD in *PX with NEW and try to simplify the

   resulting expression.  Replace *PX with a new RTL expression if an

   occurrence of OLD was found.

   This is only a wrapper around simplify-rtx.c: do not add any pattern

   matching code here.  (The sole exception is the handling of LO_SUM, but

   that is because there is no simplify_gen_* function for LO_SUM).  */

static bool

propagate_rtx_1 (rtx *px, rtx old_rtx, rtx new_rtx, int flags)

{

  rtx x = *px, tem = NULL_RTX, op0, op1, op2;

  enum rtx_code code = GET_CODE (x);

  enum machine_mode mode = GET_MODE (x);

  enum machine_mode op_mode;

  bool can_appear = (flags & PR_CAN_APPEAR) != 0;

  bool valid_ops = true;

  if (!(flags & PR_HANDLE_MEM) && MEM_P (x) && !MEM_READONLY_P (x))

    {

      /* If unsafe, change MEMs to CLOBBERs or SCRATCHes (to preserve whether

         they have side effects or not).  */

      *px = (side_effects_p (x)

             ? gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)

             : gen_rtx_SCRATCH (GET_MODE (x)));

      return false;

    }

  /* If X is OLD_RTX, return NEW_RTX.  But not if replacing only within an

     address, and we are *not* inside one.  */

  if (x == old_rtx)

    {

      *px = new_rtx;

      return can_appear;

    }

  /* If this is an expression, try recursive substitution.  */

  switch (GET_RTX_CLASS (code))

    {

    case RTX_UNARY:

      op0 = XEXP (x, 0);

      op_mode = GET_MODE (op0);

      valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);

      if (op0 == XEXP (x, 0))

        return true;

      tem = simplify_gen_unary (code, mode, op0, op_mode);

      break;

    case RTX_BIN_ARITH:

    case RTX_COMM_ARITH:

      op0 = XEXP (x, 0);

      op1 = XEXP (x, 1);

      valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);

      valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);

      if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))

        return true;

      tem = simplify_gen_binary (code, mode, op0, op1);

      break;

    case RTX_COMPARE:

    case RTX_COMM_COMPARE:

      op0 = XEXP (x, 0);

      op1 = XEXP (x, 1);

      op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);

      valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);

      valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);

      if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))

        return true;

      tem = simplify_gen_relational (code, mode, op_mode, op0, op1);

      break;

    case RTX_TERNARY:

    case RTX_BITFIELD_OPS:

      op0 = XEXP (x, 0);

      op1 = XEXP (x, 1);

      op2 = XEXP (x, 2);

      op_mode = GET_MODE (op0);

      valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);

      valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);

      valid_ops &= propagate_rtx_1 (&op2, old_rtx, new_rtx, flags);

      if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2))

        return true;

      if (op_mode == VOIDmode)

        op_mode = GET_MODE (op0);

      tem = simplify_gen_ternary (code, mode, op_mode, op0, op1, op2);

      break;

    case RTX_EXTRA:

      /* The only case we try to handle is a SUBREG.  */

      if (code == SUBREG)

        {

          op0 = XEXP (x, 0);

          valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);

          if (op0 == XEXP (x, 0))

            return true;

          tem = simplify_gen_subreg (mode, op0, GET_MODE (SUBREG_REG (x)),

                                     SUBREG_BYTE (x));

        }

      break;

    case RTX_OBJ:

      if (code == MEM && x != new_rtx)

        {

          rtx new_op0;

          op0 = XEXP (x, 0);

          /* There are some addresses that we cannot work on.  */

          if (!can_simplify_addr (op0))

            return true;

          op0 = new_op0 = targetm.delegitimize_address (op0);

          valid_ops &= propagate_rtx_1 (&new_op0, old_rtx, new_rtx,

                                        flags | PR_CAN_APPEAR);

          /* Dismiss transformation that we do not want to carry on.  */

          if (!valid_ops

              || new_op0 == op0

              || !(GET_MODE (new_op0) == GET_MODE (op0)

                   || GET_MODE (new_op0) == VOIDmode))

            return true;

          canonicalize_address (new_op0);

          /* Copy propagations are always ok.  Otherwise check the costs.  */

          if (!(REG_P (old_rtx) && REG_P (new_rtx))

              && !should_replace_address (op0, new_op0, GET_MODE (x),

                                          MEM_ADDR_SPACE (x),

                                          flags & PR_OPTIMIZE_FOR_SPEED))

            return true;

          tem = replace_equiv_address_nv (x, new_op0);

        }

      else if (code == LO_SUM)

        {

          op0 = XEXP (x, 0);

          op1 = XEXP (x, 1);

          /* The only simplification we do attempts to remove references to op0

             or make it constant -- in both cases, op0's invalidity will not

             make the result invalid.  */

          propagate_rtx_1 (&op0, old_rtx, new_rtx, flags | PR_CAN_APPEAR);

          valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);

          if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))

            return true;

          /* (lo_sum (high x) x) -> x  */

          if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1))

            tem = op1;

          else

            tem = gen_rtx_LO_SUM (mode, op0, op1);

          /* OP1 is likely not a legitimate address, otherwise there would have

             been no LO_SUM.  We want it to disappear if it is invalid, return

             false in that case.  */

          return memory_address_p (mode, tem);

        }

      else if (code == REG)

        {

          if (rtx_equal_p (x, old_rtx))

            {

              *px = new_rtx;

              return can_appear;

            }

        }

      break;

    default:

      break;

    }

  /* No change, no trouble.  */

  if (tem == NULL_RTX)

    return true;

  *px = tem;

  /* The replacement we made so far is valid, if all of the recursive

     replacements were valid, or we could simplify everything to

     a constant.  */

  return valid_ops || can_appear || CONSTANT_P (tem);

}

/* for_each_rtx traversal function that returns 1 if BODY points to

   a non-constant mem.  */

static int

varying_mem_p (rtx *body, void *data ATTRIBUTE_UNUSED)

{

  rtx x = *body;

  return MEM_P (x) && !MEM_READONLY_P (x);

}

/* Replace all occurrences of OLD in X with NEW and try to simplify the

   resulting expression (in mode MODE).  Return a new expression if it is

   a constant, otherwise X.

   Simplifications where occurrences of NEW collapse to a constant are always

   accepted.  All simplifications are accepted if NEW is a pseudo too.

   Otherwise, we accept simplifications that have a lower or equal cost.  */

static rtx

propagate_rtx (rtx x, enum machine_mode mode, rtx old_rtx, rtx new_rtx,

               bool speed)

{

  rtx tem;

  bool collapsed;

  int flags;

  if (REG_P (new_rtx) && REGNO (new_rtx) < FIRST_PSEUDO_REGISTER)

    return NULL_RTX;

  flags = 0;

  if (REG_P (new_rtx) || CONSTANT_P (new_rtx))

    flags |= PR_CAN_APPEAR;

  if (!for_each_rtx (&new_rtx, varying_mem_p, NULL))

    flags |= PR_HANDLE_MEM;

  if (speed)

    flags |= PR_OPTIMIZE_FOR_SPEED;

  tem = x;

  collapsed = propagate_rtx_1 (&tem, old_rtx, copy_rtx (new_rtx), flags);

  if (tem == x || !collapsed)

    return NULL_RTX;

  /* gen_lowpart_common will not be able to process VOIDmode entities other

     than CONST_INTs.  */

  if (GET_MODE (tem) == VOIDmode && !CONST_INT_P (tem))

    return NULL_RTX;

  if (GET_MODE (tem) == VOIDmode)

    tem = rtl_hooks.gen_lowpart_no_emit (mode, tem);

  else

    gcc_assert (GET_MODE (tem) == mode);

  return tem;

}

/* Return true if the register from reference REF is killed

   between FROM to (but not including) TO.  */

static bool

local_ref_killed_between_p (df_ref ref, rtx from, rtx to)

{

  rtx insn;

  for (insn = from; insn != to; insn = NEXT_INSN (insn))

    {

      df_ref *def_rec;

      if (!INSN_P (insn))

        continue;

      for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)