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280 |
jeremybenn |
/* Search an insn for pseudo regs that must be in hard regs and are not.
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Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
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1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
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Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* This file contains subroutines used only from the file reload1.c.
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It knows how to scan one insn for operands and values
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that need to be copied into registers to make valid code.
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It also finds other operands and values which are valid
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but for which equivalent values in registers exist and
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ought to be used instead.
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Before processing the first insn of the function, call `init_reload'.
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init_reload actually has to be called earlier anyway.
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To scan an insn, call `find_reloads'. This does two things:
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1. sets up tables describing which values must be reloaded
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for this insn, and what kind of hard regs they must be reloaded into;
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2. optionally record the locations where those values appear in
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the data, so they can be replaced properly later.
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This is done only if the second arg to `find_reloads' is nonzero.
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The third arg to `find_reloads' specifies the number of levels
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of indirect addressing supported by the machine. If it is zero,
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indirect addressing is not valid. If it is one, (MEM (REG n))
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is valid even if (REG n) did not get a hard register; if it is two,
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(MEM (MEM (REG n))) is also valid even if (REG n) did not get a
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hard register, and similarly for higher values.
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Then you must choose the hard regs to reload those pseudo regs into,
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and generate appropriate load insns before this insn and perhaps
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also store insns after this insn. Set up the array `reload_reg_rtx'
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to contain the REG rtx's for the registers you used. In some
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cases `find_reloads' will return a nonzero value in `reload_reg_rtx'
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for certain reloads. Then that tells you which register to use,
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so you do not need to allocate one. But you still do need to add extra
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instructions to copy the value into and out of that register.
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Finally you must call `subst_reloads' to substitute the reload reg rtx's
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into the locations already recorded.
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NOTE SIDE EFFECTS:
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find_reloads can alter the operands of the instruction it is called on.
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1. Two operands of any sort may be interchanged, if they are in a
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commutative instruction.
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This happens only if find_reloads thinks the instruction will compile
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better that way.
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2. Pseudo-registers that are equivalent to constants are replaced
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with those constants if they are not in hard registers.
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1 happens every time find_reloads is called.
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2 happens only when REPLACE is 1, which is only when
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actually doing the reloads, not when just counting them.
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Using a reload register for several reloads in one insn:
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When an insn has reloads, it is considered as having three parts:
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the input reloads, the insn itself after reloading, and the output reloads.
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Reloads of values used in memory addresses are often needed for only one part.
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When this is so, reload_when_needed records which part needs the reload.
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Two reloads for different parts of the insn can share the same reload
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register.
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When a reload is used for addresses in multiple parts, or when it is
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an ordinary operand, it is classified as RELOAD_OTHER, and cannot share
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a register with any other reload. */
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#define REG_OK_STRICT
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/* We do not enable this with ENABLE_CHECKING, since it is awfully slow. */
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#undef DEBUG_RELOAD
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "tm.h"
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#include "rtl.h"
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#include "tm_p.h"
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#include "insn-config.h"
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#include "expr.h"
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#include "optabs.h"
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#include "recog.h"
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#include "reload.h"
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#include "regs.h"
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#include "addresses.h"
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#include "hard-reg-set.h"
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#include "flags.h"
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#include "real.h"
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#include "output.h"
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#include "function.h"
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#include "toplev.h"
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#include "params.h"
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#include "target.h"
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#include "df.h"
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#include "ira.h"
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/* True if X is a constant that can be forced into the constant pool. */
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#define CONST_POOL_OK_P(X) \
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(CONSTANT_P (X) \
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&& GET_CODE (X) != HIGH \
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&& !targetm.cannot_force_const_mem (X))
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/* True if C is a non-empty register class that has too few registers
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to be safely used as a reload target class. */
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#define SMALL_REGISTER_CLASS_P(C) \
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(reg_class_size [(C)] == 1 \
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|| (reg_class_size [(C)] >= 1 && CLASS_LIKELY_SPILLED_P (C)))
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/* All reloads of the current insn are recorded here. See reload.h for
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comments. */
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int n_reloads;
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struct reload rld[MAX_RELOADS];
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/* All the "earlyclobber" operands of the current insn
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are recorded here. */
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int n_earlyclobbers;
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rtx reload_earlyclobbers[MAX_RECOG_OPERANDS];
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int reload_n_operands;
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/* Replacing reloads.
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If `replace_reloads' is nonzero, then as each reload is recorded
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an entry is made for it in the table `replacements'.
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Then later `subst_reloads' can look through that table and
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perform all the replacements needed. */
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/* Nonzero means record the places to replace. */
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static int replace_reloads;
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/* Each replacement is recorded with a structure like this. */
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struct replacement
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{
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rtx *where; /* Location to store in */
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rtx *subreg_loc; /* Location of SUBREG if WHERE is inside
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a SUBREG; 0 otherwise. */
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int what; /* which reload this is for */
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enum machine_mode mode; /* mode it must have */
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};
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static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
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/* Number of replacements currently recorded. */
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static int n_replacements;
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/* Used to track what is modified by an operand. */
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struct decomposition
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{
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int reg_flag; /* Nonzero if referencing a register. */
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int safe; /* Nonzero if this can't conflict with anything. */
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rtx base; /* Base address for MEM. */
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HOST_WIDE_INT start; /* Starting offset or register number. */
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HOST_WIDE_INT end; /* Ending offset or register number. */
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};
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#ifdef SECONDARY_MEMORY_NEEDED
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/* Save MEMs needed to copy from one class of registers to another. One MEM
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is used per mode, but normally only one or two modes are ever used.
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We keep two versions, before and after register elimination. The one
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after register elimination is record separately for each operand. This
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is done in case the address is not valid to be sure that we separately
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reload each. */
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static rtx secondary_memlocs[NUM_MACHINE_MODES];
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static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS];
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static int secondary_memlocs_elim_used = 0;
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#endif
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/* The instruction we are doing reloads for;
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so we can test whether a register dies in it. */
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static rtx this_insn;
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/* Nonzero if this instruction is a user-specified asm with operands. */
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static int this_insn_is_asm;
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/* If hard_regs_live_known is nonzero,
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we can tell which hard regs are currently live,
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at least enough to succeed in choosing dummy reloads. */
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static int hard_regs_live_known;
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/* Indexed by hard reg number,
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element is nonnegative if hard reg has been spilled.
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This vector is passed to `find_reloads' as an argument
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and is not changed here. */
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static short *static_reload_reg_p;
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/* Set to 1 in subst_reg_equivs if it changes anything. */
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static int subst_reg_equivs_changed;
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/* On return from push_reload, holds the reload-number for the OUT
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operand, which can be different for that from the input operand. */
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static int output_reloadnum;
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/* Compare two RTX's. */
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#define MATCHES(x, y) \
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(x == y || (x != 0 && (REG_P (x) \
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? REG_P (y) && REGNO (x) == REGNO (y) \
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: rtx_equal_p (x, y) && ! side_effects_p (x))))
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/* Indicates if two reloads purposes are for similar enough things that we
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can merge their reloads. */
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#define MERGABLE_RELOADS(when1, when2, op1, op2) \
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((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \
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|| ((when1) == (when2) && (op1) == (op2)) \
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|| ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \
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|| ((when1) == RELOAD_FOR_OPERAND_ADDRESS \
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&& (when2) == RELOAD_FOR_OPERAND_ADDRESS) \
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|| ((when1) == RELOAD_FOR_OTHER_ADDRESS \
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&& (when2) == RELOAD_FOR_OTHER_ADDRESS))
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/* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */
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#define MERGE_TO_OTHER(when1, when2, op1, op2) \
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((when1) != (when2) \
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|| ! ((op1) == (op2) \
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|| (when1) == RELOAD_FOR_INPUT \
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|| (when1) == RELOAD_FOR_OPERAND_ADDRESS \
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|| (when1) == RELOAD_FOR_OTHER_ADDRESS))
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/* If we are going to reload an address, compute the reload type to
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use. */
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#define ADDR_TYPE(type) \
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((type) == RELOAD_FOR_INPUT_ADDRESS \
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? RELOAD_FOR_INPADDR_ADDRESS \
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: ((type) == RELOAD_FOR_OUTPUT_ADDRESS \
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? RELOAD_FOR_OUTADDR_ADDRESS \
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: (type)))
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static int push_secondary_reload (int, rtx, int, int, enum reg_class,
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enum machine_mode, enum reload_type,
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enum insn_code *, secondary_reload_info *);
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static enum reg_class find_valid_class (enum machine_mode, enum machine_mode,
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int, unsigned int);
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static int reload_inner_reg_of_subreg (rtx, enum machine_mode, int);
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static void push_replacement (rtx *, int, enum machine_mode);
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static void dup_replacements (rtx *, rtx *);
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static void combine_reloads (void);
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static int find_reusable_reload (rtx *, rtx, enum reg_class,
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enum reload_type, int, int);
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static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, enum machine_mode,
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enum machine_mode, enum reg_class, int, int);
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static int hard_reg_set_here_p (unsigned int, unsigned int, rtx);
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static struct decomposition decompose (rtx);
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static int immune_p (rtx, rtx, struct decomposition);
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static bool alternative_allows_const_pool_ref (rtx, const char *, int);
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static rtx find_reloads_toplev (rtx, int, enum reload_type, int, int, rtx,
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int *);
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static rtx make_memloc (rtx, int);
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static int maybe_memory_address_addr_space_p (enum machine_mode, rtx,
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addr_space_t, rtx *);
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static int find_reloads_address (enum machine_mode, rtx *, rtx, rtx *,
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int, enum reload_type, int, rtx);
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static rtx subst_reg_equivs (rtx, rtx);
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static rtx subst_indexed_address (rtx);
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static void update_auto_inc_notes (rtx, int, int);
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static int find_reloads_address_1 (enum machine_mode, rtx, int,
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enum rtx_code, enum rtx_code, rtx *,
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int, enum reload_type,int, rtx);
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| 281 |
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static void find_reloads_address_part (rtx, rtx *, enum reg_class,
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enum machine_mode, int,
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enum reload_type, int);
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| 284 |
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static rtx find_reloads_subreg_address (rtx, int, int, enum reload_type,
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int, rtx);
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| 286 |
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static void copy_replacements_1 (rtx *, rtx *, int);
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static int find_inc_amount (rtx, rtx);
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| 288 |
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static int refers_to_mem_for_reload_p (rtx);
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static int refers_to_regno_for_reload_p (unsigned int, unsigned int,
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| 290 |
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rtx, rtx *);
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| 292 |
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/* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the
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list yet. */
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| 294 |
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static void
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push_reg_equiv_alt_mem (int regno, rtx mem)
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| 297 |
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{
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| 298 |
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rtx it;
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| 299 |
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| 300 |
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for (it = reg_equiv_alt_mem_list [regno]; it; it = XEXP (it, 1))
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if (rtx_equal_p (XEXP (it, 0), mem))
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return;
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reg_equiv_alt_mem_list [regno]
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= alloc_EXPR_LIST (REG_EQUIV, mem,
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reg_equiv_alt_mem_list [regno]);
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| 307 |
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}
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| 308 |
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| 309 |
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/* Determine if any secondary reloads are needed for loading (if IN_P is
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| 310 |
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nonzero) or storing (if IN_P is zero) X to or from a reload register of
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| 311 |
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register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads
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| 312 |
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are needed, push them.
|
| 313 |
|
|
|
| 314 |
|
|
Return the reload number of the secondary reload we made, or -1 if
|
| 315 |
|
|
we didn't need one. *PICODE is set to the insn_code to use if we do
|
| 316 |
|
|
need a secondary reload. */
|
| 317 |
|
|
|
| 318 |
|
|
static int
|
| 319 |
|
|
push_secondary_reload (int in_p, rtx x, int opnum, int optional,
|
| 320 |
|
|
enum reg_class reload_class,
|
| 321 |
|
|
enum machine_mode reload_mode, enum reload_type type,
|
| 322 |
|
|
enum insn_code *picode, secondary_reload_info *prev_sri)
|
| 323 |
|
|
{
|
| 324 |
|
|
enum reg_class rclass = NO_REGS;
|
| 325 |
|
|
enum reg_class scratch_class;
|
| 326 |
|
|
enum machine_mode mode = reload_mode;
|
| 327 |
|
|
enum insn_code icode = CODE_FOR_nothing;
|
| 328 |
|
|
enum insn_code t_icode = CODE_FOR_nothing;
|
| 329 |
|
|
enum reload_type secondary_type;
|
| 330 |
|
|
int s_reload, t_reload = -1;
|
| 331 |
|
|
const char *scratch_constraint;
|
| 332 |
|
|
char letter;
|
| 333 |
|
|
secondary_reload_info sri;
|
| 334 |
|
|
|
| 335 |
|
|
if (type == RELOAD_FOR_INPUT_ADDRESS
|
| 336 |
|
|
|| type == RELOAD_FOR_OUTPUT_ADDRESS
|
| 337 |
|
|
|| type == RELOAD_FOR_INPADDR_ADDRESS
|
| 338 |
|
|
|| type == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 339 |
|
|
secondary_type = type;
|
| 340 |
|
|
else
|
| 341 |
|
|
secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS;
|
| 342 |
|
|
|
| 343 |
|
|
*picode = CODE_FOR_nothing;
|
| 344 |
|
|
|
| 345 |
|
|
/* If X is a paradoxical SUBREG, use the inner value to determine both the
|
| 346 |
|
|
mode and object being reloaded. */
|
| 347 |
|
|
if (GET_CODE (x) == SUBREG
|
| 348 |
|
|
&& (GET_MODE_SIZE (GET_MODE (x))
|
| 349 |
|
|
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
|
| 350 |
|
|
{
|
| 351 |
|
|
x = SUBREG_REG (x);
|
| 352 |
|
|
reload_mode = GET_MODE (x);
|
| 353 |
|
|
}
|
| 354 |
|
|
|
| 355 |
|
|
/* If X is a pseudo-register that has an equivalent MEM (actually, if it
|
| 356 |
|
|
is still a pseudo-register by now, it *must* have an equivalent MEM
|
| 357 |
|
|
but we don't want to assume that), use that equivalent when seeing if
|
| 358 |
|
|
a secondary reload is needed since whether or not a reload is needed
|
| 359 |
|
|
might be sensitive to the form of the MEM. */
|
| 360 |
|
|
|
| 361 |
|
|
if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER
|
| 362 |
|
|
&& reg_equiv_mem[REGNO (x)] != 0)
|
| 363 |
|
|
x = reg_equiv_mem[REGNO (x)];
|
| 364 |
|
|
|
| 365 |
|
|
sri.icode = CODE_FOR_nothing;
|
| 366 |
|
|
sri.prev_sri = prev_sri;
|
| 367 |
|
|
rclass = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri);
|
| 368 |
|
|
icode = (enum insn_code) sri.icode;
|
| 369 |
|
|
|
| 370 |
|
|
/* If we don't need any secondary registers, done. */
|
| 371 |
|
|
if (rclass == NO_REGS && icode == CODE_FOR_nothing)
|
| 372 |
|
|
return -1;
|
| 373 |
|
|
|
| 374 |
|
|
if (rclass != NO_REGS)
|
| 375 |
|
|
t_reload = push_secondary_reload (in_p, x, opnum, optional, rclass,
|
| 376 |
|
|
reload_mode, type, &t_icode, &sri);
|
| 377 |
|
|
|
| 378 |
|
|
/* If we will be using an insn, the secondary reload is for a
|
| 379 |
|
|
scratch register. */
|
| 380 |
|
|
|
| 381 |
|
|
if (icode != CODE_FOR_nothing)
|
| 382 |
|
|
{
|
| 383 |
|
|
/* If IN_P is nonzero, the reload register will be the output in
|
| 384 |
|
|
operand 0. If IN_P is zero, the reload register will be the input
|
| 385 |
|
|
in operand 1. Outputs should have an initial "=", which we must
|
| 386 |
|
|
skip. */
|
| 387 |
|
|
|
| 388 |
|
|
/* ??? It would be useful to be able to handle only two, or more than
|
| 389 |
|
|
three, operands, but for now we can only handle the case of having
|
| 390 |
|
|
exactly three: output, input and one temp/scratch. */
|
| 391 |
|
|
gcc_assert (insn_data[(int) icode].n_operands == 3);
|
| 392 |
|
|
|
| 393 |
|
|
/* ??? We currently have no way to represent a reload that needs
|
| 394 |
|
|
an icode to reload from an intermediate tertiary reload register.
|
| 395 |
|
|
We should probably have a new field in struct reload to tag a
|
| 396 |
|
|
chain of scratch operand reloads onto. */
|
| 397 |
|
|
gcc_assert (rclass == NO_REGS);
|
| 398 |
|
|
|
| 399 |
|
|
scratch_constraint = insn_data[(int) icode].operand[2].constraint;
|
| 400 |
|
|
gcc_assert (*scratch_constraint == '=');
|
| 401 |
|
|
scratch_constraint++;
|
| 402 |
|
|
if (*scratch_constraint == '&')
|
| 403 |
|
|
scratch_constraint++;
|
| 404 |
|
|
letter = *scratch_constraint;
|
| 405 |
|
|
scratch_class = (letter == 'r' ? GENERAL_REGS
|
| 406 |
|
|
: REG_CLASS_FROM_CONSTRAINT ((unsigned char) letter,
|
| 407 |
|
|
scratch_constraint));
|
| 408 |
|
|
|
| 409 |
|
|
rclass = scratch_class;
|
| 410 |
|
|
mode = insn_data[(int) icode].operand[2].mode;
|
| 411 |
|
|
}
|
| 412 |
|
|
|
| 413 |
|
|
/* This case isn't valid, so fail. Reload is allowed to use the same
|
| 414 |
|
|
register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but
|
| 415 |
|
|
in the case of a secondary register, we actually need two different
|
| 416 |
|
|
registers for correct code. We fail here to prevent the possibility of
|
| 417 |
|
|
silently generating incorrect code later.
|
| 418 |
|
|
|
| 419 |
|
|
The convention is that secondary input reloads are valid only if the
|
| 420 |
|
|
secondary_class is different from class. If you have such a case, you
|
| 421 |
|
|
can not use secondary reloads, you must work around the problem some
|
| 422 |
|
|
other way.
|
| 423 |
|
|
|
| 424 |
|
|
Allow this when a reload_in/out pattern is being used. I.e. assume
|
| 425 |
|
|
that the generated code handles this case. */
|
| 426 |
|
|
|
| 427 |
|
|
gcc_assert (!in_p || rclass != reload_class || icode != CODE_FOR_nothing
|
| 428 |
|
|
|| t_icode != CODE_FOR_nothing);
|
| 429 |
|
|
|
| 430 |
|
|
/* See if we can reuse an existing secondary reload. */
|
| 431 |
|
|
for (s_reload = 0; s_reload < n_reloads; s_reload++)
|
| 432 |
|
|
if (rld[s_reload].secondary_p
|
| 433 |
|
|
&& (reg_class_subset_p (rclass, rld[s_reload].rclass)
|
| 434 |
|
|
|| reg_class_subset_p (rld[s_reload].rclass, rclass))
|
| 435 |
|
|
&& ((in_p && rld[s_reload].inmode == mode)
|
| 436 |
|
|
|| (! in_p && rld[s_reload].outmode == mode))
|
| 437 |
|
|
&& ((in_p && rld[s_reload].secondary_in_reload == t_reload)
|
| 438 |
|
|
|| (! in_p && rld[s_reload].secondary_out_reload == t_reload))
|
| 439 |
|
|
&& ((in_p && rld[s_reload].secondary_in_icode == t_icode)
|
| 440 |
|
|
|| (! in_p && rld[s_reload].secondary_out_icode == t_icode))
|
| 441 |
|
|
&& (SMALL_REGISTER_CLASS_P (rclass) || SMALL_REGISTER_CLASSES)
|
| 442 |
|
|
&& MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed,
|
| 443 |
|
|
opnum, rld[s_reload].opnum))
|
| 444 |
|
|
{
|
| 445 |
|
|
if (in_p)
|
| 446 |
|
|
rld[s_reload].inmode = mode;
|
| 447 |
|
|
if (! in_p)
|
| 448 |
|
|
rld[s_reload].outmode = mode;
|
| 449 |
|
|
|
| 450 |
|
|
if (reg_class_subset_p (rclass, rld[s_reload].rclass))
|
| 451 |
|
|
rld[s_reload].rclass = rclass;
|
| 452 |
|
|
|
| 453 |
|
|
rld[s_reload].opnum = MIN (rld[s_reload].opnum, opnum);
|
| 454 |
|
|
rld[s_reload].optional &= optional;
|
| 455 |
|
|
rld[s_reload].secondary_p = 1;
|
| 456 |
|
|
if (MERGE_TO_OTHER (secondary_type, rld[s_reload].when_needed,
|
| 457 |
|
|
opnum, rld[s_reload].opnum))
|
| 458 |
|
|
rld[s_reload].when_needed = RELOAD_OTHER;
|
| 459 |
|
|
|
| 460 |
|
|
break;
|
| 461 |
|
|
}
|
| 462 |
|
|
|
| 463 |
|
|
if (s_reload == n_reloads)
|
| 464 |
|
|
{
|
| 465 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 466 |
|
|
/* If we need a memory location to copy between the two reload regs,
|
| 467 |
|
|
set it up now. Note that we do the input case before making
|
| 468 |
|
|
the reload and the output case after. This is due to the
|
| 469 |
|
|
way reloads are output. */
|
| 470 |
|
|
|
| 471 |
|
|
if (in_p && icode == CODE_FOR_nothing
|
| 472 |
|
|
&& SECONDARY_MEMORY_NEEDED (rclass, reload_class, mode))
|
| 473 |
|
|
{
|
| 474 |
|
|
get_secondary_mem (x, reload_mode, opnum, type);
|
| 475 |
|
|
|
| 476 |
|
|
/* We may have just added new reloads. Make sure we add
|
| 477 |
|
|
the new reload at the end. */
|
| 478 |
|
|
s_reload = n_reloads;
|
| 479 |
|
|
}
|
| 480 |
|
|
#endif
|
| 481 |
|
|
|
| 482 |
|
|
/* We need to make a new secondary reload for this register class. */
|
| 483 |
|
|
rld[s_reload].in = rld[s_reload].out = 0;
|
| 484 |
|
|
rld[s_reload].rclass = rclass;
|
| 485 |
|
|
|
| 486 |
|
|
rld[s_reload].inmode = in_p ? mode : VOIDmode;
|
| 487 |
|
|
rld[s_reload].outmode = ! in_p ? mode : VOIDmode;
|
| 488 |
|
|
rld[s_reload].reg_rtx = 0;
|
| 489 |
|
|
rld[s_reload].optional = optional;
|
| 490 |
|
|
rld[s_reload].inc = 0;
|
| 491 |
|
|
/* Maybe we could combine these, but it seems too tricky. */
|
| 492 |
|
|
rld[s_reload].nocombine = 1;
|
| 493 |
|
|
rld[s_reload].in_reg = 0;
|
| 494 |
|
|
rld[s_reload].out_reg = 0;
|
| 495 |
|
|
rld[s_reload].opnum = opnum;
|
| 496 |
|
|
rld[s_reload].when_needed = secondary_type;
|
| 497 |
|
|
rld[s_reload].secondary_in_reload = in_p ? t_reload : -1;
|
| 498 |
|
|
rld[s_reload].secondary_out_reload = ! in_p ? t_reload : -1;
|
| 499 |
|
|
rld[s_reload].secondary_in_icode = in_p ? t_icode : CODE_FOR_nothing;
|
| 500 |
|
|
rld[s_reload].secondary_out_icode
|
| 501 |
|
|
= ! in_p ? t_icode : CODE_FOR_nothing;
|
| 502 |
|
|
rld[s_reload].secondary_p = 1;
|
| 503 |
|
|
|
| 504 |
|
|
n_reloads++;
|
| 505 |
|
|
|
| 506 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 507 |
|
|
if (! in_p && icode == CODE_FOR_nothing
|
| 508 |
|
|
&& SECONDARY_MEMORY_NEEDED (reload_class, rclass, mode))
|
| 509 |
|
|
get_secondary_mem (x, mode, opnum, type);
|
| 510 |
|
|
#endif
|
| 511 |
|
|
}
|
| 512 |
|
|
|
| 513 |
|
|
*picode = icode;
|
| 514 |
|
|
return s_reload;
|
| 515 |
|
|
}
|
| 516 |
|
|
|
| 517 |
|
|
/* If a secondary reload is needed, return its class. If both an intermediate
|
| 518 |
|
|
register and a scratch register is needed, we return the class of the
|
| 519 |
|
|
intermediate register. */
|
| 520 |
|
|
enum reg_class
|
| 521 |
|
|
secondary_reload_class (bool in_p, enum reg_class rclass,
|
| 522 |
|
|
enum machine_mode mode, rtx x)
|
| 523 |
|
|
{
|
| 524 |
|
|
enum insn_code icode;
|
| 525 |
|
|
secondary_reload_info sri;
|
| 526 |
|
|
|
| 527 |
|
|
sri.icode = CODE_FOR_nothing;
|
| 528 |
|
|
sri.prev_sri = NULL;
|
| 529 |
|
|
rclass = targetm.secondary_reload (in_p, x, rclass, mode, &sri);
|
| 530 |
|
|
icode = (enum insn_code) sri.icode;
|
| 531 |
|
|
|
| 532 |
|
|
/* If there are no secondary reloads at all, we return NO_REGS.
|
| 533 |
|
|
If an intermediate register is needed, we return its class. */
|
| 534 |
|
|
if (icode == CODE_FOR_nothing || rclass != NO_REGS)
|
| 535 |
|
|
return rclass;
|
| 536 |
|
|
|
| 537 |
|
|
/* No intermediate register is needed, but we have a special reload
|
| 538 |
|
|
pattern, which we assume for now needs a scratch register. */
|
| 539 |
|
|
return scratch_reload_class (icode);
|
| 540 |
|
|
}
|
| 541 |
|
|
|
| 542 |
|
|
/* ICODE is the insn_code of a reload pattern. Check that it has exactly
|
| 543 |
|
|
three operands, verify that operand 2 is an output operand, and return
|
| 544 |
|
|
its register class.
|
| 545 |
|
|
??? We'd like to be able to handle any pattern with at least 2 operands,
|
| 546 |
|
|
for zero or more scratch registers, but that needs more infrastructure. */
|
| 547 |
|
|
enum reg_class
|
| 548 |
|
|
scratch_reload_class (enum insn_code icode)
|
| 549 |
|
|
{
|
| 550 |
|
|
const char *scratch_constraint;
|
| 551 |
|
|
char scratch_letter;
|
| 552 |
|
|
enum reg_class rclass;
|
| 553 |
|
|
|
| 554 |
|
|
gcc_assert (insn_data[(int) icode].n_operands == 3);
|
| 555 |
|
|
scratch_constraint = insn_data[(int) icode].operand[2].constraint;
|
| 556 |
|
|
gcc_assert (*scratch_constraint == '=');
|
| 557 |
|
|
scratch_constraint++;
|
| 558 |
|
|
if (*scratch_constraint == '&')
|
| 559 |
|
|
scratch_constraint++;
|
| 560 |
|
|
scratch_letter = *scratch_constraint;
|
| 561 |
|
|
if (scratch_letter == 'r')
|
| 562 |
|
|
return GENERAL_REGS;
|
| 563 |
|
|
rclass = REG_CLASS_FROM_CONSTRAINT ((unsigned char) scratch_letter,
|
| 564 |
|
|
scratch_constraint);
|
| 565 |
|
|
gcc_assert (rclass != NO_REGS);
|
| 566 |
|
|
return rclass;
|
| 567 |
|
|
}
|
| 568 |
|
|
|
| 569 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 570 |
|
|
|
| 571 |
|
|
/* Return a memory location that will be used to copy X in mode MODE.
|
| 572 |
|
|
If we haven't already made a location for this mode in this insn,
|
| 573 |
|
|
call find_reloads_address on the location being returned. */
|
| 574 |
|
|
|
| 575 |
|
|
rtx
|
| 576 |
|
|
get_secondary_mem (rtx x ATTRIBUTE_UNUSED, enum machine_mode mode,
|
| 577 |
|
|
int opnum, enum reload_type type)
|
| 578 |
|
|
{
|
| 579 |
|
|
rtx loc;
|
| 580 |
|
|
int mem_valid;
|
| 581 |
|
|
|
| 582 |
|
|
/* By default, if MODE is narrower than a word, widen it to a word.
|
| 583 |
|
|
This is required because most machines that require these memory
|
| 584 |
|
|
locations do not support short load and stores from all registers
|
| 585 |
|
|
(e.g., FP registers). */
|
| 586 |
|
|
|
| 587 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED_MODE
|
| 588 |
|
|
mode = SECONDARY_MEMORY_NEEDED_MODE (mode);
|
| 589 |
|
|
#else
|
| 590 |
|
|
if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD && INTEGRAL_MODE_P (mode))
|
| 591 |
|
|
mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0);
|
| 592 |
|
|
#endif
|
| 593 |
|
|
|
| 594 |
|
|
/* If we already have made a MEM for this operand in MODE, return it. */
|
| 595 |
|
|
if (secondary_memlocs_elim[(int) mode][opnum] != 0)
|
| 596 |
|
|
return secondary_memlocs_elim[(int) mode][opnum];
|
| 597 |
|
|
|
| 598 |
|
|
/* If this is the first time we've tried to get a MEM for this mode,
|
| 599 |
|
|
allocate a new one. `something_changed' in reload will get set
|
| 600 |
|
|
by noticing that the frame size has changed. */
|
| 601 |
|
|
|
| 602 |
|
|
if (secondary_memlocs[(int) mode] == 0)
|
| 603 |
|
|
{
|
| 604 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED_RTX
|
| 605 |
|
|
secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode);
|
| 606 |
|
|
#else
|
| 607 |
|
|
secondary_memlocs[(int) mode]
|
| 608 |
|
|
= assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
|
| 609 |
|
|
#endif
|
| 610 |
|
|
}
|
| 611 |
|
|
|
| 612 |
|
|
/* Get a version of the address doing any eliminations needed. If that
|
| 613 |
|
|
didn't give us a new MEM, make a new one if it isn't valid. */
|
| 614 |
|
|
|
| 615 |
|
|
loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX);
|
| 616 |
|
|
mem_valid = strict_memory_address_addr_space_p (mode, XEXP (loc, 0),
|
| 617 |
|
|
MEM_ADDR_SPACE (loc));
|
| 618 |
|
|
|
| 619 |
|
|
if (! mem_valid && loc == secondary_memlocs[(int) mode])
|
| 620 |
|
|
loc = copy_rtx (loc);
|
| 621 |
|
|
|
| 622 |
|
|
/* The only time the call below will do anything is if the stack
|
| 623 |
|
|
offset is too large. In that case IND_LEVELS doesn't matter, so we
|
| 624 |
|
|
can just pass a zero. Adjust the type to be the address of the
|
| 625 |
|
|
corresponding object. If the address was valid, save the eliminated
|
| 626 |
|
|
address. If it wasn't valid, we need to make a reload each time, so
|
| 627 |
|
|
don't save it. */
|
| 628 |
|
|
|
| 629 |
|
|
if (! mem_valid)
|
| 630 |
|
|
{
|
| 631 |
|
|
type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS
|
| 632 |
|
|
: type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS
|
| 633 |
|
|
: RELOAD_OTHER);
|
| 634 |
|
|
|
| 635 |
|
|
find_reloads_address (mode, &loc, XEXP (loc, 0), &XEXP (loc, 0),
|
| 636 |
|
|
opnum, type, 0, 0);
|
| 637 |
|
|
}
|
| 638 |
|
|
|
| 639 |
|
|
secondary_memlocs_elim[(int) mode][opnum] = loc;
|
| 640 |
|
|
if (secondary_memlocs_elim_used <= (int)mode)
|
| 641 |
|
|
secondary_memlocs_elim_used = (int)mode + 1;
|
| 642 |
|
|
return loc;
|
| 643 |
|
|
}
|
| 644 |
|
|
|
| 645 |
|
|
/* Clear any secondary memory locations we've made. */
|
| 646 |
|
|
|
| 647 |
|
|
void
|
| 648 |
|
|
clear_secondary_mem (void)
|
| 649 |
|
|
{
|
| 650 |
|
|
memset (secondary_memlocs, 0, sizeof secondary_memlocs);
|
| 651 |
|
|
}
|
| 652 |
|
|
#endif /* SECONDARY_MEMORY_NEEDED */
|
| 653 |
|
|
|
| 654 |
|
|
|
| 655 |
|
|
/* Find the largest class which has at least one register valid in
|
| 656 |
|
|
mode INNER, and which for every such register, that register number
|
| 657 |
|
|
plus N is also valid in OUTER (if in range) and is cheap to move
|
| 658 |
|
|
into REGNO. Such a class must exist. */
|
| 659 |
|
|
|
| 660 |
|
|
static enum reg_class
|
| 661 |
|
|
find_valid_class (enum machine_mode outer ATTRIBUTE_UNUSED,
|
| 662 |
|
|
enum machine_mode inner ATTRIBUTE_UNUSED, int n,
|
| 663 |
|
|
unsigned int dest_regno ATTRIBUTE_UNUSED)
|
| 664 |
|
|
{
|
| 665 |
|
|
int best_cost = -1;
|
| 666 |
|
|
int rclass;
|
| 667 |
|
|
int regno;
|
| 668 |
|
|
enum reg_class best_class = NO_REGS;
|
| 669 |
|
|
enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno);
|
| 670 |
|
|
unsigned int best_size = 0;
|
| 671 |
|
|
int cost;
|
| 672 |
|
|
|
| 673 |
|
|
for (rclass = 1; rclass < N_REG_CLASSES; rclass++)
|
| 674 |
|
|
{
|
| 675 |
|
|
int bad = 0;
|
| 676 |
|
|
int good = 0;
|
| 677 |
|
|
for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++)
|
| 678 |
|
|
if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno))
|
| 679 |
|
|
{
|
| 680 |
|
|
if (HARD_REGNO_MODE_OK (regno, inner))
|
| 681 |
|
|
{
|
| 682 |
|
|
good = 1;
|
| 683 |
|
|
if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], regno + n)
|
| 684 |
|
|
|| ! HARD_REGNO_MODE_OK (regno + n, outer))
|
| 685 |
|
|
bad = 1;
|
| 686 |
|
|
}
|
| 687 |
|
|
}
|
| 688 |
|
|
|
| 689 |
|
|
if (bad || !good)
|
| 690 |
|
|
continue;
|
| 691 |
|
|
cost = REGISTER_MOVE_COST (outer, (enum reg_class) rclass, dest_class);
|
| 692 |
|
|
|
| 693 |
|
|
if ((reg_class_size[rclass] > best_size
|
| 694 |
|
|
&& (best_cost < 0 || best_cost >= cost))
|
| 695 |
|
|
|| best_cost > cost)
|
| 696 |
|
|
{
|
| 697 |
|
|
best_class = (enum reg_class) rclass;
|
| 698 |
|
|
best_size = reg_class_size[rclass];
|
| 699 |
|
|
best_cost = REGISTER_MOVE_COST (outer, (enum reg_class) rclass,
|
| 700 |
|
|
dest_class);
|
| 701 |
|
|
}
|
| 702 |
|
|
}
|
| 703 |
|
|
|
| 704 |
|
|
gcc_assert (best_size != 0);
|
| 705 |
|
|
|
| 706 |
|
|
return best_class;
|
| 707 |
|
|
}
|
| 708 |
|
|
|
| 709 |
|
|
/* Return the number of a previously made reload that can be combined with
|
| 710 |
|
|
a new one, or n_reloads if none of the existing reloads can be used.
|
| 711 |
|
|
OUT, RCLASS, TYPE and OPNUM are the same arguments as passed to
|
| 712 |
|
|
push_reload, they determine the kind of the new reload that we try to
|
| 713 |
|
|
combine. P_IN points to the corresponding value of IN, which can be
|
| 714 |
|
|
modified by this function.
|
| 715 |
|
|
DONT_SHARE is nonzero if we can't share any input-only reload for IN. */
|
| 716 |
|
|
|
| 717 |
|
|
static int
|
| 718 |
|
|
find_reusable_reload (rtx *p_in, rtx out, enum reg_class rclass,
|
| 719 |
|
|
enum reload_type type, int opnum, int dont_share)
|
| 720 |
|
|
{
|
| 721 |
|
|
rtx in = *p_in;
|
| 722 |
|
|
int i;
|
| 723 |
|
|
/* We can't merge two reloads if the output of either one is
|
| 724 |
|
|
earlyclobbered. */
|
| 725 |
|
|
|
| 726 |
|
|
if (earlyclobber_operand_p (out))
|
| 727 |
|
|
return n_reloads;
|
| 728 |
|
|
|
| 729 |
|
|
/* We can use an existing reload if the class is right
|
| 730 |
|
|
and at least one of IN and OUT is a match
|
| 731 |
|
|
and the other is at worst neutral.
|
| 732 |
|
|
(A zero compared against anything is neutral.)
|
| 733 |
|
|
|
| 734 |
|
|
If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are
|
| 735 |
|
|
for the same thing since that can cause us to need more reload registers
|
| 736 |
|
|
than we otherwise would. */
|
| 737 |
|
|
|
| 738 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 739 |
|
|
if ((reg_class_subset_p (rclass, rld[i].rclass)
|
| 740 |
|
|
|| reg_class_subset_p (rld[i].rclass, rclass))
|
| 741 |
|
|
/* If the existing reload has a register, it must fit our class. */
|
| 742 |
|
|
&& (rld[i].reg_rtx == 0
|
| 743 |
|
|
|| TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
|
| 744 |
|
|
true_regnum (rld[i].reg_rtx)))
|
| 745 |
|
|
&& ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share
|
| 746 |
|
|
&& (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out)))
|
| 747 |
|
|
|| (out != 0 && MATCHES (rld[i].out, out)
|
| 748 |
|
|
&& (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in))))
|
| 749 |
|
|
&& (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
|
| 750 |
|
|
&& (SMALL_REGISTER_CLASS_P (rclass) || SMALL_REGISTER_CLASSES)
|
| 751 |
|
|
&& MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum))
|
| 752 |
|
|
return i;
|
| 753 |
|
|
|
| 754 |
|
|
/* Reloading a plain reg for input can match a reload to postincrement
|
| 755 |
|
|
that reg, since the postincrement's value is the right value.
|
| 756 |
|
|
Likewise, it can match a preincrement reload, since we regard
|
| 757 |
|
|
the preincrementation as happening before any ref in this insn
|
| 758 |
|
|
to that register. */
|
| 759 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 760 |
|
|
if ((reg_class_subset_p (rclass, rld[i].rclass)
|
| 761 |
|
|
|| reg_class_subset_p (rld[i].rclass, rclass))
|
| 762 |
|
|
/* If the existing reload has a register, it must fit our
|
| 763 |
|
|
class. */
|
| 764 |
|
|
&& (rld[i].reg_rtx == 0
|
| 765 |
|
|
|| TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
|
| 766 |
|
|
true_regnum (rld[i].reg_rtx)))
|
| 767 |
|
|
&& out == 0 && rld[i].out == 0 && rld[i].in != 0
|
| 768 |
|
|
&& ((REG_P (in)
|
| 769 |
|
|
&& GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC
|
| 770 |
|
|
&& MATCHES (XEXP (rld[i].in, 0), in))
|
| 771 |
|
|
|| (REG_P (rld[i].in)
|
| 772 |
|
|
&& GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC
|
| 773 |
|
|
&& MATCHES (XEXP (in, 0), rld[i].in)))
|
| 774 |
|
|
&& (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
|
| 775 |
|
|
&& (SMALL_REGISTER_CLASS_P (rclass) || SMALL_REGISTER_CLASSES)
|
| 776 |
|
|
&& MERGABLE_RELOADS (type, rld[i].when_needed,
|
| 777 |
|
|
opnum, rld[i].opnum))
|
| 778 |
|
|
{
|
| 779 |
|
|
/* Make sure reload_in ultimately has the increment,
|
| 780 |
|
|
not the plain register. */
|
| 781 |
|
|
if (REG_P (in))
|
| 782 |
|
|
*p_in = rld[i].in;
|
| 783 |
|
|
return i;
|
| 784 |
|
|
}
|
| 785 |
|
|
return n_reloads;
|
| 786 |
|
|
}
|
| 787 |
|
|
|
| 788 |
|
|
/* Return nonzero if X is a SUBREG which will require reloading of its
|
| 789 |
|
|
SUBREG_REG expression. */
|
| 790 |
|
|
|
| 791 |
|
|
static int
|
| 792 |
|
|
reload_inner_reg_of_subreg (rtx x, enum machine_mode mode, int output)
|
| 793 |
|
|
{
|
| 794 |
|
|
rtx inner;
|
| 795 |
|
|
|
| 796 |
|
|
/* Only SUBREGs are problematical. */
|
| 797 |
|
|
if (GET_CODE (x) != SUBREG)
|
| 798 |
|
|
return 0;
|
| 799 |
|
|
|
| 800 |
|
|
inner = SUBREG_REG (x);
|
| 801 |
|
|
|
| 802 |
|
|
/* If INNER is a constant or PLUS, then INNER must be reloaded. */
|
| 803 |
|
|
if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS)
|
| 804 |
|
|
return 1;
|
| 805 |
|
|
|
| 806 |
|
|
/* If INNER is not a hard register, then INNER will not need to
|
| 807 |
|
|
be reloaded. */
|
| 808 |
|
|
if (!REG_P (inner)
|
| 809 |
|
|
|| REGNO (inner) >= FIRST_PSEUDO_REGISTER)
|
| 810 |
|
|
return 0;
|
| 811 |
|
|
|
| 812 |
|
|
/* If INNER is not ok for MODE, then INNER will need reloading. */
|
| 813 |
|
|
if (! HARD_REGNO_MODE_OK (subreg_regno (x), mode))
|
| 814 |
|
|
return 1;
|
| 815 |
|
|
|
| 816 |
|
|
/* If the outer part is a word or smaller, INNER larger than a
|
| 817 |
|
|
word and the number of regs for INNER is not the same as the
|
| 818 |
|
|
number of words in INNER, then INNER will need reloading. */
|
| 819 |
|
|
return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|
| 820 |
|
|
&& output
|
| 821 |
|
|
&& GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
|
| 822 |
|
|
&& ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
|
| 823 |
|
|
!= (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
|
| 824 |
|
|
}
|
| 825 |
|
|
|
| 826 |
|
|
/* Return nonzero if IN can be reloaded into REGNO with mode MODE without
|
| 827 |
|
|
requiring an extra reload register. The caller has already found that
|
| 828 |
|
|
IN contains some reference to REGNO, so check that we can produce the
|
| 829 |
|
|
new value in a single step. E.g. if we have
|
| 830 |
|
|
(set (reg r13) (plus (reg r13) (const int 1))), and there is an
|
| 831 |
|
|
instruction that adds one to a register, this should succeed.
|
| 832 |
|
|
However, if we have something like
|
| 833 |
|
|
(set (reg r13) (plus (reg r13) (const int 999))), and the constant 999
|
| 834 |
|
|
needs to be loaded into a register first, we need a separate reload
|
| 835 |
|
|
register.
|
| 836 |
|
|
Such PLUS reloads are generated by find_reload_address_part.
|
| 837 |
|
|
The out-of-range PLUS expressions are usually introduced in the instruction
|
| 838 |
|
|
patterns by register elimination and substituting pseudos without a home
|
| 839 |
|
|
by their function-invariant equivalences. */
|
| 840 |
|
|
static int
|
| 841 |
|
|
can_reload_into (rtx in, int regno, enum machine_mode mode)
|
| 842 |
|
|
{
|
| 843 |
|
|
rtx dst, test_insn;
|
| 844 |
|
|
int r = 0;
|
| 845 |
|
|
struct recog_data save_recog_data;
|
| 846 |
|
|
|
| 847 |
|
|
/* For matching constraints, we often get notional input reloads where
|
| 848 |
|
|
we want to use the original register as the reload register. I.e.
|
| 849 |
|
|
technically this is a non-optional input-output reload, but IN is
|
| 850 |
|
|
already a valid register, and has been chosen as the reload register.
|
| 851 |
|
|
Speed this up, since it trivially works. */
|
| 852 |
|
|
if (REG_P (in))
|
| 853 |
|
|
return 1;
|
| 854 |
|
|
|
| 855 |
|
|
/* To test MEMs properly, we'd have to take into account all the reloads
|
| 856 |
|
|
that are already scheduled, which can become quite complicated.
|
| 857 |
|
|
And since we've already handled address reloads for this MEM, it
|
| 858 |
|
|
should always succeed anyway. */
|
| 859 |
|
|
if (MEM_P (in))
|
| 860 |
|
|
return 1;
|
| 861 |
|
|
|
| 862 |
|
|
/* If we can make a simple SET insn that does the job, everything should
|
| 863 |
|
|
be fine. */
|
| 864 |
|
|
dst = gen_rtx_REG (mode, regno);
|
| 865 |
|
|
test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in));
|
| 866 |
|
|
save_recog_data = recog_data;
|
| 867 |
|
|
if (recog_memoized (test_insn) >= 0)
|
| 868 |
|
|
{
|
| 869 |
|
|
extract_insn (test_insn);
|
| 870 |
|
|
r = constrain_operands (1);
|
| 871 |
|
|
}
|
| 872 |
|
|
recog_data = save_recog_data;
|
| 873 |
|
|
return r;
|
| 874 |
|
|
}
|
| 875 |
|
|
|
| 876 |
|
|
/* Record one reload that needs to be performed.
|
| 877 |
|
|
IN is an rtx saying where the data are to be found before this instruction.
|
| 878 |
|
|
OUT says where they must be stored after the instruction.
|
| 879 |
|
|
(IN is zero for data not read, and OUT is zero for data not written.)
|
| 880 |
|
|
INLOC and OUTLOC point to the places in the instructions where
|
| 881 |
|
|
IN and OUT were found.
|
| 882 |
|
|
If IN and OUT are both nonzero, it means the same register must be used
|
| 883 |
|
|
to reload both IN and OUT.
|
| 884 |
|
|
|
| 885 |
|
|
RCLASS is a register class required for the reloaded data.
|
| 886 |
|
|
INMODE is the machine mode that the instruction requires
|
| 887 |
|
|
for the reg that replaces IN and OUTMODE is likewise for OUT.
|
| 888 |
|
|
|
| 889 |
|
|
If IN is zero, then OUT's location and mode should be passed as
|
| 890 |
|
|
INLOC and INMODE.
|
| 891 |
|
|
|
| 892 |
|
|
STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx.
|
| 893 |
|
|
|
| 894 |
|
|
OPTIONAL nonzero means this reload does not need to be performed:
|
| 895 |
|
|
it can be discarded if that is more convenient.
|
| 896 |
|
|
|
| 897 |
|
|
OPNUM and TYPE say what the purpose of this reload is.
|
| 898 |
|
|
|
| 899 |
|
|
The return value is the reload-number for this reload.
|
| 900 |
|
|
|
| 901 |
|
|
If both IN and OUT are nonzero, in some rare cases we might
|
| 902 |
|
|
want to make two separate reloads. (Actually we never do this now.)
|
| 903 |
|
|
Therefore, the reload-number for OUT is stored in
|
| 904 |
|
|
output_reloadnum when we return; the return value applies to IN.
|
| 905 |
|
|
Usually (presently always), when IN and OUT are nonzero,
|
| 906 |
|
|
the two reload-numbers are equal, but the caller should be careful to
|
| 907 |
|
|
distinguish them. */
|
| 908 |
|
|
|
| 909 |
|
|
int
|
| 910 |
|
|
push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
|
| 911 |
|
|
enum reg_class rclass, enum machine_mode inmode,
|
| 912 |
|
|
enum machine_mode outmode, int strict_low, int optional,
|
| 913 |
|
|
int opnum, enum reload_type type)
|
| 914 |
|
|
{
|
| 915 |
|
|
int i;
|
| 916 |
|
|
int dont_share = 0;
|
| 917 |
|
|
int dont_remove_subreg = 0;
|
| 918 |
|
|
rtx *in_subreg_loc = 0, *out_subreg_loc = 0;
|
| 919 |
|
|
int secondary_in_reload = -1, secondary_out_reload = -1;
|
| 920 |
|
|
enum insn_code secondary_in_icode = CODE_FOR_nothing;
|
| 921 |
|
|
enum insn_code secondary_out_icode = CODE_FOR_nothing;
|
| 922 |
|
|
|
| 923 |
|
|
/* INMODE and/or OUTMODE could be VOIDmode if no mode
|
| 924 |
|
|
has been specified for the operand. In that case,
|
| 925 |
|
|
use the operand's mode as the mode to reload. */
|
| 926 |
|
|
if (inmode == VOIDmode && in != 0)
|
| 927 |
|
|
inmode = GET_MODE (in);
|
| 928 |
|
|
if (outmode == VOIDmode && out != 0)
|
| 929 |
|
|
outmode = GET_MODE (out);
|
| 930 |
|
|
|
| 931 |
|
|
/* If find_reloads and friends until now missed to replace a pseudo
|
| 932 |
|
|
with a constant of reg_equiv_constant something went wrong
|
| 933 |
|
|
beforehand.
|
| 934 |
|
|
Note that it can't simply be done here if we missed it earlier
|
| 935 |
|
|
since the constant might need to be pushed into the literal pool
|
| 936 |
|
|
and the resulting memref would probably need further
|
| 937 |
|
|
reloading. */
|
| 938 |
|
|
if (in != 0 && REG_P (in))
|
| 939 |
|
|
{
|
| 940 |
|
|
int regno = REGNO (in);
|
| 941 |
|
|
|
| 942 |
|
|
gcc_assert (regno < FIRST_PSEUDO_REGISTER
|
| 943 |
|
|
|| reg_renumber[regno] >= 0
|
| 944 |
|
|
|| reg_equiv_constant[regno] == NULL_RTX);
|
| 945 |
|
|
}
|
| 946 |
|
|
|
| 947 |
|
|
/* reg_equiv_constant only contains constants which are obviously
|
| 948 |
|
|
not appropriate as destination. So if we would need to replace
|
| 949 |
|
|
the destination pseudo with a constant we are in real
|
| 950 |
|
|
trouble. */
|
| 951 |
|
|
if (out != 0 && REG_P (out))
|
| 952 |
|
|
{
|
| 953 |
|
|
int regno = REGNO (out);
|
| 954 |
|
|
|
| 955 |
|
|
gcc_assert (regno < FIRST_PSEUDO_REGISTER
|
| 956 |
|
|
|| reg_renumber[regno] >= 0
|
| 957 |
|
|
|| reg_equiv_constant[regno] == NULL_RTX);
|
| 958 |
|
|
}
|
| 959 |
|
|
|
| 960 |
|
|
/* If we have a read-write operand with an address side-effect,
|
| 961 |
|
|
change either IN or OUT so the side-effect happens only once. */
|
| 962 |
|
|
if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out))
|
| 963 |
|
|
switch (GET_CODE (XEXP (in, 0)))
|
| 964 |
|
|
{
|
| 965 |
|
|
case POST_INC: case POST_DEC: case POST_MODIFY:
|
| 966 |
|
|
in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0));
|
| 967 |
|
|
break;
|
| 968 |
|
|
|
| 969 |
|
|
case PRE_INC: case PRE_DEC: case PRE_MODIFY:
|
| 970 |
|
|
out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0));
|
| 971 |
|
|
break;
|
| 972 |
|
|
|
| 973 |
|
|
default:
|
| 974 |
|
|
break;
|
| 975 |
|
|
}
|
| 976 |
|
|
|
| 977 |
|
|
/* If we are reloading a (SUBREG constant ...), really reload just the
|
| 978 |
|
|
inside expression in its own mode. Similarly for (SUBREG (PLUS ...)).
|
| 979 |
|
|
If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still
|
| 980 |
|
|
a pseudo and hence will become a MEM) with M1 wider than M2 and the
|
| 981 |
|
|
register is a pseudo, also reload the inside expression.
|
| 982 |
|
|
For machines that extend byte loads, do this for any SUBREG of a pseudo
|
| 983 |
|
|
where both M1 and M2 are a word or smaller, M1 is wider than M2, and
|
| 984 |
|
|
M2 is an integral mode that gets extended when loaded.
|
| 985 |
|
|
Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
|
| 986 |
|
|
either M1 is not valid for R or M2 is wider than a word but we only
|
| 987 |
|
|
need one word to store an M2-sized quantity in R.
|
| 988 |
|
|
(However, if OUT is nonzero, we need to reload the reg *and*
|
| 989 |
|
|
the subreg, so do nothing here, and let following statement handle it.)
|
| 990 |
|
|
|
| 991 |
|
|
Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere;
|
| 992 |
|
|
we can't handle it here because CONST_INT does not indicate a mode.
|
| 993 |
|
|
|
| 994 |
|
|
Similarly, we must reload the inside expression if we have a
|
| 995 |
|
|
STRICT_LOW_PART (presumably, in == out in this case).
|
| 996 |
|
|
|
| 997 |
|
|
Also reload the inner expression if it does not require a secondary
|
| 998 |
|
|
reload but the SUBREG does.
|
| 999 |
|
|
|
| 1000 |
|
|
Finally, reload the inner expression if it is a register that is in
|
| 1001 |
|
|
the class whose registers cannot be referenced in a different size
|
| 1002 |
|
|
and M1 is not the same size as M2. If subreg_lowpart_p is false, we
|
| 1003 |
|
|
cannot reload just the inside since we might end up with the wrong
|
| 1004 |
|
|
register class. But if it is inside a STRICT_LOW_PART, we have
|
| 1005 |
|
|
no choice, so we hope we do get the right register class there. */
|
| 1006 |
|
|
|
| 1007 |
|
|
if (in != 0 && GET_CODE (in) == SUBREG
|
| 1008 |
|
|
&& (subreg_lowpart_p (in) || strict_low)
|
| 1009 |
|
|
#ifdef CANNOT_CHANGE_MODE_CLASS
|
| 1010 |
|
|
&& !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, rclass)
|
| 1011 |
|
|
#endif
|
| 1012 |
|
|
&& (CONSTANT_P (SUBREG_REG (in))
|
| 1013 |
|
|
|| GET_CODE (SUBREG_REG (in)) == PLUS
|
| 1014 |
|
|
|| strict_low
|
| 1015 |
|
|
|| (((REG_P (SUBREG_REG (in))
|
| 1016 |
|
|
&& REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)
|
| 1017 |
|
|
|| MEM_P (SUBREG_REG (in)))
|
| 1018 |
|
|
&& ((GET_MODE_SIZE (inmode)
|
| 1019 |
|
|
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
|
| 1020 |
|
|
#ifdef LOAD_EXTEND_OP
|
| 1021 |
|
|
|| (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
|
| 1022 |
|
|
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
|
| 1023 |
|
|
<= UNITS_PER_WORD)
|
| 1024 |
|
|
&& (GET_MODE_SIZE (inmode)
|
| 1025 |
|
|
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
|
| 1026 |
|
|
&& INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in)))
|
| 1027 |
|
|
&& LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN)
|
| 1028 |
|
|
#endif
|
| 1029 |
|
|
#ifdef WORD_REGISTER_OPERATIONS
|
| 1030 |
|
|
|| ((GET_MODE_SIZE (inmode)
|
| 1031 |
|
|
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
|
| 1032 |
|
|
&& ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD ==
|
| 1033 |
|
|
((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1)
|
| 1034 |
|
|
/ UNITS_PER_WORD)))
|
| 1035 |
|
|
#endif
|
| 1036 |
|
|
))
|
| 1037 |
|
|
|| (REG_P (SUBREG_REG (in))
|
| 1038 |
|
|
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
|
| 1039 |
|
|
/* The case where out is nonzero
|
| 1040 |
|
|
is handled differently in the following statement. */
|
| 1041 |
|
|
&& (out == 0 || subreg_lowpart_p (in))
|
| 1042 |
|
|
&& ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
|
| 1043 |
|
|
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
|
| 1044 |
|
|
> UNITS_PER_WORD)
|
| 1045 |
|
|
&& ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
|
| 1046 |
|
|
/ UNITS_PER_WORD)
|
| 1047 |
|
|
!= (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
|
| 1048 |
|
|
[GET_MODE (SUBREG_REG (in))]))
|
| 1049 |
|
|
|| ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
|
| 1050 |
|
|
|| (secondary_reload_class (1, rclass, inmode, in) != NO_REGS
|
| 1051 |
|
|
&& (secondary_reload_class (1, rclass, GET_MODE (SUBREG_REG (in)),
|
| 1052 |
|
|
SUBREG_REG (in))
|
| 1053 |
|
|
== NO_REGS))
|
| 1054 |
|
|
#ifdef CANNOT_CHANGE_MODE_CLASS
|
| 1055 |
|
|
|| (REG_P (SUBREG_REG (in))
|
| 1056 |
|
|
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
|
| 1057 |
|
|
&& REG_CANNOT_CHANGE_MODE_P
|
| 1058 |
|
|
(REGNO (SUBREG_REG (in)), GET_MODE (SUBREG_REG (in)), inmode))
|
| 1059 |
|
|
#endif
|
| 1060 |
|
|
))
|
| 1061 |
|
|
{
|
| 1062 |
|
|
in_subreg_loc = inloc;
|
| 1063 |
|
|
inloc = &SUBREG_REG (in);
|
| 1064 |
|
|
in = *inloc;
|
| 1065 |
|
|
#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
|
| 1066 |
|
|
if (MEM_P (in))
|
| 1067 |
|
|
/* This is supposed to happen only for paradoxical subregs made by
|
| 1068 |
|
|
combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
|
| 1069 |
|
|
gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode));
|
| 1070 |
|
|
#endif
|
| 1071 |
|
|
inmode = GET_MODE (in);
|
| 1072 |
|
|
}
|
| 1073 |
|
|
|
| 1074 |
|
|
/* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
|
| 1075 |
|
|
either M1 is not valid for R or M2 is wider than a word but we only
|
| 1076 |
|
|
need one word to store an M2-sized quantity in R.
|
| 1077 |
|
|
|
| 1078 |
|
|
However, we must reload the inner reg *as well as* the subreg in
|
| 1079 |
|
|
that case. */
|
| 1080 |
|
|
|
| 1081 |
|
|
/* Similar issue for (SUBREG constant ...) if it was not handled by the
|
| 1082 |
|
|
code above. This can happen if SUBREG_BYTE != 0. */
|
| 1083 |
|
|
|
| 1084 |
|
|
if (in != 0 && reload_inner_reg_of_subreg (in, inmode, 0))
|
| 1085 |
|
|
{
|
| 1086 |
|
|
enum reg_class in_class = rclass;
|
| 1087 |
|
|
|
| 1088 |
|
|
if (REG_P (SUBREG_REG (in)))
|
| 1089 |
|
|
in_class
|
| 1090 |
|
|
= find_valid_class (inmode, GET_MODE (SUBREG_REG (in)),
|
| 1091 |
|
|
subreg_regno_offset (REGNO (SUBREG_REG (in)),
|
| 1092 |
|
|
GET_MODE (SUBREG_REG (in)),
|
| 1093 |
|
|
SUBREG_BYTE (in),
|
| 1094 |
|
|
GET_MODE (in)),
|
| 1095 |
|
|
REGNO (SUBREG_REG (in)));
|
| 1096 |
|
|
|
| 1097 |
|
|
/* This relies on the fact that emit_reload_insns outputs the
|
| 1098 |
|
|
instructions for input reloads of type RELOAD_OTHER in the same
|
| 1099 |
|
|
order as the reloads. Thus if the outer reload is also of type
|
| 1100 |
|
|
RELOAD_OTHER, we are guaranteed that this inner reload will be
|
| 1101 |
|
|
output before the outer reload. */
|
| 1102 |
|
|
push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), (rtx *) 0,
|
| 1103 |
|
|
in_class, VOIDmode, VOIDmode, 0, 0, opnum, type);
|
| 1104 |
|
|
dont_remove_subreg = 1;
|
| 1105 |
|
|
}
|
| 1106 |
|
|
|
| 1107 |
|
|
/* Similarly for paradoxical and problematical SUBREGs on the output.
|
| 1108 |
|
|
Note that there is no reason we need worry about the previous value
|
| 1109 |
|
|
of SUBREG_REG (out); even if wider than out,
|
| 1110 |
|
|
storing in a subreg is entitled to clobber it all
|
| 1111 |
|
|
(except in the case of STRICT_LOW_PART,
|
| 1112 |
|
|
and in that case the constraint should label it input-output.) */
|
| 1113 |
|
|
if (out != 0 && GET_CODE (out) == SUBREG
|
| 1114 |
|
|
&& (subreg_lowpart_p (out) || strict_low)
|
| 1115 |
|
|
#ifdef CANNOT_CHANGE_MODE_CLASS
|
| 1116 |
|
|
&& !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, rclass)
|
| 1117 |
|
|
#endif
|
| 1118 |
|
|
&& (CONSTANT_P (SUBREG_REG (out))
|
| 1119 |
|
|
|| strict_low
|
| 1120 |
|
|
|| (((REG_P (SUBREG_REG (out))
|
| 1121 |
|
|
&& REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER)
|
| 1122 |
|
|
|| MEM_P (SUBREG_REG (out)))
|
| 1123 |
|
|
&& ((GET_MODE_SIZE (outmode)
|
| 1124 |
|
|
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
|
| 1125 |
|
|
#ifdef WORD_REGISTER_OPERATIONS
|
| 1126 |
|
|
|| ((GET_MODE_SIZE (outmode)
|
| 1127 |
|
|
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
|
| 1128 |
|
|
&& ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD ==
|
| 1129 |
|
|
((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1)
|
| 1130 |
|
|
/ UNITS_PER_WORD)))
|
| 1131 |
|
|
#endif
|
| 1132 |
|
|
))
|
| 1133 |
|
|
|| (REG_P (SUBREG_REG (out))
|
| 1134 |
|
|
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
|
| 1135 |
|
|
&& ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
|
| 1136 |
|
|
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
|
| 1137 |
|
|
> UNITS_PER_WORD)
|
| 1138 |
|
|
&& ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
|
| 1139 |
|
|
/ UNITS_PER_WORD)
|
| 1140 |
|
|
!= (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
|
| 1141 |
|
|
[GET_MODE (SUBREG_REG (out))]))
|
| 1142 |
|
|
|| ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
|
| 1143 |
|
|
|| (secondary_reload_class (0, rclass, outmode, out) != NO_REGS
|
| 1144 |
|
|
&& (secondary_reload_class (0, rclass, GET_MODE (SUBREG_REG (out)),
|
| 1145 |
|
|
SUBREG_REG (out))
|
| 1146 |
|
|
== NO_REGS))
|
| 1147 |
|
|
#ifdef CANNOT_CHANGE_MODE_CLASS
|
| 1148 |
|
|
|| (REG_P (SUBREG_REG (out))
|
| 1149 |
|
|
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
|
| 1150 |
|
|
&& REG_CANNOT_CHANGE_MODE_P (REGNO (SUBREG_REG (out)),
|
| 1151 |
|
|
GET_MODE (SUBREG_REG (out)),
|
| 1152 |
|
|
outmode))
|
| 1153 |
|
|
#endif
|
| 1154 |
|
|
))
|
| 1155 |
|
|
{
|
| 1156 |
|
|
out_subreg_loc = outloc;
|
| 1157 |
|
|
outloc = &SUBREG_REG (out);
|
| 1158 |
|
|
out = *outloc;
|
| 1159 |
|
|
#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
|
| 1160 |
|
|
gcc_assert (!MEM_P (out)
|
| 1161 |
|
|
|| GET_MODE_SIZE (GET_MODE (out))
|
| 1162 |
|
|
<= GET_MODE_SIZE (outmode));
|
| 1163 |
|
|
#endif
|
| 1164 |
|
|
outmode = GET_MODE (out);
|
| 1165 |
|
|
}
|
| 1166 |
|
|
|
| 1167 |
|
|
/* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
|
| 1168 |
|
|
either M1 is not valid for R or M2 is wider than a word but we only
|
| 1169 |
|
|
need one word to store an M2-sized quantity in R.
|
| 1170 |
|
|
|
| 1171 |
|
|
However, we must reload the inner reg *as well as* the subreg in
|
| 1172 |
|
|
that case. In this case, the inner reg is an in-out reload. */
|
| 1173 |
|
|
|
| 1174 |
|
|
if (out != 0 && reload_inner_reg_of_subreg (out, outmode, 1))
|
| 1175 |
|
|
{
|
| 1176 |
|
|
/* This relies on the fact that emit_reload_insns outputs the
|
| 1177 |
|
|
instructions for output reloads of type RELOAD_OTHER in reverse
|
| 1178 |
|
|
order of the reloads. Thus if the outer reload is also of type
|
| 1179 |
|
|
RELOAD_OTHER, we are guaranteed that this inner reload will be
|
| 1180 |
|
|
output after the outer reload. */
|
| 1181 |
|
|
dont_remove_subreg = 1;
|
| 1182 |
|
|
push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out),
|
| 1183 |
|
|
&SUBREG_REG (out),
|
| 1184 |
|
|
find_valid_class (outmode, GET_MODE (SUBREG_REG (out)),
|
| 1185 |
|
|
subreg_regno_offset (REGNO (SUBREG_REG (out)),
|
| 1186 |
|
|
GET_MODE (SUBREG_REG (out)),
|
| 1187 |
|
|
SUBREG_BYTE (out),
|
| 1188 |
|
|
GET_MODE (out)),
|
| 1189 |
|
|
REGNO (SUBREG_REG (out))),
|
| 1190 |
|
|
VOIDmode, VOIDmode, 0, 0,
|
| 1191 |
|
|
opnum, RELOAD_OTHER);
|
| 1192 |
|
|
}
|
| 1193 |
|
|
|
| 1194 |
|
|
/* If IN appears in OUT, we can't share any input-only reload for IN. */
|
| 1195 |
|
|
if (in != 0 && out != 0 && MEM_P (out)
|
| 1196 |
|
|
&& (REG_P (in) || MEM_P (in) || GET_CODE (in) == PLUS)
|
| 1197 |
|
|
&& reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0)))
|
| 1198 |
|
|
dont_share = 1;
|
| 1199 |
|
|
|
| 1200 |
|
|
/* If IN is a SUBREG of a hard register, make a new REG. This
|
| 1201 |
|
|
simplifies some of the cases below. */
|
| 1202 |
|
|
|
| 1203 |
|
|
if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
|
| 1204 |
|
|
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
|
| 1205 |
|
|
&& ! dont_remove_subreg)
|
| 1206 |
|
|
in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
|
| 1207 |
|
|
|
| 1208 |
|
|
/* Similarly for OUT. */
|
| 1209 |
|
|
if (out != 0 && GET_CODE (out) == SUBREG
|
| 1210 |
|
|
&& REG_P (SUBREG_REG (out))
|
| 1211 |
|
|
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
|
| 1212 |
|
|
&& ! dont_remove_subreg)
|
| 1213 |
|
|
out = gen_rtx_REG (GET_MODE (out), subreg_regno (out));
|
| 1214 |
|
|
|
| 1215 |
|
|
/* Narrow down the class of register wanted if that is
|
| 1216 |
|
|
desirable on this machine for efficiency. */
|
| 1217 |
|
|
{
|
| 1218 |
|
|
enum reg_class preferred_class = rclass;
|
| 1219 |
|
|
|
| 1220 |
|
|
if (in != 0)
|
| 1221 |
|
|
preferred_class = PREFERRED_RELOAD_CLASS (in, rclass);
|
| 1222 |
|
|
|
| 1223 |
|
|
/* Output reloads may need analogous treatment, different in detail. */
|
| 1224 |
|
|
#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
|
| 1225 |
|
|
if (out != 0)
|
| 1226 |
|
|
preferred_class = PREFERRED_OUTPUT_RELOAD_CLASS (out, preferred_class);
|
| 1227 |
|
|
#endif
|
| 1228 |
|
|
|
| 1229 |
|
|
/* Discard what the target said if we cannot do it. */
|
| 1230 |
|
|
if (preferred_class != NO_REGS
|
| 1231 |
|
|
|| (optional && type == RELOAD_FOR_OUTPUT))
|
| 1232 |
|
|
rclass = preferred_class;
|
| 1233 |
|
|
}
|
| 1234 |
|
|
|
| 1235 |
|
|
/* Make sure we use a class that can handle the actual pseudo
|
| 1236 |
|
|
inside any subreg. For example, on the 386, QImode regs
|
| 1237 |
|
|
can appear within SImode subregs. Although GENERAL_REGS
|
| 1238 |
|
|
can handle SImode, QImode needs a smaller class. */
|
| 1239 |
|
|
#ifdef LIMIT_RELOAD_CLASS
|
| 1240 |
|
|
if (in_subreg_loc)
|
| 1241 |
|
|
rclass = LIMIT_RELOAD_CLASS (inmode, rclass);
|
| 1242 |
|
|
else if (in != 0 && GET_CODE (in) == SUBREG)
|
| 1243 |
|
|
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass);
|
| 1244 |
|
|
|
| 1245 |
|
|
if (out_subreg_loc)
|
| 1246 |
|
|
rclass = LIMIT_RELOAD_CLASS (outmode, rclass);
|
| 1247 |
|
|
if (out != 0 && GET_CODE (out) == SUBREG)
|
| 1248 |
|
|
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass);
|
| 1249 |
|
|
#endif
|
| 1250 |
|
|
|
| 1251 |
|
|
/* Verify that this class is at least possible for the mode that
|
| 1252 |
|
|
is specified. */
|
| 1253 |
|
|
if (this_insn_is_asm)
|
| 1254 |
|
|
{
|
| 1255 |
|
|
enum machine_mode mode;
|
| 1256 |
|
|
if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
|
| 1257 |
|
|
mode = inmode;
|
| 1258 |
|
|
else
|
| 1259 |
|
|
mode = outmode;
|
| 1260 |
|
|
if (mode == VOIDmode)
|
| 1261 |
|
|
{
|
| 1262 |
|
|
error_for_asm (this_insn, "cannot reload integer constant "
|
| 1263 |
|
|
"operand in %<asm%>");
|
| 1264 |
|
|
mode = word_mode;
|
| 1265 |
|
|
if (in != 0)
|
| 1266 |
|
|
inmode = word_mode;
|
| 1267 |
|
|
if (out != 0)
|
| 1268 |
|
|
outmode = word_mode;
|
| 1269 |
|
|
}
|
| 1270 |
|
|
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
| 1271 |
|
|
if (HARD_REGNO_MODE_OK (i, mode)
|
| 1272 |
|
|
&& in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, i))
|
| 1273 |
|
|
break;
|
| 1274 |
|
|
if (i == FIRST_PSEUDO_REGISTER)
|
| 1275 |
|
|
{
|
| 1276 |
|
|
error_for_asm (this_insn, "impossible register constraint "
|
| 1277 |
|
|
"in %<asm%>");
|
| 1278 |
|
|
/* Avoid further trouble with this insn. */
|
| 1279 |
|
|
PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
|
| 1280 |
|
|
/* We used to continue here setting class to ALL_REGS, but it triggers
|
| 1281 |
|
|
sanity check on i386 for:
|
| 1282 |
|
|
void foo(long double d)
|
| 1283 |
|
|
{
|
| 1284 |
|
|
asm("" :: "a" (d));
|
| 1285 |
|
|
}
|
| 1286 |
|
|
Returning zero here ought to be safe as we take care in
|
| 1287 |
|
|
find_reloads to not process the reloads when instruction was
|
| 1288 |
|
|
replaced by USE. */
|
| 1289 |
|
|
|
| 1290 |
|
|
return 0;
|
| 1291 |
|
|
}
|
| 1292 |
|
|
}
|
| 1293 |
|
|
|
| 1294 |
|
|
/* Optional output reloads are always OK even if we have no register class,
|
| 1295 |
|
|
since the function of these reloads is only to have spill_reg_store etc.
|
| 1296 |
|
|
set, so that the storing insn can be deleted later. */
|
| 1297 |
|
|
gcc_assert (rclass != NO_REGS
|
| 1298 |
|
|
|| (optional != 0 && type == RELOAD_FOR_OUTPUT));
|
| 1299 |
|
|
|
| 1300 |
|
|
i = find_reusable_reload (&in, out, rclass, type, opnum, dont_share);
|
| 1301 |
|
|
|
| 1302 |
|
|
if (i == n_reloads)
|
| 1303 |
|
|
{
|
| 1304 |
|
|
/* See if we need a secondary reload register to move between CLASS
|
| 1305 |
|
|
and IN or CLASS and OUT. Get the icode and push any required reloads
|
| 1306 |
|
|
needed for each of them if so. */
|
| 1307 |
|
|
|
| 1308 |
|
|
if (in != 0)
|
| 1309 |
|
|
secondary_in_reload
|
| 1310 |
|
|
= push_secondary_reload (1, in, opnum, optional, rclass, inmode, type,
|
| 1311 |
|
|
&secondary_in_icode, NULL);
|
| 1312 |
|
|
if (out != 0 && GET_CODE (out) != SCRATCH)
|
| 1313 |
|
|
secondary_out_reload
|
| 1314 |
|
|
= push_secondary_reload (0, out, opnum, optional, rclass, outmode,
|
| 1315 |
|
|
type, &secondary_out_icode, NULL);
|
| 1316 |
|
|
|
| 1317 |
|
|
/* We found no existing reload suitable for re-use.
|
| 1318 |
|
|
So add an additional reload. */
|
| 1319 |
|
|
|
| 1320 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 1321 |
|
|
/* If a memory location is needed for the copy, make one. */
|
| 1322 |
|
|
if (in != 0
|
| 1323 |
|
|
&& (REG_P (in)
|
| 1324 |
|
|
|| (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
|
| 1325 |
|
|
&& reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
|
| 1326 |
|
|
&& SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
|
| 1327 |
|
|
rclass, inmode))
|
| 1328 |
|
|
get_secondary_mem (in, inmode, opnum, type);
|
| 1329 |
|
|
#endif
|
| 1330 |
|
|
|
| 1331 |
|
|
i = n_reloads;
|
| 1332 |
|
|
rld[i].in = in;
|
| 1333 |
|
|
rld[i].out = out;
|
| 1334 |
|
|
rld[i].rclass = rclass;
|
| 1335 |
|
|
rld[i].inmode = inmode;
|
| 1336 |
|
|
rld[i].outmode = outmode;
|
| 1337 |
|
|
rld[i].reg_rtx = 0;
|
| 1338 |
|
|
rld[i].optional = optional;
|
| 1339 |
|
|
rld[i].inc = 0;
|
| 1340 |
|
|
rld[i].nocombine = 0;
|
| 1341 |
|
|
rld[i].in_reg = inloc ? *inloc : 0;
|
| 1342 |
|
|
rld[i].out_reg = outloc ? *outloc : 0;
|
| 1343 |
|
|
rld[i].opnum = opnum;
|
| 1344 |
|
|
rld[i].when_needed = type;
|
| 1345 |
|
|
rld[i].secondary_in_reload = secondary_in_reload;
|
| 1346 |
|
|
rld[i].secondary_out_reload = secondary_out_reload;
|
| 1347 |
|
|
rld[i].secondary_in_icode = secondary_in_icode;
|
| 1348 |
|
|
rld[i].secondary_out_icode = secondary_out_icode;
|
| 1349 |
|
|
rld[i].secondary_p = 0;
|
| 1350 |
|
|
|
| 1351 |
|
|
n_reloads++;
|
| 1352 |
|
|
|
| 1353 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 1354 |
|
|
if (out != 0
|
| 1355 |
|
|
&& (REG_P (out)
|
| 1356 |
|
|
|| (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
|
| 1357 |
|
|
&& reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
|
| 1358 |
|
|
&& SECONDARY_MEMORY_NEEDED (rclass,
|
| 1359 |
|
|
REGNO_REG_CLASS (reg_or_subregno (out)),
|
| 1360 |
|
|
outmode))
|
| 1361 |
|
|
get_secondary_mem (out, outmode, opnum, type);
|
| 1362 |
|
|
#endif
|
| 1363 |
|
|
}
|
| 1364 |
|
|
else
|
| 1365 |
|
|
{
|
| 1366 |
|
|
/* We are reusing an existing reload,
|
| 1367 |
|
|
but we may have additional information for it.
|
| 1368 |
|
|
For example, we may now have both IN and OUT
|
| 1369 |
|
|
while the old one may have just one of them. */
|
| 1370 |
|
|
|
| 1371 |
|
|
/* The modes can be different. If they are, we want to reload in
|
| 1372 |
|
|
the larger mode, so that the value is valid for both modes. */
|
| 1373 |
|
|
if (inmode != VOIDmode
|
| 1374 |
|
|
&& GET_MODE_SIZE (inmode) > GET_MODE_SIZE (rld[i].inmode))
|
| 1375 |
|
|
rld[i].inmode = inmode;
|
| 1376 |
|
|
if (outmode != VOIDmode
|
| 1377 |
|
|
&& GET_MODE_SIZE (outmode) > GET_MODE_SIZE (rld[i].outmode))
|
| 1378 |
|
|
rld[i].outmode = outmode;
|
| 1379 |
|
|
if (in != 0)
|
| 1380 |
|
|
{
|
| 1381 |
|
|
rtx in_reg = inloc ? *inloc : 0;
|
| 1382 |
|
|
/* If we merge reloads for two distinct rtl expressions that
|
| 1383 |
|
|
are identical in content, there might be duplicate address
|
| 1384 |
|
|
reloads. Remove the extra set now, so that if we later find
|
| 1385 |
|
|
that we can inherit this reload, we can get rid of the
|
| 1386 |
|
|
address reloads altogether.
|
| 1387 |
|
|
|
| 1388 |
|
|
Do not do this if both reloads are optional since the result
|
| 1389 |
|
|
would be an optional reload which could potentially leave
|
| 1390 |
|
|
unresolved address replacements.
|
| 1391 |
|
|
|
| 1392 |
|
|
It is not sufficient to call transfer_replacements since
|
| 1393 |
|
|
choose_reload_regs will remove the replacements for address
|
| 1394 |
|
|
reloads of inherited reloads which results in the same
|
| 1395 |
|
|
problem. */
|
| 1396 |
|
|
if (rld[i].in != in && rtx_equal_p (in, rld[i].in)
|
| 1397 |
|
|
&& ! (rld[i].optional && optional))
|
| 1398 |
|
|
{
|
| 1399 |
|
|
/* We must keep the address reload with the lower operand
|
| 1400 |
|
|
number alive. */
|
| 1401 |
|
|
if (opnum > rld[i].opnum)
|
| 1402 |
|
|
{
|
| 1403 |
|
|
remove_address_replacements (in);
|
| 1404 |
|
|
in = rld[i].in;
|
| 1405 |
|
|
in_reg = rld[i].in_reg;
|
| 1406 |
|
|
}
|
| 1407 |
|
|
else
|
| 1408 |
|
|
remove_address_replacements (rld[i].in);
|
| 1409 |
|
|
}
|
| 1410 |
|
|
/* When emitting reloads we don't necessarily look at the in-
|
| 1411 |
|
|
and outmode, but also directly at the operands (in and out).
|
| 1412 |
|
|
So we can't simply overwrite them with whatever we have found
|
| 1413 |
|
|
for this (to-be-merged) reload, we have to "merge" that too.
|
| 1414 |
|
|
Reusing another reload already verified that we deal with the
|
| 1415 |
|
|
same operands, just possibly in different modes. So we
|
| 1416 |
|
|
overwrite the operands only when the new mode is larger.
|
| 1417 |
|
|
See also PR33613. */
|
| 1418 |
|
|
if (!rld[i].in
|
| 1419 |
|
|
|| GET_MODE_SIZE (GET_MODE (in))
|
| 1420 |
|
|
> GET_MODE_SIZE (GET_MODE (rld[i].in)))
|
| 1421 |
|
|
rld[i].in = in;
|
| 1422 |
|
|
if (!rld[i].in_reg
|
| 1423 |
|
|
|| (in_reg
|
| 1424 |
|
|
&& GET_MODE_SIZE (GET_MODE (in_reg))
|
| 1425 |
|
|
> GET_MODE_SIZE (GET_MODE (rld[i].in_reg))))
|
| 1426 |
|
|
rld[i].in_reg = in_reg;
|
| 1427 |
|
|
}
|
| 1428 |
|
|
if (out != 0)
|
| 1429 |
|
|
{
|
| 1430 |
|
|
if (!rld[i].out
|
| 1431 |
|
|
|| (out
|
| 1432 |
|
|
&& GET_MODE_SIZE (GET_MODE (out))
|
| 1433 |
|
|
> GET_MODE_SIZE (GET_MODE (rld[i].out))))
|
| 1434 |
|
|
rld[i].out = out;
|
| 1435 |
|
|
if (outloc
|
| 1436 |
|
|
&& (!rld[i].out_reg
|
| 1437 |
|
|
|| GET_MODE_SIZE (GET_MODE (*outloc))
|
| 1438 |
|
|
> GET_MODE_SIZE (GET_MODE (rld[i].out_reg))))
|
| 1439 |
|
|
rld[i].out_reg = *outloc;
|
| 1440 |
|
|
}
|
| 1441 |
|
|
if (reg_class_subset_p (rclass, rld[i].rclass))
|
| 1442 |
|
|
rld[i].rclass = rclass;
|
| 1443 |
|
|
rld[i].optional &= optional;
|
| 1444 |
|
|
if (MERGE_TO_OTHER (type, rld[i].when_needed,
|
| 1445 |
|
|
opnum, rld[i].opnum))
|
| 1446 |
|
|
rld[i].when_needed = RELOAD_OTHER;
|
| 1447 |
|
|
rld[i].opnum = MIN (rld[i].opnum, opnum);
|
| 1448 |
|
|
}
|
| 1449 |
|
|
|
| 1450 |
|
|
/* If the ostensible rtx being reloaded differs from the rtx found
|
| 1451 |
|
|
in the location to substitute, this reload is not safe to combine
|
| 1452 |
|
|
because we cannot reliably tell whether it appears in the insn. */
|
| 1453 |
|
|
|
| 1454 |
|
|
if (in != 0 && in != *inloc)
|
| 1455 |
|
|
rld[i].nocombine = 1;
|
| 1456 |
|
|
|
| 1457 |
|
|
#if 0
|
| 1458 |
|
|
/* This was replaced by changes in find_reloads_address_1 and the new
|
| 1459 |
|
|
function inc_for_reload, which go with a new meaning of reload_inc. */
|
| 1460 |
|
|
|
| 1461 |
|
|
/* If this is an IN/OUT reload in an insn that sets the CC,
|
| 1462 |
|
|
it must be for an autoincrement. It doesn't work to store
|
| 1463 |
|
|
the incremented value after the insn because that would clobber the CC.
|
| 1464 |
|
|
So we must do the increment of the value reloaded from,
|
| 1465 |
|
|
increment it, store it back, then decrement again. */
|
| 1466 |
|
|
if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
|
| 1467 |
|
|
{
|
| 1468 |
|
|
out = 0;
|
| 1469 |
|
|
rld[i].out = 0;
|
| 1470 |
|
|
rld[i].inc = find_inc_amount (PATTERN (this_insn), in);
|
| 1471 |
|
|
/* If we did not find a nonzero amount-to-increment-by,
|
| 1472 |
|
|
that contradicts the belief that IN is being incremented
|
| 1473 |
|
|
in an address in this insn. */
|
| 1474 |
|
|
gcc_assert (rld[i].inc != 0);
|
| 1475 |
|
|
}
|
| 1476 |
|
|
#endif
|
| 1477 |
|
|
|
| 1478 |
|
|
/* If we will replace IN and OUT with the reload-reg,
|
| 1479 |
|
|
record where they are located so that substitution need
|
| 1480 |
|
|
not do a tree walk. */
|
| 1481 |
|
|
|
| 1482 |
|
|
if (replace_reloads)
|
| 1483 |
|
|
{
|
| 1484 |
|
|
if (inloc != 0)
|
| 1485 |
|
|
{
|
| 1486 |
|
|
struct replacement *r = &replacements[n_replacements++];
|
| 1487 |
|
|
r->what = i;
|
| 1488 |
|
|
r->subreg_loc = in_subreg_loc;
|
| 1489 |
|
|
r->where = inloc;
|
| 1490 |
|
|
r->mode = inmode;
|
| 1491 |
|
|
}
|
| 1492 |
|
|
if (outloc != 0 && outloc != inloc)
|
| 1493 |
|
|
{
|
| 1494 |
|
|
struct replacement *r = &replacements[n_replacements++];
|
| 1495 |
|
|
r->what = i;
|
| 1496 |
|
|
r->where = outloc;
|
| 1497 |
|
|
r->subreg_loc = out_subreg_loc;
|
| 1498 |
|
|
r->mode = outmode;
|
| 1499 |
|
|
}
|
| 1500 |
|
|
}
|
| 1501 |
|
|
|
| 1502 |
|
|
/* If this reload is just being introduced and it has both
|
| 1503 |
|
|
an incoming quantity and an outgoing quantity that are
|
| 1504 |
|
|
supposed to be made to match, see if either one of the two
|
| 1505 |
|
|
can serve as the place to reload into.
|
| 1506 |
|
|
|
| 1507 |
|
|
If one of them is acceptable, set rld[i].reg_rtx
|
| 1508 |
|
|
to that one. */
|
| 1509 |
|
|
|
| 1510 |
|
|
if (in != 0 && out != 0 && in != out && rld[i].reg_rtx == 0)
|
| 1511 |
|
|
{
|
| 1512 |
|
|
rld[i].reg_rtx = find_dummy_reload (in, out, inloc, outloc,
|
| 1513 |
|
|
inmode, outmode,
|
| 1514 |
|
|
rld[i].rclass, i,
|
| 1515 |
|
|
earlyclobber_operand_p (out));
|
| 1516 |
|
|
|
| 1517 |
|
|
/* If the outgoing register already contains the same value
|
| 1518 |
|
|
as the incoming one, we can dispense with loading it.
|
| 1519 |
|
|
The easiest way to tell the caller that is to give a phony
|
| 1520 |
|
|
value for the incoming operand (same as outgoing one). */
|
| 1521 |
|
|
if (rld[i].reg_rtx == out
|
| 1522 |
|
|
&& (REG_P (in) || CONSTANT_P (in))
|
| 1523 |
|
|
&& 0 != find_equiv_reg (in, this_insn, NO_REGS, REGNO (out),
|
| 1524 |
|
|
static_reload_reg_p, i, inmode))
|
| 1525 |
|
|
rld[i].in = out;
|
| 1526 |
|
|
}
|
| 1527 |
|
|
|
| 1528 |
|
|
/* If this is an input reload and the operand contains a register that
|
| 1529 |
|
|
dies in this insn and is used nowhere else, see if it is the right class
|
| 1530 |
|
|
to be used for this reload. Use it if so. (This occurs most commonly
|
| 1531 |
|
|
in the case of paradoxical SUBREGs and in-out reloads). We cannot do
|
| 1532 |
|
|
this if it is also an output reload that mentions the register unless
|
| 1533 |
|
|
the output is a SUBREG that clobbers an entire register.
|
| 1534 |
|
|
|
| 1535 |
|
|
Note that the operand might be one of the spill regs, if it is a
|
| 1536 |
|
|
pseudo reg and we are in a block where spilling has not taken place.
|
| 1537 |
|
|
But if there is no spilling in this block, that is OK.
|
| 1538 |
|
|
An explicitly used hard reg cannot be a spill reg. */
|
| 1539 |
|
|
|
| 1540 |
|
|
if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known)
|
| 1541 |
|
|
{
|
| 1542 |
|
|
rtx note;
|
| 1543 |
|
|
int regno;
|
| 1544 |
|
|
enum machine_mode rel_mode = inmode;
|
| 1545 |
|
|
|
| 1546 |
|
|
if (out && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (inmode))
|
| 1547 |
|
|
rel_mode = outmode;
|
| 1548 |
|
|
|
| 1549 |
|
|
for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
|
| 1550 |
|
|
if (REG_NOTE_KIND (note) == REG_DEAD
|
| 1551 |
|
|
&& REG_P (XEXP (note, 0))
|
| 1552 |
|
|
&& (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
|
| 1553 |
|
|
&& reg_mentioned_p (XEXP (note, 0), in)
|
| 1554 |
|
|
/* Check that a former pseudo is valid; see find_dummy_reload. */
|
| 1555 |
|
|
&& (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
|
| 1556 |
|
|
|| (! bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR),
|
| 1557 |
|
|
ORIGINAL_REGNO (XEXP (note, 0)))
|
| 1558 |
|
|
&& hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] == 1))
|
| 1559 |
|
|
&& ! refers_to_regno_for_reload_p (regno,
|
| 1560 |
|
|
end_hard_regno (rel_mode,
|
| 1561 |
|
|
regno),
|
| 1562 |
|
|
PATTERN (this_insn), inloc)
|
| 1563 |
|
|
/* If this is also an output reload, IN cannot be used as
|
| 1564 |
|
|
the reload register if it is set in this insn unless IN
|
| 1565 |
|
|
is also OUT. */
|
| 1566 |
|
|
&& (out == 0 || in == out
|
| 1567 |
|
|
|| ! hard_reg_set_here_p (regno,
|
| 1568 |
|
|
end_hard_regno (rel_mode, regno),
|
| 1569 |
|
|
PATTERN (this_insn)))
|
| 1570 |
|
|
/* ??? Why is this code so different from the previous?
|
| 1571 |
|
|
Is there any simple coherent way to describe the two together?
|
| 1572 |
|
|
What's going on here. */
|
| 1573 |
|
|
&& (in != out
|
| 1574 |
|
|
|| (GET_CODE (in) == SUBREG
|
| 1575 |
|
|
&& (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
|
| 1576 |
|
|
/ UNITS_PER_WORD)
|
| 1577 |
|
|
== ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
|
| 1578 |
|
|
+ (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
|
| 1579 |
|
|
/* Make sure the operand fits in the reg that dies. */
|
| 1580 |
|
|
&& (GET_MODE_SIZE (rel_mode)
|
| 1581 |
|
|
<= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))))
|
| 1582 |
|
|
&& HARD_REGNO_MODE_OK (regno, inmode)
|
| 1583 |
|
|
&& HARD_REGNO_MODE_OK (regno, outmode))
|
| 1584 |
|
|
{
|
| 1585 |
|
|
unsigned int offs;
|
| 1586 |
|
|
unsigned int nregs = MAX (hard_regno_nregs[regno][inmode],
|
| 1587 |
|
|
hard_regno_nregs[regno][outmode]);
|
| 1588 |
|
|
|
| 1589 |
|
|
for (offs = 0; offs < nregs; offs++)
|
| 1590 |
|
|
if (fixed_regs[regno + offs]
|
| 1591 |
|
|
|| ! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
|
| 1592 |
|
|
regno + offs))
|
| 1593 |
|
|
break;
|
| 1594 |
|
|
|
| 1595 |
|
|
if (offs == nregs
|
| 1596 |
|
|
&& (! (refers_to_regno_for_reload_p
|
| 1597 |
|
|
(regno, end_hard_regno (inmode, regno), in, (rtx *) 0))
|
| 1598 |
|
|
|| can_reload_into (in, regno, inmode)))
|
| 1599 |
|
|
{
|
| 1600 |
|
|
rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno);
|
| 1601 |
|
|
break;
|
| 1602 |
|
|
}
|
| 1603 |
|
|
}
|
| 1604 |
|
|
}
|
| 1605 |
|
|
|
| 1606 |
|
|
if (out)
|
| 1607 |
|
|
output_reloadnum = i;
|
| 1608 |
|
|
|
| 1609 |
|
|
return i;
|
| 1610 |
|
|
}
|
| 1611 |
|
|
|
| 1612 |
|
|
/* Record an additional place we must replace a value
|
| 1613 |
|
|
for which we have already recorded a reload.
|
| 1614 |
|
|
RELOADNUM is the value returned by push_reload
|
| 1615 |
|
|
when the reload was recorded.
|
| 1616 |
|
|
This is used in insn patterns that use match_dup. */
|
| 1617 |
|
|
|
| 1618 |
|
|
static void
|
| 1619 |
|
|
push_replacement (rtx *loc, int reloadnum, enum machine_mode mode)
|
| 1620 |
|
|
{
|
| 1621 |
|
|
if (replace_reloads)
|
| 1622 |
|
|
{
|
| 1623 |
|
|
struct replacement *r = &replacements[n_replacements++];
|
| 1624 |
|
|
r->what = reloadnum;
|
| 1625 |
|
|
r->where = loc;
|
| 1626 |
|
|
r->subreg_loc = 0;
|
| 1627 |
|
|
r->mode = mode;
|
| 1628 |
|
|
}
|
| 1629 |
|
|
}
|
| 1630 |
|
|
|
| 1631 |
|
|
/* Duplicate any replacement we have recorded to apply at
|
| 1632 |
|
|
location ORIG_LOC to also be performed at DUP_LOC.
|
| 1633 |
|
|
This is used in insn patterns that use match_dup. */
|
| 1634 |
|
|
|
| 1635 |
|
|
static void
|
| 1636 |
|
|
dup_replacements (rtx *dup_loc, rtx *orig_loc)
|
| 1637 |
|
|
{
|
| 1638 |
|
|
int i, n = n_replacements;
|
| 1639 |
|
|
|
| 1640 |
|
|
for (i = 0; i < n; i++)
|
| 1641 |
|
|
{
|
| 1642 |
|
|
struct replacement *r = &replacements[i];
|
| 1643 |
|
|
if (r->where == orig_loc)
|
| 1644 |
|
|
push_replacement (dup_loc, r->what, r->mode);
|
| 1645 |
|
|
}
|
| 1646 |
|
|
}
|
| 1647 |
|
|
|
| 1648 |
|
|
/* Transfer all replacements that used to be in reload FROM to be in
|
| 1649 |
|
|
reload TO. */
|
| 1650 |
|
|
|
| 1651 |
|
|
void
|
| 1652 |
|
|
transfer_replacements (int to, int from)
|
| 1653 |
|
|
{
|
| 1654 |
|
|
int i;
|
| 1655 |
|
|
|
| 1656 |
|
|
for (i = 0; i < n_replacements; i++)
|
| 1657 |
|
|
if (replacements[i].what == from)
|
| 1658 |
|
|
replacements[i].what = to;
|
| 1659 |
|
|
}
|
| 1660 |
|
|
|
| 1661 |
|
|
/* IN_RTX is the value loaded by a reload that we now decided to inherit,
|
| 1662 |
|
|
or a subpart of it. If we have any replacements registered for IN_RTX,
|
| 1663 |
|
|
cancel the reloads that were supposed to load them.
|
| 1664 |
|
|
Return nonzero if we canceled any reloads. */
|
| 1665 |
|
|
int
|
| 1666 |
|
|
remove_address_replacements (rtx in_rtx)
|
| 1667 |
|
|
{
|
| 1668 |
|
|
int i, j;
|
| 1669 |
|
|
char reload_flags[MAX_RELOADS];
|
| 1670 |
|
|
int something_changed = 0;
|
| 1671 |
|
|
|
| 1672 |
|
|
memset (reload_flags, 0, sizeof reload_flags);
|
| 1673 |
|
|
for (i = 0, j = 0; i < n_replacements; i++)
|
| 1674 |
|
|
{
|
| 1675 |
|
|
if (loc_mentioned_in_p (replacements[i].where, in_rtx))
|
| 1676 |
|
|
reload_flags[replacements[i].what] |= 1;
|
| 1677 |
|
|
else
|
| 1678 |
|
|
{
|
| 1679 |
|
|
replacements[j++] = replacements[i];
|
| 1680 |
|
|
reload_flags[replacements[i].what] |= 2;
|
| 1681 |
|
|
}
|
| 1682 |
|
|
}
|
| 1683 |
|
|
/* Note that the following store must be done before the recursive calls. */
|
| 1684 |
|
|
n_replacements = j;
|
| 1685 |
|
|
|
| 1686 |
|
|
for (i = n_reloads - 1; i >= 0; i--)
|
| 1687 |
|
|
{
|
| 1688 |
|
|
if (reload_flags[i] == 1)
|
| 1689 |
|
|
{
|
| 1690 |
|
|
deallocate_reload_reg (i);
|
| 1691 |
|
|
remove_address_replacements (rld[i].in);
|
| 1692 |
|
|
rld[i].in = 0;
|
| 1693 |
|
|
something_changed = 1;
|
| 1694 |
|
|
}
|
| 1695 |
|
|
}
|
| 1696 |
|
|
return something_changed;
|
| 1697 |
|
|
}
|
| 1698 |
|
|
|
| 1699 |
|
|
/* If there is only one output reload, and it is not for an earlyclobber
|
| 1700 |
|
|
operand, try to combine it with a (logically unrelated) input reload
|
| 1701 |
|
|
to reduce the number of reload registers needed.
|
| 1702 |
|
|
|
| 1703 |
|
|
This is safe if the input reload does not appear in
|
| 1704 |
|
|
the value being output-reloaded, because this implies
|
| 1705 |
|
|
it is not needed any more once the original insn completes.
|
| 1706 |
|
|
|
| 1707 |
|
|
If that doesn't work, see we can use any of the registers that
|
| 1708 |
|
|
die in this insn as a reload register. We can if it is of the right
|
| 1709 |
|
|
class and does not appear in the value being output-reloaded. */
|
| 1710 |
|
|
|
| 1711 |
|
|
static void
|
| 1712 |
|
|
combine_reloads (void)
|
| 1713 |
|
|
{
|
| 1714 |
|
|
int i, regno;
|
| 1715 |
|
|
int output_reload = -1;
|
| 1716 |
|
|
int secondary_out = -1;
|
| 1717 |
|
|
rtx note;
|
| 1718 |
|
|
|
| 1719 |
|
|
/* Find the output reload; return unless there is exactly one
|
| 1720 |
|
|
and that one is mandatory. */
|
| 1721 |
|
|
|
| 1722 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 1723 |
|
|
if (rld[i].out != 0)
|
| 1724 |
|
|
{
|
| 1725 |
|
|
if (output_reload >= 0)
|
| 1726 |
|
|
return;
|
| 1727 |
|
|
output_reload = i;
|
| 1728 |
|
|
}
|
| 1729 |
|
|
|
| 1730 |
|
|
if (output_reload < 0 || rld[output_reload].optional)
|
| 1731 |
|
|
return;
|
| 1732 |
|
|
|
| 1733 |
|
|
/* An input-output reload isn't combinable. */
|
| 1734 |
|
|
|
| 1735 |
|
|
if (rld[output_reload].in != 0)
|
| 1736 |
|
|
return;
|
| 1737 |
|
|
|
| 1738 |
|
|
/* If this reload is for an earlyclobber operand, we can't do anything. */
|
| 1739 |
|
|
if (earlyclobber_operand_p (rld[output_reload].out))
|
| 1740 |
|
|
return;
|
| 1741 |
|
|
|
| 1742 |
|
|
/* If there is a reload for part of the address of this operand, we would
|
| 1743 |
|
|
need to change it to RELOAD_FOR_OTHER_ADDRESS. But that would extend
|
| 1744 |
|
|
its life to the point where doing this combine would not lower the
|
| 1745 |
|
|
number of spill registers needed. */
|
| 1746 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 1747 |
|
|
if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
|
| 1748 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 1749 |
|
|
&& rld[i].opnum == rld[output_reload].opnum)
|
| 1750 |
|
|
return;
|
| 1751 |
|
|
|
| 1752 |
|
|
/* Check each input reload; can we combine it? */
|
| 1753 |
|
|
|
| 1754 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 1755 |
|
|
if (rld[i].in && ! rld[i].optional && ! rld[i].nocombine
|
| 1756 |
|
|
/* Life span of this reload must not extend past main insn. */
|
| 1757 |
|
|
&& rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
|
| 1758 |
|
|
&& rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS
|
| 1759 |
|
|
&& rld[i].when_needed != RELOAD_OTHER
|
| 1760 |
|
|
&& (CLASS_MAX_NREGS (rld[i].rclass, rld[i].inmode)
|
| 1761 |
|
|
== CLASS_MAX_NREGS (rld[output_reload].rclass,
|
| 1762 |
|
|
rld[output_reload].outmode))
|
| 1763 |
|
|
&& rld[i].inc == 0
|
| 1764 |
|
|
&& rld[i].reg_rtx == 0
|
| 1765 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 1766 |
|
|
/* Don't combine two reloads with different secondary
|
| 1767 |
|
|
memory locations. */
|
| 1768 |
|
|
&& (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum] == 0
|
| 1769 |
|
|
|| secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] == 0
|
| 1770 |
|
|
|| rtx_equal_p (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum],
|
| 1771 |
|
|
secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum]))
|
| 1772 |
|
|
#endif
|
| 1773 |
|
|
&& (SMALL_REGISTER_CLASSES
|
| 1774 |
|
|
? (rld[i].rclass == rld[output_reload].rclass)
|
| 1775 |
|
|
: (reg_class_subset_p (rld[i].rclass,
|
| 1776 |
|
|
rld[output_reload].rclass)
|
| 1777 |
|
|
|| reg_class_subset_p (rld[output_reload].rclass,
|
| 1778 |
|
|
rld[i].rclass)))
|
| 1779 |
|
|
&& (MATCHES (rld[i].in, rld[output_reload].out)
|
| 1780 |
|
|
/* Args reversed because the first arg seems to be
|
| 1781 |
|
|
the one that we imagine being modified
|
| 1782 |
|
|
while the second is the one that might be affected. */
|
| 1783 |
|
|
|| (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out,
|
| 1784 |
|
|
rld[i].in)
|
| 1785 |
|
|
/* However, if the input is a register that appears inside
|
| 1786 |
|
|
the output, then we also can't share.
|
| 1787 |
|
|
Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
|
| 1788 |
|
|
If the same reload reg is used for both reg 69 and the
|
| 1789 |
|
|
result to be stored in memory, then that result
|
| 1790 |
|
|
will clobber the address of the memory ref. */
|
| 1791 |
|
|
&& ! (REG_P (rld[i].in)
|
| 1792 |
|
|
&& reg_overlap_mentioned_for_reload_p (rld[i].in,
|
| 1793 |
|
|
rld[output_reload].out))))
|
| 1794 |
|
|
&& ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode,
|
| 1795 |
|
|
rld[i].when_needed != RELOAD_FOR_INPUT)
|
| 1796 |
|
|
&& (reg_class_size[(int) rld[i].rclass]
|
| 1797 |
|
|
|| SMALL_REGISTER_CLASSES)
|
| 1798 |
|
|
/* We will allow making things slightly worse by combining an
|
| 1799 |
|
|
input and an output, but no worse than that. */
|
| 1800 |
|
|
&& (rld[i].when_needed == RELOAD_FOR_INPUT
|
| 1801 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTPUT))
|
| 1802 |
|
|
{
|
| 1803 |
|
|
int j;
|
| 1804 |
|
|
|
| 1805 |
|
|
/* We have found a reload to combine with! */
|
| 1806 |
|
|
rld[i].out = rld[output_reload].out;
|
| 1807 |
|
|
rld[i].out_reg = rld[output_reload].out_reg;
|
| 1808 |
|
|
rld[i].outmode = rld[output_reload].outmode;
|
| 1809 |
|
|
/* Mark the old output reload as inoperative. */
|
| 1810 |
|
|
rld[output_reload].out = 0;
|
| 1811 |
|
|
/* The combined reload is needed for the entire insn. */
|
| 1812 |
|
|
rld[i].when_needed = RELOAD_OTHER;
|
| 1813 |
|
|
/* If the output reload had a secondary reload, copy it. */
|
| 1814 |
|
|
if (rld[output_reload].secondary_out_reload != -1)
|
| 1815 |
|
|
{
|
| 1816 |
|
|
rld[i].secondary_out_reload
|
| 1817 |
|
|
= rld[output_reload].secondary_out_reload;
|
| 1818 |
|
|
rld[i].secondary_out_icode
|
| 1819 |
|
|
= rld[output_reload].secondary_out_icode;
|
| 1820 |
|
|
}
|
| 1821 |
|
|
|
| 1822 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 1823 |
|
|
/* Copy any secondary MEM. */
|
| 1824 |
|
|
if (secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum] != 0)
|
| 1825 |
|
|
secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[i].opnum]
|
| 1826 |
|
|
= secondary_memlocs_elim[(int) rld[output_reload].outmode][rld[output_reload].opnum];
|
| 1827 |
|
|
#endif
|
| 1828 |
|
|
/* If required, minimize the register class. */
|
| 1829 |
|
|
if (reg_class_subset_p (rld[output_reload].rclass,
|
| 1830 |
|
|
rld[i].rclass))
|
| 1831 |
|
|
rld[i].rclass = rld[output_reload].rclass;
|
| 1832 |
|
|
|
| 1833 |
|
|
/* Transfer all replacements from the old reload to the combined. */
|
| 1834 |
|
|
for (j = 0; j < n_replacements; j++)
|
| 1835 |
|
|
if (replacements[j].what == output_reload)
|
| 1836 |
|
|
replacements[j].what = i;
|
| 1837 |
|
|
|
| 1838 |
|
|
return;
|
| 1839 |
|
|
}
|
| 1840 |
|
|
|
| 1841 |
|
|
/* If this insn has only one operand that is modified or written (assumed
|
| 1842 |
|
|
to be the first), it must be the one corresponding to this reload. It
|
| 1843 |
|
|
is safe to use anything that dies in this insn for that output provided
|
| 1844 |
|
|
that it does not occur in the output (we already know it isn't an
|
| 1845 |
|
|
earlyclobber. If this is an asm insn, give up. */
|
| 1846 |
|
|
|
| 1847 |
|
|
if (INSN_CODE (this_insn) == -1)
|
| 1848 |
|
|
return;
|
| 1849 |
|
|
|
| 1850 |
|
|
for (i = 1; i < insn_data[INSN_CODE (this_insn)].n_operands; i++)
|
| 1851 |
|
|
if (insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '='
|
| 1852 |
|
|
|| insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+')
|
| 1853 |
|
|
return;
|
| 1854 |
|
|
|
| 1855 |
|
|
/* See if some hard register that dies in this insn and is not used in
|
| 1856 |
|
|
the output is the right class. Only works if the register we pick
|
| 1857 |
|
|
up can fully hold our output reload. */
|
| 1858 |
|
|
for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
|
| 1859 |
|
|
if (REG_NOTE_KIND (note) == REG_DEAD
|
| 1860 |
|
|
&& REG_P (XEXP (note, 0))
|
| 1861 |
|
|
&& !reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
|
| 1862 |
|
|
rld[output_reload].out)
|
| 1863 |
|
|
&& (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
|
| 1864 |
|
|
&& HARD_REGNO_MODE_OK (regno, rld[output_reload].outmode)
|
| 1865 |
|
|
&& TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].rclass],
|
| 1866 |
|
|
regno)
|
| 1867 |
|
|
&& (hard_regno_nregs[regno][rld[output_reload].outmode]
|
| 1868 |
|
|
<= hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))])
|
| 1869 |
|
|
/* Ensure that a secondary or tertiary reload for this output
|
| 1870 |
|
|
won't want this register. */
|
| 1871 |
|
|
&& ((secondary_out = rld[output_reload].secondary_out_reload) == -1
|
| 1872 |
|
|
|| (!(TEST_HARD_REG_BIT
|
| 1873 |
|
|
(reg_class_contents[(int) rld[secondary_out].rclass], regno))
|
| 1874 |
|
|
&& ((secondary_out = rld[secondary_out].secondary_out_reload) == -1
|
| 1875 |
|
|
|| !(TEST_HARD_REG_BIT
|
| 1876 |
|
|
(reg_class_contents[(int) rld[secondary_out].rclass],
|
| 1877 |
|
|
regno)))))
|
| 1878 |
|
|
&& !fixed_regs[regno]
|
| 1879 |
|
|
/* Check that a former pseudo is valid; see find_dummy_reload. */
|
| 1880 |
|
|
&& (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
|
| 1881 |
|
|
|| (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR),
|
| 1882 |
|
|
ORIGINAL_REGNO (XEXP (note, 0)))
|
| 1883 |
|
|
&& hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] == 1)))
|
| 1884 |
|
|
{
|
| 1885 |
|
|
rld[output_reload].reg_rtx
|
| 1886 |
|
|
= gen_rtx_REG (rld[output_reload].outmode, regno);
|
| 1887 |
|
|
return;
|
| 1888 |
|
|
}
|
| 1889 |
|
|
}
|
| 1890 |
|
|
|
| 1891 |
|
|
/* Try to find a reload register for an in-out reload (expressions IN and OUT).
|
| 1892 |
|
|
See if one of IN and OUT is a register that may be used;
|
| 1893 |
|
|
this is desirable since a spill-register won't be needed.
|
| 1894 |
|
|
If so, return the register rtx that proves acceptable.
|
| 1895 |
|
|
|
| 1896 |
|
|
INLOC and OUTLOC are locations where IN and OUT appear in the insn.
|
| 1897 |
|
|
RCLASS is the register class required for the reload.
|
| 1898 |
|
|
|
| 1899 |
|
|
If FOR_REAL is >= 0, it is the number of the reload,
|
| 1900 |
|
|
and in some cases when it can be discovered that OUT doesn't need
|
| 1901 |
|
|
to be computed, clear out rld[FOR_REAL].out.
|
| 1902 |
|
|
|
| 1903 |
|
|
If FOR_REAL is -1, this should not be done, because this call
|
| 1904 |
|
|
is just to see if a register can be found, not to find and install it.
|
| 1905 |
|
|
|
| 1906 |
|
|
EARLYCLOBBER is nonzero if OUT is an earlyclobber operand. This
|
| 1907 |
|
|
puts an additional constraint on being able to use IN for OUT since
|
| 1908 |
|
|
IN must not appear elsewhere in the insn (it is assumed that IN itself
|
| 1909 |
|
|
is safe from the earlyclobber). */
|
| 1910 |
|
|
|
| 1911 |
|
|
static rtx
|
| 1912 |
|
|
find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
|
| 1913 |
|
|
enum machine_mode inmode, enum machine_mode outmode,
|
| 1914 |
|
|
enum reg_class rclass, int for_real, int earlyclobber)
|
| 1915 |
|
|
{
|
| 1916 |
|
|
rtx in = real_in;
|
| 1917 |
|
|
rtx out = real_out;
|
| 1918 |
|
|
int in_offset = 0;
|
| 1919 |
|
|
int out_offset = 0;
|
| 1920 |
|
|
rtx value = 0;
|
| 1921 |
|
|
|
| 1922 |
|
|
/* If operands exceed a word, we can't use either of them
|
| 1923 |
|
|
unless they have the same size. */
|
| 1924 |
|
|
if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode)
|
| 1925 |
|
|
&& (GET_MODE_SIZE (outmode) > UNITS_PER_WORD
|
| 1926 |
|
|
|| GET_MODE_SIZE (inmode) > UNITS_PER_WORD))
|
| 1927 |
|
|
return 0;
|
| 1928 |
|
|
|
| 1929 |
|
|
/* Note that {in,out}_offset are needed only when 'in' or 'out'
|
| 1930 |
|
|
respectively refers to a hard register. */
|
| 1931 |
|
|
|
| 1932 |
|
|
/* Find the inside of any subregs. */
|
| 1933 |
|
|
while (GET_CODE (out) == SUBREG)
|
| 1934 |
|
|
{
|
| 1935 |
|
|
if (REG_P (SUBREG_REG (out))
|
| 1936 |
|
|
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
|
| 1937 |
|
|
out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)),
|
| 1938 |
|
|
GET_MODE (SUBREG_REG (out)),
|
| 1939 |
|
|
SUBREG_BYTE (out),
|
| 1940 |
|
|
GET_MODE (out));
|
| 1941 |
|
|
out = SUBREG_REG (out);
|
| 1942 |
|
|
}
|
| 1943 |
|
|
while (GET_CODE (in) == SUBREG)
|
| 1944 |
|
|
{
|
| 1945 |
|
|
if (REG_P (SUBREG_REG (in))
|
| 1946 |
|
|
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
|
| 1947 |
|
|
in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)),
|
| 1948 |
|
|
GET_MODE (SUBREG_REG (in)),
|
| 1949 |
|
|
SUBREG_BYTE (in),
|
| 1950 |
|
|
GET_MODE (in));
|
| 1951 |
|
|
in = SUBREG_REG (in);
|
| 1952 |
|
|
}
|
| 1953 |
|
|
|
| 1954 |
|
|
/* Narrow down the reg class, the same way push_reload will;
|
| 1955 |
|
|
otherwise we might find a dummy now, but push_reload won't. */
|
| 1956 |
|
|
{
|
| 1957 |
|
|
enum reg_class preferred_class = PREFERRED_RELOAD_CLASS (in, rclass);
|
| 1958 |
|
|
if (preferred_class != NO_REGS)
|
| 1959 |
|
|
rclass = preferred_class;
|
| 1960 |
|
|
}
|
| 1961 |
|
|
|
| 1962 |
|
|
/* See if OUT will do. */
|
| 1963 |
|
|
if (REG_P (out)
|
| 1964 |
|
|
&& REGNO (out) < FIRST_PSEUDO_REGISTER)
|
| 1965 |
|
|
{
|
| 1966 |
|
|
unsigned int regno = REGNO (out) + out_offset;
|
| 1967 |
|
|
unsigned int nwords = hard_regno_nregs[regno][outmode];
|
| 1968 |
|
|
rtx saved_rtx;
|
| 1969 |
|
|
|
| 1970 |
|
|
/* When we consider whether the insn uses OUT,
|
| 1971 |
|
|
ignore references within IN. They don't prevent us
|
| 1972 |
|
|
from copying IN into OUT, because those refs would
|
| 1973 |
|
|
move into the insn that reloads IN.
|
| 1974 |
|
|
|
| 1975 |
|
|
However, we only ignore IN in its role as this reload.
|
| 1976 |
|
|
If the insn uses IN elsewhere and it contains OUT,
|
| 1977 |
|
|
that counts. We can't be sure it's the "same" operand
|
| 1978 |
|
|
so it might not go through this reload. */
|
| 1979 |
|
|
saved_rtx = *inloc;
|
| 1980 |
|
|
*inloc = const0_rtx;
|
| 1981 |
|
|
|
| 1982 |
|
|
if (regno < FIRST_PSEUDO_REGISTER
|
| 1983 |
|
|
&& HARD_REGNO_MODE_OK (regno, outmode)
|
| 1984 |
|
|
&& ! refers_to_regno_for_reload_p (regno, regno + nwords,
|
| 1985 |
|
|
PATTERN (this_insn), outloc))
|
| 1986 |
|
|
{
|
| 1987 |
|
|
unsigned int i;
|
| 1988 |
|
|
|
| 1989 |
|
|
for (i = 0; i < nwords; i++)
|
| 1990 |
|
|
if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
|
| 1991 |
|
|
regno + i))
|
| 1992 |
|
|
break;
|
| 1993 |
|
|
|
| 1994 |
|
|
if (i == nwords)
|
| 1995 |
|
|
{
|
| 1996 |
|
|
if (REG_P (real_out))
|
| 1997 |
|
|
value = real_out;
|
| 1998 |
|
|
else
|
| 1999 |
|
|
value = gen_rtx_REG (outmode, regno);
|
| 2000 |
|
|
}
|
| 2001 |
|
|
}
|
| 2002 |
|
|
|
| 2003 |
|
|
*inloc = saved_rtx;
|
| 2004 |
|
|
}
|
| 2005 |
|
|
|
| 2006 |
|
|
/* Consider using IN if OUT was not acceptable
|
| 2007 |
|
|
or if OUT dies in this insn (like the quotient in a divmod insn).
|
| 2008 |
|
|
We can't use IN unless it is dies in this insn,
|
| 2009 |
|
|
which means we must know accurately which hard regs are live.
|
| 2010 |
|
|
Also, the result can't go in IN if IN is used within OUT,
|
| 2011 |
|
|
or if OUT is an earlyclobber and IN appears elsewhere in the insn. */
|
| 2012 |
|
|
if (hard_regs_live_known
|
| 2013 |
|
|
&& REG_P (in)
|
| 2014 |
|
|
&& REGNO (in) < FIRST_PSEUDO_REGISTER
|
| 2015 |
|
|
&& (value == 0
|
| 2016 |
|
|
|| find_reg_note (this_insn, REG_UNUSED, real_out))
|
| 2017 |
|
|
&& find_reg_note (this_insn, REG_DEAD, real_in)
|
| 2018 |
|
|
&& !fixed_regs[REGNO (in)]
|
| 2019 |
|
|
&& HARD_REGNO_MODE_OK (REGNO (in),
|
| 2020 |
|
|
/* The only case where out and real_out might
|
| 2021 |
|
|
have different modes is where real_out
|
| 2022 |
|
|
is a subreg, and in that case, out
|
| 2023 |
|
|
has a real mode. */
|
| 2024 |
|
|
(GET_MODE (out) != VOIDmode
|
| 2025 |
|
|
? GET_MODE (out) : outmode))
|
| 2026 |
|
|
&& (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER
|
| 2027 |
|
|
/* However only do this if we can be sure that this input
|
| 2028 |
|
|
operand doesn't correspond with an uninitialized pseudo.
|
| 2029 |
|
|
global can assign some hardreg to it that is the same as
|
| 2030 |
|
|
the one assigned to a different, also live pseudo (as it
|
| 2031 |
|
|
can ignore the conflict). We must never introduce writes
|
| 2032 |
|
|
to such hardregs, as they would clobber the other live
|
| 2033 |
|
|
pseudo. See PR 20973. */
|
| 2034 |
|
|
|| (!bitmap_bit_p (DF_LR_OUT (ENTRY_BLOCK_PTR),
|
| 2035 |
|
|
ORIGINAL_REGNO (in))
|
| 2036 |
|
|
/* Similarly, only do this if we can be sure that the death
|
| 2037 |
|
|
note is still valid. global can assign some hardreg to
|
| 2038 |
|
|
the pseudo referenced in the note and simultaneously a
|
| 2039 |
|
|
subword of this hardreg to a different, also live pseudo,
|
| 2040 |
|
|
because only another subword of the hardreg is actually
|
| 2041 |
|
|
used in the insn. This cannot happen if the pseudo has
|
| 2042 |
|
|
been assigned exactly one hardreg. See PR 33732. */
|
| 2043 |
|
|
&& hard_regno_nregs[REGNO (in)][GET_MODE (in)] == 1)))
|
| 2044 |
|
|
{
|
| 2045 |
|
|
unsigned int regno = REGNO (in) + in_offset;
|
| 2046 |
|
|
unsigned int nwords = hard_regno_nregs[regno][inmode];
|
| 2047 |
|
|
|
| 2048 |
|
|
if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0)
|
| 2049 |
|
|
&& ! hard_reg_set_here_p (regno, regno + nwords,
|
| 2050 |
|
|
PATTERN (this_insn))
|
| 2051 |
|
|
&& (! earlyclobber
|
| 2052 |
|
|
|| ! refers_to_regno_for_reload_p (regno, regno + nwords,
|
| 2053 |
|
|
PATTERN (this_insn), inloc)))
|
| 2054 |
|
|
{
|
| 2055 |
|
|
unsigned int i;
|
| 2056 |
|
|
|
| 2057 |
|
|
for (i = 0; i < nwords; i++)
|
| 2058 |
|
|
if (! TEST_HARD_REG_BIT (reg_class_contents[(int) rclass],
|
| 2059 |
|
|
regno + i))
|
| 2060 |
|
|
break;
|
| 2061 |
|
|
|
| 2062 |
|
|
if (i == nwords)
|
| 2063 |
|
|
{
|
| 2064 |
|
|
/* If we were going to use OUT as the reload reg
|
| 2065 |
|
|
and changed our mind, it means OUT is a dummy that
|
| 2066 |
|
|
dies here. So don't bother copying value to it. */
|
| 2067 |
|
|
if (for_real >= 0 && value == real_out)
|
| 2068 |
|
|
rld[for_real].out = 0;
|
| 2069 |
|
|
if (REG_P (real_in))
|
| 2070 |
|
|
value = real_in;
|
| 2071 |
|
|
else
|
| 2072 |
|
|
value = gen_rtx_REG (inmode, regno);
|
| 2073 |
|
|
}
|
| 2074 |
|
|
}
|
| 2075 |
|
|
}
|
| 2076 |
|
|
|
| 2077 |
|
|
return value;
|
| 2078 |
|
|
}
|
| 2079 |
|
|
|
| 2080 |
|
|
/* This page contains subroutines used mainly for determining
|
| 2081 |
|
|
whether the IN or an OUT of a reload can serve as the
|
| 2082 |
|
|
reload register. */
|
| 2083 |
|
|
|
| 2084 |
|
|
/* Return 1 if X is an operand of an insn that is being earlyclobbered. */
|
| 2085 |
|
|
|
| 2086 |
|
|
int
|
| 2087 |
|
|
earlyclobber_operand_p (rtx x)
|
| 2088 |
|
|
{
|
| 2089 |
|
|
int i;
|
| 2090 |
|
|
|
| 2091 |
|
|
for (i = 0; i < n_earlyclobbers; i++)
|
| 2092 |
|
|
if (reload_earlyclobbers[i] == x)
|
| 2093 |
|
|
return 1;
|
| 2094 |
|
|
|
| 2095 |
|
|
return 0;
|
| 2096 |
|
|
}
|
| 2097 |
|
|
|
| 2098 |
|
|
/* Return 1 if expression X alters a hard reg in the range
|
| 2099 |
|
|
from BEG_REGNO (inclusive) to END_REGNO (exclusive),
|
| 2100 |
|
|
either explicitly or in the guise of a pseudo-reg allocated to REGNO.
|
| 2101 |
|
|
X should be the body of an instruction. */
|
| 2102 |
|
|
|
| 2103 |
|
|
static int
|
| 2104 |
|
|
hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
|
| 2105 |
|
|
{
|
| 2106 |
|
|
if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
|
| 2107 |
|
|
{
|
| 2108 |
|
|
rtx op0 = SET_DEST (x);
|
| 2109 |
|
|
|
| 2110 |
|
|
while (GET_CODE (op0) == SUBREG)
|
| 2111 |
|
|
op0 = SUBREG_REG (op0);
|
| 2112 |
|
|
if (REG_P (op0))
|
| 2113 |
|
|
{
|
| 2114 |
|
|
unsigned int r = REGNO (op0);
|
| 2115 |
|
|
|
| 2116 |
|
|
/* See if this reg overlaps range under consideration. */
|
| 2117 |
|
|
if (r < end_regno
|
| 2118 |
|
|
&& end_hard_regno (GET_MODE (op0), r) > beg_regno)
|
| 2119 |
|
|
return 1;
|
| 2120 |
|
|
}
|
| 2121 |
|
|
}
|
| 2122 |
|
|
else if (GET_CODE (x) == PARALLEL)
|
| 2123 |
|
|
{
|
| 2124 |
|
|
int i = XVECLEN (x, 0) - 1;
|
| 2125 |
|
|
|
| 2126 |
|
|
for (; i >= 0; i--)
|
| 2127 |
|
|
if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i)))
|
| 2128 |
|
|
return 1;
|
| 2129 |
|
|
}
|
| 2130 |
|
|
|
| 2131 |
|
|
return 0;
|
| 2132 |
|
|
}
|
| 2133 |
|
|
|
| 2134 |
|
|
/* Return 1 if ADDR is a valid memory address for mode MODE
|
| 2135 |
|
|
in address space AS, and check that each pseudo reg has the
|
| 2136 |
|
|
proper kind of hard reg. */
|
| 2137 |
|
|
|
| 2138 |
|
|
int
|
| 2139 |
|
|
strict_memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED,
|
| 2140 |
|
|
rtx addr, addr_space_t as)
|
| 2141 |
|
|
{
|
| 2142 |
|
|
#ifdef GO_IF_LEGITIMATE_ADDRESS
|
| 2143 |
|
|
gcc_assert (ADDR_SPACE_GENERIC_P (as));
|
| 2144 |
|
|
GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
|
| 2145 |
|
|
return 0;
|
| 2146 |
|
|
|
| 2147 |
|
|
win:
|
| 2148 |
|
|
return 1;
|
| 2149 |
|
|
#else
|
| 2150 |
|
|
return targetm.addr_space.legitimate_address_p (mode, addr, 1, as);
|
| 2151 |
|
|
#endif
|
| 2152 |
|
|
}
|
| 2153 |
|
|
|
| 2154 |
|
|
/* Like rtx_equal_p except that it allows a REG and a SUBREG to match
|
| 2155 |
|
|
if they are the same hard reg, and has special hacks for
|
| 2156 |
|
|
autoincrement and autodecrement.
|
| 2157 |
|
|
This is specifically intended for find_reloads to use
|
| 2158 |
|
|
in determining whether two operands match.
|
| 2159 |
|
|
X is the operand whose number is the lower of the two.
|
| 2160 |
|
|
|
| 2161 |
|
|
The value is 2 if Y contains a pre-increment that matches
|
| 2162 |
|
|
a non-incrementing address in X. */
|
| 2163 |
|
|
|
| 2164 |
|
|
/* ??? To be completely correct, we should arrange to pass
|
| 2165 |
|
|
for X the output operand and for Y the input operand.
|
| 2166 |
|
|
For now, we assume that the output operand has the lower number
|
| 2167 |
|
|
because that is natural in (SET output (... input ...)). */
|
| 2168 |
|
|
|
| 2169 |
|
|
int
|
| 2170 |
|
|
operands_match_p (rtx x, rtx y)
|
| 2171 |
|
|
{
|
| 2172 |
|
|
int i;
|
| 2173 |
|
|
RTX_CODE code = GET_CODE (x);
|
| 2174 |
|
|
const char *fmt;
|
| 2175 |
|
|
int success_2;
|
| 2176 |
|
|
|
| 2177 |
|
|
if (x == y)
|
| 2178 |
|
|
return 1;
|
| 2179 |
|
|
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
|
| 2180 |
|
|
&& (REG_P (y) || (GET_CODE (y) == SUBREG
|
| 2181 |
|
|
&& REG_P (SUBREG_REG (y)))))
|
| 2182 |
|
|
{
|
| 2183 |
|
|
int j;
|
| 2184 |
|
|
|
| 2185 |
|
|
if (code == SUBREG)
|
| 2186 |
|
|
{
|
| 2187 |
|
|
i = REGNO (SUBREG_REG (x));
|
| 2188 |
|
|
if (i >= FIRST_PSEUDO_REGISTER)
|
| 2189 |
|
|
goto slow;
|
| 2190 |
|
|
i += subreg_regno_offset (REGNO (SUBREG_REG (x)),
|
| 2191 |
|
|
GET_MODE (SUBREG_REG (x)),
|
| 2192 |
|
|
SUBREG_BYTE (x),
|
| 2193 |
|
|
GET_MODE (x));
|
| 2194 |
|
|
}
|
| 2195 |
|
|
else
|
| 2196 |
|
|
i = REGNO (x);
|
| 2197 |
|
|
|
| 2198 |
|
|
if (GET_CODE (y) == SUBREG)
|
| 2199 |
|
|
{
|
| 2200 |
|
|
j = REGNO (SUBREG_REG (y));
|
| 2201 |
|
|
if (j >= FIRST_PSEUDO_REGISTER)
|
| 2202 |
|
|
goto slow;
|
| 2203 |
|
|
j += subreg_regno_offset (REGNO (SUBREG_REG (y)),
|
| 2204 |
|
|
GET_MODE (SUBREG_REG (y)),
|
| 2205 |
|
|
SUBREG_BYTE (y),
|
| 2206 |
|
|
GET_MODE (y));
|
| 2207 |
|
|
}
|
| 2208 |
|
|
else
|
| 2209 |
|
|
j = REGNO (y);
|
| 2210 |
|
|
|
| 2211 |
|
|
/* On a WORDS_BIG_ENDIAN machine, point to the last register of a
|
| 2212 |
|
|
multiple hard register group of scalar integer registers, so that
|
| 2213 |
|
|
for example (reg:DI 0) and (reg:SI 1) will be considered the same
|
| 2214 |
|
|
register. */
|
| 2215 |
|
|
if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD
|
| 2216 |
|
|
&& SCALAR_INT_MODE_P (GET_MODE (x))
|
| 2217 |
|
|
&& i < FIRST_PSEUDO_REGISTER)
|
| 2218 |
|
|
i += hard_regno_nregs[i][GET_MODE (x)] - 1;
|
| 2219 |
|
|
if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD
|
| 2220 |
|
|
&& SCALAR_INT_MODE_P (GET_MODE (y))
|
| 2221 |
|
|
&& j < FIRST_PSEUDO_REGISTER)
|
| 2222 |
|
|
j += hard_regno_nregs[j][GET_MODE (y)] - 1;
|
| 2223 |
|
|
|
| 2224 |
|
|
return i == j;
|
| 2225 |
|
|
}
|
| 2226 |
|
|
/* If two operands must match, because they are really a single
|
| 2227 |
|
|
operand of an assembler insn, then two postincrements are invalid
|
| 2228 |
|
|
because the assembler insn would increment only once.
|
| 2229 |
|
|
On the other hand, a postincrement matches ordinary indexing
|
| 2230 |
|
|
if the postincrement is the output operand. */
|
| 2231 |
|
|
if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
|
| 2232 |
|
|
return operands_match_p (XEXP (x, 0), y);
|
| 2233 |
|
|
/* Two preincrements are invalid
|
| 2234 |
|
|
because the assembler insn would increment only once.
|
| 2235 |
|
|
On the other hand, a preincrement matches ordinary indexing
|
| 2236 |
|
|
if the preincrement is the input operand.
|
| 2237 |
|
|
In this case, return 2, since some callers need to do special
|
| 2238 |
|
|
things when this happens. */
|
| 2239 |
|
|
if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
|
| 2240 |
|
|
|| GET_CODE (y) == PRE_MODIFY)
|
| 2241 |
|
|
return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
|
| 2242 |
|
|
|
| 2243 |
|
|
slow:
|
| 2244 |
|
|
|
| 2245 |
|
|
/* Now we have disposed of all the cases in which different rtx codes
|
| 2246 |
|
|
can match. */
|
| 2247 |
|
|
if (code != GET_CODE (y))
|
| 2248 |
|
|
return 0;
|
| 2249 |
|
|
|
| 2250 |
|
|
/* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
|
| 2251 |
|
|
if (GET_MODE (x) != GET_MODE (y))
|
| 2252 |
|
|
return 0;
|
| 2253 |
|
|
|
| 2254 |
|
|
/* MEMs refering to different address space are not equivalent. */
|
| 2255 |
|
|
if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y))
|
| 2256 |
|
|
return 0;
|
| 2257 |
|
|
|
| 2258 |
|
|
switch (code)
|
| 2259 |
|
|
{
|
| 2260 |
|
|
case CONST_INT:
|
| 2261 |
|
|
case CONST_DOUBLE:
|
| 2262 |
|
|
case CONST_FIXED:
|
| 2263 |
|
|
return 0;
|
| 2264 |
|
|
|
| 2265 |
|
|
case LABEL_REF:
|
| 2266 |
|
|
return XEXP (x, 0) == XEXP (y, 0);
|
| 2267 |
|
|
case SYMBOL_REF:
|
| 2268 |
|
|
return XSTR (x, 0) == XSTR (y, 0);
|
| 2269 |
|
|
|
| 2270 |
|
|
default:
|
| 2271 |
|
|
break;
|
| 2272 |
|
|
}
|
| 2273 |
|
|
|
| 2274 |
|
|
/* Compare the elements. If any pair of corresponding elements
|
| 2275 |
|
|
fail to match, return 0 for the whole things. */
|
| 2276 |
|
|
|
| 2277 |
|
|
success_2 = 0;
|
| 2278 |
|
|
fmt = GET_RTX_FORMAT (code);
|
| 2279 |
|
|
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 2280 |
|
|
{
|
| 2281 |
|
|
int val, j;
|
| 2282 |
|
|
switch (fmt[i])
|
| 2283 |
|
|
{
|
| 2284 |
|
|
case 'w':
|
| 2285 |
|
|
if (XWINT (x, i) != XWINT (y, i))
|
| 2286 |
|
|
return 0;
|
| 2287 |
|
|
break;
|
| 2288 |
|
|
|
| 2289 |
|
|
case 'i':
|
| 2290 |
|
|
if (XINT (x, i) != XINT (y, i))
|
| 2291 |
|
|
return 0;
|
| 2292 |
|
|
break;
|
| 2293 |
|
|
|
| 2294 |
|
|
case 'e':
|
| 2295 |
|
|
val = operands_match_p (XEXP (x, i), XEXP (y, i));
|
| 2296 |
|
|
if (val == 0)
|
| 2297 |
|
|
return 0;
|
| 2298 |
|
|
/* If any subexpression returns 2,
|
| 2299 |
|
|
we should return 2 if we are successful. */
|
| 2300 |
|
|
if (val == 2)
|
| 2301 |
|
|
success_2 = 1;
|
| 2302 |
|
|
break;
|
| 2303 |
|
|
|
| 2304 |
|
|
case '0':
|
| 2305 |
|
|
break;
|
| 2306 |
|
|
|
| 2307 |
|
|
case 'E':
|
| 2308 |
|
|
if (XVECLEN (x, i) != XVECLEN (y, i))
|
| 2309 |
|
|
return 0;
|
| 2310 |
|
|
for (j = XVECLEN (x, i) - 1; j >= 0; --j)
|
| 2311 |
|
|
{
|
| 2312 |
|
|
val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j));
|
| 2313 |
|
|
if (val == 0)
|
| 2314 |
|
|
return 0;
|
| 2315 |
|
|
if (val == 2)
|
| 2316 |
|
|
success_2 = 1;
|
| 2317 |
|
|
}
|
| 2318 |
|
|
break;
|
| 2319 |
|
|
|
| 2320 |
|
|
/* It is believed that rtx's at this level will never
|
| 2321 |
|
|
contain anything but integers and other rtx's,
|
| 2322 |
|
|
except for within LABEL_REFs and SYMBOL_REFs. */
|
| 2323 |
|
|
default:
|
| 2324 |
|
|
gcc_unreachable ();
|
| 2325 |
|
|
}
|
| 2326 |
|
|
}
|
| 2327 |
|
|
return 1 + success_2;
|
| 2328 |
|
|
}
|
| 2329 |
|
|
|
| 2330 |
|
|
/* Describe the range of registers or memory referenced by X.
|
| 2331 |
|
|
If X is a register, set REG_FLAG and put the first register
|
| 2332 |
|
|
number into START and the last plus one into END.
|
| 2333 |
|
|
If X is a memory reference, put a base address into BASE
|
| 2334 |
|
|
and a range of integer offsets into START and END.
|
| 2335 |
|
|
If X is pushing on the stack, we can assume it causes no trouble,
|
| 2336 |
|
|
so we set the SAFE field. */
|
| 2337 |
|
|
|
| 2338 |
|
|
static struct decomposition
|
| 2339 |
|
|
decompose (rtx x)
|
| 2340 |
|
|
{
|
| 2341 |
|
|
struct decomposition val;
|
| 2342 |
|
|
int all_const = 0;
|
| 2343 |
|
|
|
| 2344 |
|
|
memset (&val, 0, sizeof (val));
|
| 2345 |
|
|
|
| 2346 |
|
|
switch (GET_CODE (x))
|
| 2347 |
|
|
{
|
| 2348 |
|
|
case MEM:
|
| 2349 |
|
|
{
|
| 2350 |
|
|
rtx base = NULL_RTX, offset = 0;
|
| 2351 |
|
|
rtx addr = XEXP (x, 0);
|
| 2352 |
|
|
|
| 2353 |
|
|
if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
|
| 2354 |
|
|
|| GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
|
| 2355 |
|
|
{
|
| 2356 |
|
|
val.base = XEXP (addr, 0);
|
| 2357 |
|
|
val.start = -GET_MODE_SIZE (GET_MODE (x));
|
| 2358 |
|
|
val.end = GET_MODE_SIZE (GET_MODE (x));
|
| 2359 |
|
|
val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
|
| 2360 |
|
|
return val;
|
| 2361 |
|
|
}
|
| 2362 |
|
|
|
| 2363 |
|
|
if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
|
| 2364 |
|
|
{
|
| 2365 |
|
|
if (GET_CODE (XEXP (addr, 1)) == PLUS
|
| 2366 |
|
|
&& XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
|
| 2367 |
|
|
&& CONSTANT_P (XEXP (XEXP (addr, 1), 1)))
|
| 2368 |
|
|
{
|
| 2369 |
|
|
val.base = XEXP (addr, 0);
|
| 2370 |
|
|
val.start = -INTVAL (XEXP (XEXP (addr, 1), 1));
|
| 2371 |
|
|
val.end = INTVAL (XEXP (XEXP (addr, 1), 1));
|
| 2372 |
|
|
val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
|
| 2373 |
|
|
return val;
|
| 2374 |
|
|
}
|
| 2375 |
|
|
}
|
| 2376 |
|
|
|
| 2377 |
|
|
if (GET_CODE (addr) == CONST)
|
| 2378 |
|
|
{
|
| 2379 |
|
|
addr = XEXP (addr, 0);
|
| 2380 |
|
|
all_const = 1;
|
| 2381 |
|
|
}
|
| 2382 |
|
|
if (GET_CODE (addr) == PLUS)
|
| 2383 |
|
|
{
|
| 2384 |
|
|
if (CONSTANT_P (XEXP (addr, 0)))
|
| 2385 |
|
|
{
|
| 2386 |
|
|
base = XEXP (addr, 1);
|
| 2387 |
|
|
offset = XEXP (addr, 0);
|
| 2388 |
|
|
}
|
| 2389 |
|
|
else if (CONSTANT_P (XEXP (addr, 1)))
|
| 2390 |
|
|
{
|
| 2391 |
|
|
base = XEXP (addr, 0);
|
| 2392 |
|
|
offset = XEXP (addr, 1);
|
| 2393 |
|
|
}
|
| 2394 |
|
|
}
|
| 2395 |
|
|
|
| 2396 |
|
|
if (offset == 0)
|
| 2397 |
|
|
{
|
| 2398 |
|
|
base = addr;
|
| 2399 |
|
|
offset = const0_rtx;
|
| 2400 |
|
|
}
|
| 2401 |
|
|
if (GET_CODE (offset) == CONST)
|
| 2402 |
|
|
offset = XEXP (offset, 0);
|
| 2403 |
|
|
if (GET_CODE (offset) == PLUS)
|
| 2404 |
|
|
{
|
| 2405 |
|
|
if (CONST_INT_P (XEXP (offset, 0)))
|
| 2406 |
|
|
{
|
| 2407 |
|
|
base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1));
|
| 2408 |
|
|
offset = XEXP (offset, 0);
|
| 2409 |
|
|
}
|
| 2410 |
|
|
else if (CONST_INT_P (XEXP (offset, 1)))
|
| 2411 |
|
|
{
|
| 2412 |
|
|
base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0));
|
| 2413 |
|
|
offset = XEXP (offset, 1);
|
| 2414 |
|
|
}
|
| 2415 |
|
|
else
|
| 2416 |
|
|
{
|
| 2417 |
|
|
base = gen_rtx_PLUS (GET_MODE (base), base, offset);
|
| 2418 |
|
|
offset = const0_rtx;
|
| 2419 |
|
|
}
|
| 2420 |
|
|
}
|
| 2421 |
|
|
else if (!CONST_INT_P (offset))
|
| 2422 |
|
|
{
|
| 2423 |
|
|
base = gen_rtx_PLUS (GET_MODE (base), base, offset);
|
| 2424 |
|
|
offset = const0_rtx;
|
| 2425 |
|
|
}
|
| 2426 |
|
|
|
| 2427 |
|
|
if (all_const && GET_CODE (base) == PLUS)
|
| 2428 |
|
|
base = gen_rtx_CONST (GET_MODE (base), base);
|
| 2429 |
|
|
|
| 2430 |
|
|
gcc_assert (CONST_INT_P (offset));
|
| 2431 |
|
|
|
| 2432 |
|
|
val.start = INTVAL (offset);
|
| 2433 |
|
|
val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
|
| 2434 |
|
|
val.base = base;
|
| 2435 |
|
|
}
|
| 2436 |
|
|
break;
|
| 2437 |
|
|
|
| 2438 |
|
|
case REG:
|
| 2439 |
|
|
val.reg_flag = 1;
|
| 2440 |
|
|
val.start = true_regnum (x);
|
| 2441 |
|
|
if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER)
|
| 2442 |
|
|
{
|
| 2443 |
|
|
/* A pseudo with no hard reg. */
|
| 2444 |
|
|
val.start = REGNO (x);
|
| 2445 |
|
|
val.end = val.start + 1;
|
| 2446 |
|
|
}
|
| 2447 |
|
|
else
|
| 2448 |
|
|
/* A hard reg. */
|
| 2449 |
|
|
val.end = end_hard_regno (GET_MODE (x), val.start);
|
| 2450 |
|
|
break;
|
| 2451 |
|
|
|
| 2452 |
|
|
case SUBREG:
|
| 2453 |
|
|
if (!REG_P (SUBREG_REG (x)))
|
| 2454 |
|
|
/* This could be more precise, but it's good enough. */
|
| 2455 |
|
|
return decompose (SUBREG_REG (x));
|
| 2456 |
|
|
val.reg_flag = 1;
|
| 2457 |
|
|
val.start = true_regnum (x);
|
| 2458 |
|
|
if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER)
|
| 2459 |
|
|
return decompose (SUBREG_REG (x));
|
| 2460 |
|
|
else
|
| 2461 |
|
|
/* A hard reg. */
|
| 2462 |
|
|
val.end = val.start + subreg_nregs (x);
|
| 2463 |
|
|
break;
|
| 2464 |
|
|
|
| 2465 |
|
|
case SCRATCH:
|
| 2466 |
|
|
/* This hasn't been assigned yet, so it can't conflict yet. */
|
| 2467 |
|
|
val.safe = 1;
|
| 2468 |
|
|
break;
|
| 2469 |
|
|
|
| 2470 |
|
|
default:
|
| 2471 |
|
|
gcc_assert (CONSTANT_P (x));
|
| 2472 |
|
|
val.safe = 1;
|
| 2473 |
|
|
break;
|
| 2474 |
|
|
}
|
| 2475 |
|
|
return val;
|
| 2476 |
|
|
}
|
| 2477 |
|
|
|
| 2478 |
|
|
/* Return 1 if altering Y will not modify the value of X.
|
| 2479 |
|
|
Y is also described by YDATA, which should be decompose (Y). */
|
| 2480 |
|
|
|
| 2481 |
|
|
static int
|
| 2482 |
|
|
immune_p (rtx x, rtx y, struct decomposition ydata)
|
| 2483 |
|
|
{
|
| 2484 |
|
|
struct decomposition xdata;
|
| 2485 |
|
|
|
| 2486 |
|
|
if (ydata.reg_flag)
|
| 2487 |
|
|
return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, (rtx*) 0);
|
| 2488 |
|
|
if (ydata.safe)
|
| 2489 |
|
|
return 1;
|
| 2490 |
|
|
|
| 2491 |
|
|
gcc_assert (MEM_P (y));
|
| 2492 |
|
|
/* If Y is memory and X is not, Y can't affect X. */
|
| 2493 |
|
|
if (!MEM_P (x))
|
| 2494 |
|
|
return 1;
|
| 2495 |
|
|
|
| 2496 |
|
|
xdata = decompose (x);
|
| 2497 |
|
|
|
| 2498 |
|
|
if (! rtx_equal_p (xdata.base, ydata.base))
|
| 2499 |
|
|
{
|
| 2500 |
|
|
/* If bases are distinct symbolic constants, there is no overlap. */
|
| 2501 |
|
|
if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))
|
| 2502 |
|
|
return 1;
|
| 2503 |
|
|
/* Constants and stack slots never overlap. */
|
| 2504 |
|
|
if (CONSTANT_P (xdata.base)
|
| 2505 |
|
|
&& (ydata.base == frame_pointer_rtx
|
| 2506 |
|
|
|| ydata.base == hard_frame_pointer_rtx
|
| 2507 |
|
|
|| ydata.base == stack_pointer_rtx))
|
| 2508 |
|
|
return 1;
|
| 2509 |
|
|
if (CONSTANT_P (ydata.base)
|
| 2510 |
|
|
&& (xdata.base == frame_pointer_rtx
|
| 2511 |
|
|
|| xdata.base == hard_frame_pointer_rtx
|
| 2512 |
|
|
|| xdata.base == stack_pointer_rtx))
|
| 2513 |
|
|
return 1;
|
| 2514 |
|
|
/* If either base is variable, we don't know anything. */
|
| 2515 |
|
|
return 0;
|
| 2516 |
|
|
}
|
| 2517 |
|
|
|
| 2518 |
|
|
return (xdata.start >= ydata.end || ydata.start >= xdata.end);
|
| 2519 |
|
|
}
|
| 2520 |
|
|
|
| 2521 |
|
|
/* Similar, but calls decompose. */
|
| 2522 |
|
|
|
| 2523 |
|
|
int
|
| 2524 |
|
|
safe_from_earlyclobber (rtx op, rtx clobber)
|
| 2525 |
|
|
{
|
| 2526 |
|
|
struct decomposition early_data;
|
| 2527 |
|
|
|
| 2528 |
|
|
early_data = decompose (clobber);
|
| 2529 |
|
|
return immune_p (op, clobber, early_data);
|
| 2530 |
|
|
}
|
| 2531 |
|
|
|
| 2532 |
|
|
/* Main entry point of this file: search the body of INSN
|
| 2533 |
|
|
for values that need reloading and record them with push_reload.
|
| 2534 |
|
|
REPLACE nonzero means record also where the values occur
|
| 2535 |
|
|
so that subst_reloads can be used.
|
| 2536 |
|
|
|
| 2537 |
|
|
IND_LEVELS says how many levels of indirection are supported by this
|
| 2538 |
|
|
machine; a value of zero means that a memory reference is not a valid
|
| 2539 |
|
|
memory address.
|
| 2540 |
|
|
|
| 2541 |
|
|
LIVE_KNOWN says we have valid information about which hard
|
| 2542 |
|
|
regs are live at each point in the program; this is true when
|
| 2543 |
|
|
we are called from global_alloc but false when stupid register
|
| 2544 |
|
|
allocation has been done.
|
| 2545 |
|
|
|
| 2546 |
|
|
RELOAD_REG_P if nonzero is a vector indexed by hard reg number
|
| 2547 |
|
|
which is nonnegative if the reg has been commandeered for reloading into.
|
| 2548 |
|
|
It is copied into STATIC_RELOAD_REG_P and referenced from there
|
| 2549 |
|
|
by various subroutines.
|
| 2550 |
|
|
|
| 2551 |
|
|
Return TRUE if some operands need to be changed, because of swapping
|
| 2552 |
|
|
commutative operands, reg_equiv_address substitution, or whatever. */
|
| 2553 |
|
|
|
| 2554 |
|
|
int
|
| 2555 |
|
|
find_reloads (rtx insn, int replace, int ind_levels, int live_known,
|
| 2556 |
|
|
short *reload_reg_p)
|
| 2557 |
|
|
{
|
| 2558 |
|
|
int insn_code_number;
|
| 2559 |
|
|
int i, j;
|
| 2560 |
|
|
int noperands;
|
| 2561 |
|
|
/* These start out as the constraints for the insn
|
| 2562 |
|
|
and they are chewed up as we consider alternatives. */
|
| 2563 |
|
|
const char *constraints[MAX_RECOG_OPERANDS];
|
| 2564 |
|
|
/* These are the preferred classes for an operand, or NO_REGS if it isn't
|
| 2565 |
|
|
a register. */
|
| 2566 |
|
|
enum reg_class preferred_class[MAX_RECOG_OPERANDS];
|
| 2567 |
|
|
char pref_or_nothing[MAX_RECOG_OPERANDS];
|
| 2568 |
|
|
/* Nonzero for a MEM operand whose entire address needs a reload.
|
| 2569 |
|
|
May be -1 to indicate the entire address may or may not need a reload. */
|
| 2570 |
|
|
int address_reloaded[MAX_RECOG_OPERANDS];
|
| 2571 |
|
|
/* Nonzero for an address operand that needs to be completely reloaded.
|
| 2572 |
|
|
May be -1 to indicate the entire operand may or may not need a reload. */
|
| 2573 |
|
|
int address_operand_reloaded[MAX_RECOG_OPERANDS];
|
| 2574 |
|
|
/* Value of enum reload_type to use for operand. */
|
| 2575 |
|
|
enum reload_type operand_type[MAX_RECOG_OPERANDS];
|
| 2576 |
|
|
/* Value of enum reload_type to use within address of operand. */
|
| 2577 |
|
|
enum reload_type address_type[MAX_RECOG_OPERANDS];
|
| 2578 |
|
|
/* Save the usage of each operand. */
|
| 2579 |
|
|
enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS];
|
| 2580 |
|
|
int no_input_reloads = 0, no_output_reloads = 0;
|
| 2581 |
|
|
int n_alternatives;
|
| 2582 |
|
|
enum reg_class this_alternative[MAX_RECOG_OPERANDS];
|
| 2583 |
|
|
char this_alternative_match_win[MAX_RECOG_OPERANDS];
|
| 2584 |
|
|
char this_alternative_win[MAX_RECOG_OPERANDS];
|
| 2585 |
|
|
char this_alternative_offmemok[MAX_RECOG_OPERANDS];
|
| 2586 |
|
|
char this_alternative_earlyclobber[MAX_RECOG_OPERANDS];
|
| 2587 |
|
|
int this_alternative_matches[MAX_RECOG_OPERANDS];
|
| 2588 |
|
|
int swapped;
|
| 2589 |
|
|
int goal_alternative[MAX_RECOG_OPERANDS];
|
| 2590 |
|
|
int this_alternative_number;
|
| 2591 |
|
|
int goal_alternative_number = 0;
|
| 2592 |
|
|
int operand_reloadnum[MAX_RECOG_OPERANDS];
|
| 2593 |
|
|
int goal_alternative_matches[MAX_RECOG_OPERANDS];
|
| 2594 |
|
|
int goal_alternative_matched[MAX_RECOG_OPERANDS];
|
| 2595 |
|
|
char goal_alternative_match_win[MAX_RECOG_OPERANDS];
|
| 2596 |
|
|
char goal_alternative_win[MAX_RECOG_OPERANDS];
|
| 2597 |
|
|
char goal_alternative_offmemok[MAX_RECOG_OPERANDS];
|
| 2598 |
|
|
char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS];
|
| 2599 |
|
|
int goal_alternative_swapped;
|
| 2600 |
|
|
int best;
|
| 2601 |
|
|
int best_small_class_operands_num;
|
| 2602 |
|
|
int commutative;
|
| 2603 |
|
|
char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
|
| 2604 |
|
|
rtx substed_operand[MAX_RECOG_OPERANDS];
|
| 2605 |
|
|
rtx body = PATTERN (insn);
|
| 2606 |
|
|
rtx set = single_set (insn);
|
| 2607 |
|
|
int goal_earlyclobber = 0, this_earlyclobber;
|
| 2608 |
|
|
enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
|
| 2609 |
|
|
int retval = 0;
|
| 2610 |
|
|
|
| 2611 |
|
|
this_insn = insn;
|
| 2612 |
|
|
n_reloads = 0;
|
| 2613 |
|
|
n_replacements = 0;
|
| 2614 |
|
|
n_earlyclobbers = 0;
|
| 2615 |
|
|
replace_reloads = replace;
|
| 2616 |
|
|
hard_regs_live_known = live_known;
|
| 2617 |
|
|
static_reload_reg_p = reload_reg_p;
|
| 2618 |
|
|
|
| 2619 |
|
|
/* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
|
| 2620 |
|
|
neither are insns that SET cc0. Insns that use CC0 are not allowed
|
| 2621 |
|
|
to have any input reloads. */
|
| 2622 |
|
|
if (JUMP_P (insn) || CALL_P (insn))
|
| 2623 |
|
|
no_output_reloads = 1;
|
| 2624 |
|
|
|
| 2625 |
|
|
#ifdef HAVE_cc0
|
| 2626 |
|
|
if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
|
| 2627 |
|
|
no_input_reloads = 1;
|
| 2628 |
|
|
if (reg_set_p (cc0_rtx, PATTERN (insn)))
|
| 2629 |
|
|
no_output_reloads = 1;
|
| 2630 |
|
|
#endif
|
| 2631 |
|
|
|
| 2632 |
|
|
#ifdef SECONDARY_MEMORY_NEEDED
|
| 2633 |
|
|
/* The eliminated forms of any secondary memory locations are per-insn, so
|
| 2634 |
|
|
clear them out here. */
|
| 2635 |
|
|
|
| 2636 |
|
|
if (secondary_memlocs_elim_used)
|
| 2637 |
|
|
{
|
| 2638 |
|
|
memset (secondary_memlocs_elim, 0,
|
| 2639 |
|
|
sizeof (secondary_memlocs_elim[0]) * secondary_memlocs_elim_used);
|
| 2640 |
|
|
secondary_memlocs_elim_used = 0;
|
| 2641 |
|
|
}
|
| 2642 |
|
|
#endif
|
| 2643 |
|
|
|
| 2644 |
|
|
/* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
|
| 2645 |
|
|
is cheap to move between them. If it is not, there may not be an insn
|
| 2646 |
|
|
to do the copy, so we may need a reload. */
|
| 2647 |
|
|
if (GET_CODE (body) == SET
|
| 2648 |
|
|
&& REG_P (SET_DEST (body))
|
| 2649 |
|
|
&& REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
|
| 2650 |
|
|
&& REG_P (SET_SRC (body))
|
| 2651 |
|
|
&& REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
|
| 2652 |
|
|
&& REGISTER_MOVE_COST (GET_MODE (SET_SRC (body)),
|
| 2653 |
|
|
REGNO_REG_CLASS (REGNO (SET_SRC (body))),
|
| 2654 |
|
|
REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
|
| 2655 |
|
|
return 0;
|
| 2656 |
|
|
|
| 2657 |
|
|
extract_insn (insn);
|
| 2658 |
|
|
|
| 2659 |
|
|
noperands = reload_n_operands = recog_data.n_operands;
|
| 2660 |
|
|
n_alternatives = recog_data.n_alternatives;
|
| 2661 |
|
|
|
| 2662 |
|
|
/* Just return "no reloads" if insn has no operands with constraints. */
|
| 2663 |
|
|
if (noperands == 0 || n_alternatives == 0)
|
| 2664 |
|
|
return 0;
|
| 2665 |
|
|
|
| 2666 |
|
|
insn_code_number = INSN_CODE (insn);
|
| 2667 |
|
|
this_insn_is_asm = insn_code_number < 0;
|
| 2668 |
|
|
|
| 2669 |
|
|
memcpy (operand_mode, recog_data.operand_mode,
|
| 2670 |
|
|
noperands * sizeof (enum machine_mode));
|
| 2671 |
|
|
memcpy (constraints, recog_data.constraints,
|
| 2672 |
|
|
noperands * sizeof (const char *));
|
| 2673 |
|
|
|
| 2674 |
|
|
commutative = -1;
|
| 2675 |
|
|
|
| 2676 |
|
|
/* If we will need to know, later, whether some pair of operands
|
| 2677 |
|
|
are the same, we must compare them now and save the result.
|
| 2678 |
|
|
Reloading the base and index registers will clobber them
|
| 2679 |
|
|
and afterward they will fail to match. */
|
| 2680 |
|
|
|
| 2681 |
|
|
for (i = 0; i < noperands; i++)
|
| 2682 |
|
|
{
|
| 2683 |
|
|
const char *p;
|
| 2684 |
|
|
int c;
|
| 2685 |
|
|
char *end;
|
| 2686 |
|
|
|
| 2687 |
|
|
substed_operand[i] = recog_data.operand[i];
|
| 2688 |
|
|
p = constraints[i];
|
| 2689 |
|
|
|
| 2690 |
|
|
modified[i] = RELOAD_READ;
|
| 2691 |
|
|
|
| 2692 |
|
|
/* Scan this operand's constraint to see if it is an output operand,
|
| 2693 |
|
|
an in-out operand, is commutative, or should match another. */
|
| 2694 |
|
|
|
| 2695 |
|
|
while ((c = *p))
|
| 2696 |
|
|
{
|
| 2697 |
|
|
p += CONSTRAINT_LEN (c, p);
|
| 2698 |
|
|
switch (c)
|
| 2699 |
|
|
{
|
| 2700 |
|
|
case '=':
|
| 2701 |
|
|
modified[i] = RELOAD_WRITE;
|
| 2702 |
|
|
break;
|
| 2703 |
|
|
case '+':
|
| 2704 |
|
|
modified[i] = RELOAD_READ_WRITE;
|
| 2705 |
|
|
break;
|
| 2706 |
|
|
case '%':
|
| 2707 |
|
|
{
|
| 2708 |
|
|
/* The last operand should not be marked commutative. */
|
| 2709 |
|
|
gcc_assert (i != noperands - 1);
|
| 2710 |
|
|
|
| 2711 |
|
|
/* We currently only support one commutative pair of
|
| 2712 |
|
|
operands. Some existing asm code currently uses more
|
| 2713 |
|
|
than one pair. Previously, that would usually work,
|
| 2714 |
|
|
but sometimes it would crash the compiler. We
|
| 2715 |
|
|
continue supporting that case as well as we can by
|
| 2716 |
|
|
silently ignoring all but the first pair. In the
|
| 2717 |
|
|
future we may handle it correctly. */
|
| 2718 |
|
|
if (commutative < 0)
|
| 2719 |
|
|
commutative = i;
|
| 2720 |
|
|
else
|
| 2721 |
|
|
gcc_assert (this_insn_is_asm);
|
| 2722 |
|
|
}
|
| 2723 |
|
|
break;
|
| 2724 |
|
|
/* Use of ISDIGIT is tempting here, but it may get expensive because
|
| 2725 |
|
|
of locale support we don't want. */
|
| 2726 |
|
|
case '0': case '1': case '2': case '3': case '4':
|
| 2727 |
|
|
case '5': case '6': case '7': case '8': case '9':
|
| 2728 |
|
|
{
|
| 2729 |
|
|
c = strtoul (p - 1, &end, 10);
|
| 2730 |
|
|
p = end;
|
| 2731 |
|
|
|
| 2732 |
|
|
operands_match[c][i]
|
| 2733 |
|
|
= operands_match_p (recog_data.operand[c],
|
| 2734 |
|
|
recog_data.operand[i]);
|
| 2735 |
|
|
|
| 2736 |
|
|
/* An operand may not match itself. */
|
| 2737 |
|
|
gcc_assert (c != i);
|
| 2738 |
|
|
|
| 2739 |
|
|
/* If C can be commuted with C+1, and C might need to match I,
|
| 2740 |
|
|
then C+1 might also need to match I. */
|
| 2741 |
|
|
if (commutative >= 0)
|
| 2742 |
|
|
{
|
| 2743 |
|
|
if (c == commutative || c == commutative + 1)
|
| 2744 |
|
|
{
|
| 2745 |
|
|
int other = c + (c == commutative ? 1 : -1);
|
| 2746 |
|
|
operands_match[other][i]
|
| 2747 |
|
|
= operands_match_p (recog_data.operand[other],
|
| 2748 |
|
|
recog_data.operand[i]);
|
| 2749 |
|
|
}
|
| 2750 |
|
|
if (i == commutative || i == commutative + 1)
|
| 2751 |
|
|
{
|
| 2752 |
|
|
int other = i + (i == commutative ? 1 : -1);
|
| 2753 |
|
|
operands_match[c][other]
|
| 2754 |
|
|
= operands_match_p (recog_data.operand[c],
|
| 2755 |
|
|
recog_data.operand[other]);
|
| 2756 |
|
|
}
|
| 2757 |
|
|
/* Note that C is supposed to be less than I.
|
| 2758 |
|
|
No need to consider altering both C and I because in
|
| 2759 |
|
|
that case we would alter one into the other. */
|
| 2760 |
|
|
}
|
| 2761 |
|
|
}
|
| 2762 |
|
|
}
|
| 2763 |
|
|
}
|
| 2764 |
|
|
}
|
| 2765 |
|
|
|
| 2766 |
|
|
/* Examine each operand that is a memory reference or memory address
|
| 2767 |
|
|
and reload parts of the addresses into index registers.
|
| 2768 |
|
|
Also here any references to pseudo regs that didn't get hard regs
|
| 2769 |
|
|
but are equivalent to constants get replaced in the insn itself
|
| 2770 |
|
|
with those constants. Nobody will ever see them again.
|
| 2771 |
|
|
|
| 2772 |
|
|
Finally, set up the preferred classes of each operand. */
|
| 2773 |
|
|
|
| 2774 |
|
|
for (i = 0; i < noperands; i++)
|
| 2775 |
|
|
{
|
| 2776 |
|
|
RTX_CODE code = GET_CODE (recog_data.operand[i]);
|
| 2777 |
|
|
|
| 2778 |
|
|
address_reloaded[i] = 0;
|
| 2779 |
|
|
address_operand_reloaded[i] = 0;
|
| 2780 |
|
|
operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT
|
| 2781 |
|
|
: modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT
|
| 2782 |
|
|
: RELOAD_OTHER);
|
| 2783 |
|
|
address_type[i]
|
| 2784 |
|
|
= (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS
|
| 2785 |
|
|
: modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS
|
| 2786 |
|
|
: RELOAD_OTHER);
|
| 2787 |
|
|
|
| 2788 |
|
|
if (*constraints[i] == 0)
|
| 2789 |
|
|
/* Ignore things like match_operator operands. */
|
| 2790 |
|
|
;
|
| 2791 |
|
|
else if (constraints[i][0] == 'p'
|
| 2792 |
|
|
|| EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i]))
|
| 2793 |
|
|
{
|
| 2794 |
|
|
address_operand_reloaded[i]
|
| 2795 |
|
|
= find_reloads_address (recog_data.operand_mode[i], (rtx*) 0,
|
| 2796 |
|
|
recog_data.operand[i],
|
| 2797 |
|
|
recog_data.operand_loc[i],
|
| 2798 |
|
|
i, operand_type[i], ind_levels, insn);
|
| 2799 |
|
|
|
| 2800 |
|
|
/* If we now have a simple operand where we used to have a
|
| 2801 |
|
|
PLUS or MULT, re-recognize and try again. */
|
| 2802 |
|
|
if ((OBJECT_P (*recog_data.operand_loc[i])
|
| 2803 |
|
|
|| GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
|
| 2804 |
|
|
&& (GET_CODE (recog_data.operand[i]) == MULT
|
| 2805 |
|
|
|| GET_CODE (recog_data.operand[i]) == PLUS))
|
| 2806 |
|
|
{
|
| 2807 |
|
|
INSN_CODE (insn) = -1;
|
| 2808 |
|
|
retval = find_reloads (insn, replace, ind_levels, live_known,
|
| 2809 |
|
|
reload_reg_p);
|
| 2810 |
|
|
return retval;
|
| 2811 |
|
|
}
|
| 2812 |
|
|
|
| 2813 |
|
|
recog_data.operand[i] = *recog_data.operand_loc[i];
|
| 2814 |
|
|
substed_operand[i] = recog_data.operand[i];
|
| 2815 |
|
|
|
| 2816 |
|
|
/* Address operands are reloaded in their existing mode,
|
| 2817 |
|
|
no matter what is specified in the machine description. */
|
| 2818 |
|
|
operand_mode[i] = GET_MODE (recog_data.operand[i]);
|
| 2819 |
|
|
}
|
| 2820 |
|
|
else if (code == MEM)
|
| 2821 |
|
|
{
|
| 2822 |
|
|
address_reloaded[i]
|
| 2823 |
|
|
= find_reloads_address (GET_MODE (recog_data.operand[i]),
|
| 2824 |
|
|
recog_data.operand_loc[i],
|
| 2825 |
|
|
XEXP (recog_data.operand[i], 0),
|
| 2826 |
|
|
&XEXP (recog_data.operand[i], 0),
|
| 2827 |
|
|
i, address_type[i], ind_levels, insn);
|
| 2828 |
|
|
recog_data.operand[i] = *recog_data.operand_loc[i];
|
| 2829 |
|
|
substed_operand[i] = recog_data.operand[i];
|
| 2830 |
|
|
}
|
| 2831 |
|
|
else if (code == SUBREG)
|
| 2832 |
|
|
{
|
| 2833 |
|
|
rtx reg = SUBREG_REG (recog_data.operand[i]);
|
| 2834 |
|
|
rtx op
|
| 2835 |
|
|
= find_reloads_toplev (recog_data.operand[i], i, address_type[i],
|
| 2836 |
|
|
ind_levels,
|
| 2837 |
|
|
set != 0
|
| 2838 |
|
|
&& &SET_DEST (set) == recog_data.operand_loc[i],
|
| 2839 |
|
|
insn,
|
| 2840 |
|
|
&address_reloaded[i]);
|
| 2841 |
|
|
|
| 2842 |
|
|
/* If we made a MEM to load (a part of) the stackslot of a pseudo
|
| 2843 |
|
|
that didn't get a hard register, emit a USE with a REG_EQUAL
|
| 2844 |
|
|
note in front so that we might inherit a previous, possibly
|
| 2845 |
|
|
wider reload. */
|
| 2846 |
|
|
|
| 2847 |
|
|
if (replace
|
| 2848 |
|
|
&& MEM_P (op)
|
| 2849 |
|
|
&& REG_P (reg)
|
| 2850 |
|
|
&& (GET_MODE_SIZE (GET_MODE (reg))
|
| 2851 |
|
|
>= GET_MODE_SIZE (GET_MODE (op)))
|
| 2852 |
|
|
&& reg_equiv_constant[REGNO (reg)] == 0)
|
| 2853 |
|
|
set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg),
|
| 2854 |
|
|
insn),
|
| 2855 |
|
|
REG_EQUAL, reg_equiv_memory_loc[REGNO (reg)]);
|
| 2856 |
|
|
|
| 2857 |
|
|
substed_operand[i] = recog_data.operand[i] = op;
|
| 2858 |
|
|
}
|
| 2859 |
|
|
else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY)
|
| 2860 |
|
|
/* We can get a PLUS as an "operand" as a result of register
|
| 2861 |
|
|
elimination. See eliminate_regs and gen_reload. We handle
|
| 2862 |
|
|
a unary operator by reloading the operand. */
|
| 2863 |
|
|
substed_operand[i] = recog_data.operand[i]
|
| 2864 |
|
|
= find_reloads_toplev (recog_data.operand[i], i, address_type[i],
|
| 2865 |
|
|
ind_levels, 0, insn,
|
| 2866 |
|
|
&address_reloaded[i]);
|
| 2867 |
|
|
else if (code == REG)
|
| 2868 |
|
|
{
|
| 2869 |
|
|
/* This is equivalent to calling find_reloads_toplev.
|
| 2870 |
|
|
The code is duplicated for speed.
|
| 2871 |
|
|
When we find a pseudo always equivalent to a constant,
|
| 2872 |
|
|
we replace it by the constant. We must be sure, however,
|
| 2873 |
|
|
that we don't try to replace it in the insn in which it
|
| 2874 |
|
|
is being set. */
|
| 2875 |
|
|
int regno = REGNO (recog_data.operand[i]);
|
| 2876 |
|
|
if (reg_equiv_constant[regno] != 0
|
| 2877 |
|
|
&& (set == 0 || &SET_DEST (set) != recog_data.operand_loc[i]))
|
| 2878 |
|
|
{
|
| 2879 |
|
|
/* Record the existing mode so that the check if constants are
|
| 2880 |
|
|
allowed will work when operand_mode isn't specified. */
|
| 2881 |
|
|
|
| 2882 |
|
|
if (operand_mode[i] == VOIDmode)
|
| 2883 |
|
|
operand_mode[i] = GET_MODE (recog_data.operand[i]);
|
| 2884 |
|
|
|
| 2885 |
|
|
substed_operand[i] = recog_data.operand[i]
|
| 2886 |
|
|
= reg_equiv_constant[regno];
|
| 2887 |
|
|
}
|
| 2888 |
|
|
if (reg_equiv_memory_loc[regno] != 0
|
| 2889 |
|
|
&& (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
|
| 2890 |
|
|
/* We need not give a valid is_set_dest argument since the case
|
| 2891 |
|
|
of a constant equivalence was checked above. */
|
| 2892 |
|
|
substed_operand[i] = recog_data.operand[i]
|
| 2893 |
|
|
= find_reloads_toplev (recog_data.operand[i], i, address_type[i],
|
| 2894 |
|
|
ind_levels, 0, insn,
|
| 2895 |
|
|
&address_reloaded[i]);
|
| 2896 |
|
|
}
|
| 2897 |
|
|
/* If the operand is still a register (we didn't replace it with an
|
| 2898 |
|
|
equivalent), get the preferred class to reload it into. */
|
| 2899 |
|
|
code = GET_CODE (recog_data.operand[i]);
|
| 2900 |
|
|
preferred_class[i]
|
| 2901 |
|
|
= ((code == REG && REGNO (recog_data.operand[i])
|
| 2902 |
|
|
>= FIRST_PSEUDO_REGISTER)
|
| 2903 |
|
|
? reg_preferred_class (REGNO (recog_data.operand[i]))
|
| 2904 |
|
|
: NO_REGS);
|
| 2905 |
|
|
pref_or_nothing[i]
|
| 2906 |
|
|
= (code == REG
|
| 2907 |
|
|
&& REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER
|
| 2908 |
|
|
&& reg_alternate_class (REGNO (recog_data.operand[i])) == NO_REGS);
|
| 2909 |
|
|
}
|
| 2910 |
|
|
|
| 2911 |
|
|
/* If this is simply a copy from operand 1 to operand 0, merge the
|
| 2912 |
|
|
preferred classes for the operands. */
|
| 2913 |
|
|
if (set != 0 && noperands >= 2 && recog_data.operand[0] == SET_DEST (set)
|
| 2914 |
|
|
&& recog_data.operand[1] == SET_SRC (set))
|
| 2915 |
|
|
{
|
| 2916 |
|
|
preferred_class[0] = preferred_class[1]
|
| 2917 |
|
|
= reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]];
|
| 2918 |
|
|
pref_or_nothing[0] |= pref_or_nothing[1];
|
| 2919 |
|
|
pref_or_nothing[1] |= pref_or_nothing[0];
|
| 2920 |
|
|
}
|
| 2921 |
|
|
|
| 2922 |
|
|
/* Now see what we need for pseudo-regs that didn't get hard regs
|
| 2923 |
|
|
or got the wrong kind of hard reg. For this, we must consider
|
| 2924 |
|
|
all the operands together against the register constraints. */
|
| 2925 |
|
|
|
| 2926 |
|
|
best = MAX_RECOG_OPERANDS * 2 + 600;
|
| 2927 |
|
|
best_small_class_operands_num = 0;
|
| 2928 |
|
|
|
| 2929 |
|
|
swapped = 0;
|
| 2930 |
|
|
goal_alternative_swapped = 0;
|
| 2931 |
|
|
try_swapped:
|
| 2932 |
|
|
|
| 2933 |
|
|
/* The constraints are made of several alternatives.
|
| 2934 |
|
|
Each operand's constraint looks like foo,bar,... with commas
|
| 2935 |
|
|
separating the alternatives. The first alternatives for all
|
| 2936 |
|
|
operands go together, the second alternatives go together, etc.
|
| 2937 |
|
|
|
| 2938 |
|
|
First loop over alternatives. */
|
| 2939 |
|
|
|
| 2940 |
|
|
for (this_alternative_number = 0;
|
| 2941 |
|
|
this_alternative_number < n_alternatives;
|
| 2942 |
|
|
this_alternative_number++)
|
| 2943 |
|
|
{
|
| 2944 |
|
|
/* Loop over operands for one constraint alternative. */
|
| 2945 |
|
|
/* LOSERS counts those that don't fit this alternative
|
| 2946 |
|
|
and would require loading. */
|
| 2947 |
|
|
int losers = 0;
|
| 2948 |
|
|
/* BAD is set to 1 if it some operand can't fit this alternative
|
| 2949 |
|
|
even after reloading. */
|
| 2950 |
|
|
int bad = 0;
|
| 2951 |
|
|
/* REJECT is a count of how undesirable this alternative says it is
|
| 2952 |
|
|
if any reloading is required. If the alternative matches exactly
|
| 2953 |
|
|
then REJECT is ignored, but otherwise it gets this much
|
| 2954 |
|
|
counted against it in addition to the reloading needed. Each
|
| 2955 |
|
|
? counts three times here since we want the disparaging caused by
|
| 2956 |
|
|
a bad register class to only count 1/3 as much. */
|
| 2957 |
|
|
int reject = 0;
|
| 2958 |
|
|
|
| 2959 |
|
|
if (!recog_data.alternative_enabled_p[this_alternative_number])
|
| 2960 |
|
|
{
|
| 2961 |
|
|
int i;
|
| 2962 |
|
|
|
| 2963 |
|
|
for (i = 0; i < recog_data.n_operands; i++)
|
| 2964 |
|
|
constraints[i] = skip_alternative (constraints[i]);
|
| 2965 |
|
|
|
| 2966 |
|
|
continue;
|
| 2967 |
|
|
}
|
| 2968 |
|
|
|
| 2969 |
|
|
this_earlyclobber = 0;
|
| 2970 |
|
|
|
| 2971 |
|
|
for (i = 0; i < noperands; i++)
|
| 2972 |
|
|
{
|
| 2973 |
|
|
const char *p = constraints[i];
|
| 2974 |
|
|
char *end;
|
| 2975 |
|
|
int len;
|
| 2976 |
|
|
int win = 0;
|
| 2977 |
|
|
int did_match = 0;
|
| 2978 |
|
|
/* 0 => this operand can be reloaded somehow for this alternative. */
|
| 2979 |
|
|
int badop = 1;
|
| 2980 |
|
|
/* 0 => this operand can be reloaded if the alternative allows regs. */
|
| 2981 |
|
|
int winreg = 0;
|
| 2982 |
|
|
int c;
|
| 2983 |
|
|
int m;
|
| 2984 |
|
|
rtx operand = recog_data.operand[i];
|
| 2985 |
|
|
int offset = 0;
|
| 2986 |
|
|
/* Nonzero means this is a MEM that must be reloaded into a reg
|
| 2987 |
|
|
regardless of what the constraint says. */
|
| 2988 |
|
|
int force_reload = 0;
|
| 2989 |
|
|
int offmemok = 0;
|
| 2990 |
|
|
/* Nonzero if a constant forced into memory would be OK for this
|
| 2991 |
|
|
operand. */
|
| 2992 |
|
|
int constmemok = 0;
|
| 2993 |
|
|
int earlyclobber = 0;
|
| 2994 |
|
|
|
| 2995 |
|
|
/* If the predicate accepts a unary operator, it means that
|
| 2996 |
|
|
we need to reload the operand, but do not do this for
|
| 2997 |
|
|
match_operator and friends. */
|
| 2998 |
|
|
if (UNARY_P (operand) && *p != 0)
|
| 2999 |
|
|
operand = XEXP (operand, 0);
|
| 3000 |
|
|
|
| 3001 |
|
|
/* If the operand is a SUBREG, extract
|
| 3002 |
|
|
the REG or MEM (or maybe even a constant) within.
|
| 3003 |
|
|
(Constants can occur as a result of reg_equiv_constant.) */
|
| 3004 |
|
|
|
| 3005 |
|
|
while (GET_CODE (operand) == SUBREG)
|
| 3006 |
|
|
{
|
| 3007 |
|
|
/* Offset only matters when operand is a REG and
|
| 3008 |
|
|
it is a hard reg. This is because it is passed
|
| 3009 |
|
|
to reg_fits_class_p if it is a REG and all pseudos
|
| 3010 |
|
|
return 0 from that function. */
|
| 3011 |
|
|
if (REG_P (SUBREG_REG (operand))
|
| 3012 |
|
|
&& REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER)
|
| 3013 |
|
|
{
|
| 3014 |
|
|
if (simplify_subreg_regno (REGNO (SUBREG_REG (operand)),
|
| 3015 |
|
|
GET_MODE (SUBREG_REG (operand)),
|
| 3016 |
|
|
SUBREG_BYTE (operand),
|
| 3017 |
|
|
GET_MODE (operand)) < 0)
|
| 3018 |
|
|
force_reload = 1;
|
| 3019 |
|
|
offset += subreg_regno_offset (REGNO (SUBREG_REG (operand)),
|
| 3020 |
|
|
GET_MODE (SUBREG_REG (operand)),
|
| 3021 |
|
|
SUBREG_BYTE (operand),
|
| 3022 |
|
|
GET_MODE (operand));
|
| 3023 |
|
|
}
|
| 3024 |
|
|
operand = SUBREG_REG (operand);
|
| 3025 |
|
|
/* Force reload if this is a constant or PLUS or if there may
|
| 3026 |
|
|
be a problem accessing OPERAND in the outer mode. */
|
| 3027 |
|
|
if (CONSTANT_P (operand)
|
| 3028 |
|
|
|| GET_CODE (operand) == PLUS
|
| 3029 |
|
|
/* We must force a reload of paradoxical SUBREGs
|
| 3030 |
|
|
of a MEM because the alignment of the inner value
|
| 3031 |
|
|
may not be enough to do the outer reference. On
|
| 3032 |
|
|
big-endian machines, it may also reference outside
|
| 3033 |
|
|
the object.
|
| 3034 |
|
|
|
| 3035 |
|
|
On machines that extend byte operations and we have a
|
| 3036 |
|
|
SUBREG where both the inner and outer modes are no wider
|
| 3037 |
|
|
than a word and the inner mode is narrower, is integral,
|
| 3038 |
|
|
and gets extended when loaded from memory, combine.c has
|
| 3039 |
|
|
made assumptions about the behavior of the machine in such
|
| 3040 |
|
|
register access. If the data is, in fact, in memory we
|
| 3041 |
|
|
must always load using the size assumed to be in the
|
| 3042 |
|
|
register and let the insn do the different-sized
|
| 3043 |
|
|
accesses.
|
| 3044 |
|
|
|
| 3045 |
|
|
This is doubly true if WORD_REGISTER_OPERATIONS. In
|
| 3046 |
|
|
this case eliminate_regs has left non-paradoxical
|
| 3047 |
|
|
subregs for push_reload to see. Make sure it does
|
| 3048 |
|
|
by forcing the reload.
|
| 3049 |
|
|
|
| 3050 |
|
|
??? When is it right at this stage to have a subreg
|
| 3051 |
|
|
of a mem that is _not_ to be handled specially? IMO
|
| 3052 |
|
|
those should have been reduced to just a mem. */
|
| 3053 |
|
|
|| ((MEM_P (operand)
|
| 3054 |
|
|
|| (REG_P (operand)
|
| 3055 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER))
|
| 3056 |
|
|
#ifndef WORD_REGISTER_OPERATIONS
|
| 3057 |
|
|
&& (((GET_MODE_BITSIZE (GET_MODE (operand))
|
| 3058 |
|
|
< BIGGEST_ALIGNMENT)
|
| 3059 |
|
|
&& (GET_MODE_SIZE (operand_mode[i])
|
| 3060 |
|
|
> GET_MODE_SIZE (GET_MODE (operand))))
|
| 3061 |
|
|
|| BYTES_BIG_ENDIAN
|
| 3062 |
|
|
#ifdef LOAD_EXTEND_OP
|
| 3063 |
|
|
|| (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
|
| 3064 |
|
|
&& (GET_MODE_SIZE (GET_MODE (operand))
|
| 3065 |
|
|
<= UNITS_PER_WORD)
|
| 3066 |
|
|
&& (GET_MODE_SIZE (operand_mode[i])
|
| 3067 |
|
|
> GET_MODE_SIZE (GET_MODE (operand)))
|
| 3068 |
|
|
&& INTEGRAL_MODE_P (GET_MODE (operand))
|
| 3069 |
|
|
&& LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN)
|
| 3070 |
|
|
#endif
|
| 3071 |
|
|
)
|
| 3072 |
|
|
#endif
|
| 3073 |
|
|
)
|
| 3074 |
|
|
)
|
| 3075 |
|
|
force_reload = 1;
|
| 3076 |
|
|
}
|
| 3077 |
|
|
|
| 3078 |
|
|
this_alternative[i] = NO_REGS;
|
| 3079 |
|
|
this_alternative_win[i] = 0;
|
| 3080 |
|
|
this_alternative_match_win[i] = 0;
|
| 3081 |
|
|
this_alternative_offmemok[i] = 0;
|
| 3082 |
|
|
this_alternative_earlyclobber[i] = 0;
|
| 3083 |
|
|
this_alternative_matches[i] = -1;
|
| 3084 |
|
|
|
| 3085 |
|
|
/* An empty constraint or empty alternative
|
| 3086 |
|
|
allows anything which matched the pattern. */
|
| 3087 |
|
|
if (*p == 0 || *p == ',')
|
| 3088 |
|
|
win = 1, badop = 0;
|
| 3089 |
|
|
|
| 3090 |
|
|
/* Scan this alternative's specs for this operand;
|
| 3091 |
|
|
set WIN if the operand fits any letter in this alternative.
|
| 3092 |
|
|
Otherwise, clear BADOP if this operand could
|
| 3093 |
|
|
fit some letter after reloads,
|
| 3094 |
|
|
or set WINREG if this operand could fit after reloads
|
| 3095 |
|
|
provided the constraint allows some registers. */
|
| 3096 |
|
|
|
| 3097 |
|
|
do
|
| 3098 |
|
|
switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
|
| 3099 |
|
|
{
|
| 3100 |
|
|
case '\0':
|
| 3101 |
|
|
len = 0;
|
| 3102 |
|
|
break;
|
| 3103 |
|
|
case ',':
|
| 3104 |
|
|
c = '\0';
|
| 3105 |
|
|
break;
|
| 3106 |
|
|
|
| 3107 |
|
|
case '=': case '+': case '*':
|
| 3108 |
|
|
break;
|
| 3109 |
|
|
|
| 3110 |
|
|
case '%':
|
| 3111 |
|
|
/* We only support one commutative marker, the first
|
| 3112 |
|
|
one. We already set commutative above. */
|
| 3113 |
|
|
break;
|
| 3114 |
|
|
|
| 3115 |
|
|
case '?':
|
| 3116 |
|
|
reject += 6;
|
| 3117 |
|
|
break;
|
| 3118 |
|
|
|
| 3119 |
|
|
case '!':
|
| 3120 |
|
|
reject = 600;
|
| 3121 |
|
|
break;
|
| 3122 |
|
|
|
| 3123 |
|
|
case '#':
|
| 3124 |
|
|
/* Ignore rest of this alternative as far as
|
| 3125 |
|
|
reloading is concerned. */
|
| 3126 |
|
|
do
|
| 3127 |
|
|
p++;
|
| 3128 |
|
|
while (*p && *p != ',');
|
| 3129 |
|
|
len = 0;
|
| 3130 |
|
|
break;
|
| 3131 |
|
|
|
| 3132 |
|
|
case '0': case '1': case '2': case '3': case '4':
|
| 3133 |
|
|
case '5': case '6': case '7': case '8': case '9':
|
| 3134 |
|
|
m = strtoul (p, &end, 10);
|
| 3135 |
|
|
p = end;
|
| 3136 |
|
|
len = 0;
|
| 3137 |
|
|
|
| 3138 |
|
|
this_alternative_matches[i] = m;
|
| 3139 |
|
|
/* We are supposed to match a previous operand.
|
| 3140 |
|
|
If we do, we win if that one did.
|
| 3141 |
|
|
If we do not, count both of the operands as losers.
|
| 3142 |
|
|
(This is too conservative, since most of the time
|
| 3143 |
|
|
only a single reload insn will be needed to make
|
| 3144 |
|
|
the two operands win. As a result, this alternative
|
| 3145 |
|
|
may be rejected when it is actually desirable.) */
|
| 3146 |
|
|
if ((swapped && (m != commutative || i != commutative + 1))
|
| 3147 |
|
|
/* If we are matching as if two operands were swapped,
|
| 3148 |
|
|
also pretend that operands_match had been computed
|
| 3149 |
|
|
with swapped.
|
| 3150 |
|
|
But if I is the second of those and C is the first,
|
| 3151 |
|
|
don't exchange them, because operands_match is valid
|
| 3152 |
|
|
only on one side of its diagonal. */
|
| 3153 |
|
|
? (operands_match
|
| 3154 |
|
|
[(m == commutative || m == commutative + 1)
|
| 3155 |
|
|
? 2 * commutative + 1 - m : m]
|
| 3156 |
|
|
[(i == commutative || i == commutative + 1)
|
| 3157 |
|
|
? 2 * commutative + 1 - i : i])
|
| 3158 |
|
|
: operands_match[m][i])
|
| 3159 |
|
|
{
|
| 3160 |
|
|
/* If we are matching a non-offsettable address where an
|
| 3161 |
|
|
offsettable address was expected, then we must reject
|
| 3162 |
|
|
this combination, because we can't reload it. */
|
| 3163 |
|
|
if (this_alternative_offmemok[m]
|
| 3164 |
|
|
&& MEM_P (recog_data.operand[m])
|
| 3165 |
|
|
&& this_alternative[m] == NO_REGS
|
| 3166 |
|
|
&& ! this_alternative_win[m])
|
| 3167 |
|
|
bad = 1;
|
| 3168 |
|
|
|
| 3169 |
|
|
did_match = this_alternative_win[m];
|
| 3170 |
|
|
}
|
| 3171 |
|
|
else
|
| 3172 |
|
|
{
|
| 3173 |
|
|
/* Operands don't match. */
|
| 3174 |
|
|
rtx value;
|
| 3175 |
|
|
int loc1, loc2;
|
| 3176 |
|
|
/* Retroactively mark the operand we had to match
|
| 3177 |
|
|
as a loser, if it wasn't already. */
|
| 3178 |
|
|
if (this_alternative_win[m])
|
| 3179 |
|
|
losers++;
|
| 3180 |
|
|
this_alternative_win[m] = 0;
|
| 3181 |
|
|
if (this_alternative[m] == NO_REGS)
|
| 3182 |
|
|
bad = 1;
|
| 3183 |
|
|
/* But count the pair only once in the total badness of
|
| 3184 |
|
|
this alternative, if the pair can be a dummy reload.
|
| 3185 |
|
|
The pointers in operand_loc are not swapped; swap
|
| 3186 |
|
|
them by hand if necessary. */
|
| 3187 |
|
|
if (swapped && i == commutative)
|
| 3188 |
|
|
loc1 = commutative + 1;
|
| 3189 |
|
|
else if (swapped && i == commutative + 1)
|
| 3190 |
|
|
loc1 = commutative;
|
| 3191 |
|
|
else
|
| 3192 |
|
|
loc1 = i;
|
| 3193 |
|
|
if (swapped && m == commutative)
|
| 3194 |
|
|
loc2 = commutative + 1;
|
| 3195 |
|
|
else if (swapped && m == commutative + 1)
|
| 3196 |
|
|
loc2 = commutative;
|
| 3197 |
|
|
else
|
| 3198 |
|
|
loc2 = m;
|
| 3199 |
|
|
value
|
| 3200 |
|
|
= find_dummy_reload (recog_data.operand[i],
|
| 3201 |
|
|
recog_data.operand[m],
|
| 3202 |
|
|
recog_data.operand_loc[loc1],
|
| 3203 |
|
|
recog_data.operand_loc[loc2],
|
| 3204 |
|
|
operand_mode[i], operand_mode[m],
|
| 3205 |
|
|
this_alternative[m], -1,
|
| 3206 |
|
|
this_alternative_earlyclobber[m]);
|
| 3207 |
|
|
|
| 3208 |
|
|
if (value != 0)
|
| 3209 |
|
|
losers--;
|
| 3210 |
|
|
}
|
| 3211 |
|
|
/* This can be fixed with reloads if the operand
|
| 3212 |
|
|
we are supposed to match can be fixed with reloads. */
|
| 3213 |
|
|
badop = 0;
|
| 3214 |
|
|
this_alternative[i] = this_alternative[m];
|
| 3215 |
|
|
|
| 3216 |
|
|
/* If we have to reload this operand and some previous
|
| 3217 |
|
|
operand also had to match the same thing as this
|
| 3218 |
|
|
operand, we don't know how to do that. So reject this
|
| 3219 |
|
|
alternative. */
|
| 3220 |
|
|
if (! did_match || force_reload)
|
| 3221 |
|
|
for (j = 0; j < i; j++)
|
| 3222 |
|
|
if (this_alternative_matches[j]
|
| 3223 |
|
|
== this_alternative_matches[i])
|
| 3224 |
|
|
badop = 1;
|
| 3225 |
|
|
break;
|
| 3226 |
|
|
|
| 3227 |
|
|
case 'p':
|
| 3228 |
|
|
/* All necessary reloads for an address_operand
|
| 3229 |
|
|
were handled in find_reloads_address. */
|
| 3230 |
|
|
this_alternative[i] = base_reg_class (VOIDmode, ADDRESS,
|
| 3231 |
|
|
SCRATCH);
|
| 3232 |
|
|
win = 1;
|
| 3233 |
|
|
badop = 0;
|
| 3234 |
|
|
break;
|
| 3235 |
|
|
|
| 3236 |
|
|
case TARGET_MEM_CONSTRAINT:
|
| 3237 |
|
|
if (force_reload)
|
| 3238 |
|
|
break;
|
| 3239 |
|
|
if (MEM_P (operand)
|
| 3240 |
|
|
|| (REG_P (operand)
|
| 3241 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER
|
| 3242 |
|
|
&& reg_renumber[REGNO (operand)] < 0))
|
| 3243 |
|
|
win = 1;
|
| 3244 |
|
|
if (CONST_POOL_OK_P (operand))
|
| 3245 |
|
|
badop = 0;
|
| 3246 |
|
|
constmemok = 1;
|
| 3247 |
|
|
break;
|
| 3248 |
|
|
|
| 3249 |
|
|
case '<':
|
| 3250 |
|
|
if (MEM_P (operand)
|
| 3251 |
|
|
&& ! address_reloaded[i]
|
| 3252 |
|
|
&& (GET_CODE (XEXP (operand, 0)) == PRE_DEC
|
| 3253 |
|
|
|| GET_CODE (XEXP (operand, 0)) == POST_DEC))
|
| 3254 |
|
|
win = 1;
|
| 3255 |
|
|
break;
|
| 3256 |
|
|
|
| 3257 |
|
|
case '>':
|
| 3258 |
|
|
if (MEM_P (operand)
|
| 3259 |
|
|
&& ! address_reloaded[i]
|
| 3260 |
|
|
&& (GET_CODE (XEXP (operand, 0)) == PRE_INC
|
| 3261 |
|
|
|| GET_CODE (XEXP (operand, 0)) == POST_INC))
|
| 3262 |
|
|
win = 1;
|
| 3263 |
|
|
break;
|
| 3264 |
|
|
|
| 3265 |
|
|
/* Memory operand whose address is not offsettable. */
|
| 3266 |
|
|
case 'V':
|
| 3267 |
|
|
if (force_reload)
|
| 3268 |
|
|
break;
|
| 3269 |
|
|
if (MEM_P (operand)
|
| 3270 |
|
|
&& ! (ind_levels ? offsettable_memref_p (operand)
|
| 3271 |
|
|
: offsettable_nonstrict_memref_p (operand))
|
| 3272 |
|
|
/* Certain mem addresses will become offsettable
|
| 3273 |
|
|
after they themselves are reloaded. This is important;
|
| 3274 |
|
|
we don't want our own handling of unoffsettables
|
| 3275 |
|
|
to override the handling of reg_equiv_address. */
|
| 3276 |
|
|
&& !(REG_P (XEXP (operand, 0))
|
| 3277 |
|
|
&& (ind_levels == 0
|
| 3278 |
|
|
|| reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
|
| 3279 |
|
|
win = 1;
|
| 3280 |
|
|
break;
|
| 3281 |
|
|
|
| 3282 |
|
|
/* Memory operand whose address is offsettable. */
|
| 3283 |
|
|
case 'o':
|
| 3284 |
|
|
if (force_reload)
|
| 3285 |
|
|
break;
|
| 3286 |
|
|
if ((MEM_P (operand)
|
| 3287 |
|
|
/* If IND_LEVELS, find_reloads_address won't reload a
|
| 3288 |
|
|
pseudo that didn't get a hard reg, so we have to
|
| 3289 |
|
|
reject that case. */
|
| 3290 |
|
|
&& ((ind_levels ? offsettable_memref_p (operand)
|
| 3291 |
|
|
: offsettable_nonstrict_memref_p (operand))
|
| 3292 |
|
|
/* A reloaded address is offsettable because it is now
|
| 3293 |
|
|
just a simple register indirect. */
|
| 3294 |
|
|
|| address_reloaded[i] == 1))
|
| 3295 |
|
|
|| (REG_P (operand)
|
| 3296 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER
|
| 3297 |
|
|
&& reg_renumber[REGNO (operand)] < 0
|
| 3298 |
|
|
/* If reg_equiv_address is nonzero, we will be
|
| 3299 |
|
|
loading it into a register; hence it will be
|
| 3300 |
|
|
offsettable, but we cannot say that reg_equiv_mem
|
| 3301 |
|
|
is offsettable without checking. */
|
| 3302 |
|
|
&& ((reg_equiv_mem[REGNO (operand)] != 0
|
| 3303 |
|
|
&& offsettable_memref_p (reg_equiv_mem[REGNO (operand)]))
|
| 3304 |
|
|
|| (reg_equiv_address[REGNO (operand)] != 0))))
|
| 3305 |
|
|
win = 1;
|
| 3306 |
|
|
if (CONST_POOL_OK_P (operand)
|
| 3307 |
|
|
|| MEM_P (operand))
|
| 3308 |
|
|
badop = 0;
|
| 3309 |
|
|
constmemok = 1;
|
| 3310 |
|
|
offmemok = 1;
|
| 3311 |
|
|
break;
|
| 3312 |
|
|
|
| 3313 |
|
|
case '&':
|
| 3314 |
|
|
/* Output operand that is stored before the need for the
|
| 3315 |
|
|
input operands (and their index registers) is over. */
|
| 3316 |
|
|
earlyclobber = 1, this_earlyclobber = 1;
|
| 3317 |
|
|
break;
|
| 3318 |
|
|
|
| 3319 |
|
|
case 'E':
|
| 3320 |
|
|
case 'F':
|
| 3321 |
|
|
if (GET_CODE (operand) == CONST_DOUBLE
|
| 3322 |
|
|
|| (GET_CODE (operand) == CONST_VECTOR
|
| 3323 |
|
|
&& (GET_MODE_CLASS (GET_MODE (operand))
|
| 3324 |
|
|
== MODE_VECTOR_FLOAT)))
|
| 3325 |
|
|
win = 1;
|
| 3326 |
|
|
break;
|
| 3327 |
|
|
|
| 3328 |
|
|
case 'G':
|
| 3329 |
|
|
case 'H':
|
| 3330 |
|
|
if (GET_CODE (operand) == CONST_DOUBLE
|
| 3331 |
|
|
&& CONST_DOUBLE_OK_FOR_CONSTRAINT_P (operand, c, p))
|
| 3332 |
|
|
win = 1;
|
| 3333 |
|
|
break;
|
| 3334 |
|
|
|
| 3335 |
|
|
case 's':
|
| 3336 |
|
|
if (CONST_INT_P (operand)
|
| 3337 |
|
|
|| (GET_CODE (operand) == CONST_DOUBLE
|
| 3338 |
|
|
&& GET_MODE (operand) == VOIDmode))
|
| 3339 |
|
|
break;
|
| 3340 |
|
|
case 'i':
|
| 3341 |
|
|
if (CONSTANT_P (operand)
|
| 3342 |
|
|
&& (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)))
|
| 3343 |
|
|
win = 1;
|
| 3344 |
|
|
break;
|
| 3345 |
|
|
|
| 3346 |
|
|
case 'n':
|
| 3347 |
|
|
if (CONST_INT_P (operand)
|
| 3348 |
|
|
|| (GET_CODE (operand) == CONST_DOUBLE
|
| 3349 |
|
|
&& GET_MODE (operand) == VOIDmode))
|
| 3350 |
|
|
win = 1;
|
| 3351 |
|
|
break;
|
| 3352 |
|
|
|
| 3353 |
|
|
case 'I':
|
| 3354 |
|
|
case 'J':
|
| 3355 |
|
|
case 'K':
|
| 3356 |
|
|
case 'L':
|
| 3357 |
|
|
case 'M':
|
| 3358 |
|
|
case 'N':
|
| 3359 |
|
|
case 'O':
|
| 3360 |
|
|
case 'P':
|
| 3361 |
|
|
if (CONST_INT_P (operand)
|
| 3362 |
|
|
&& CONST_OK_FOR_CONSTRAINT_P (INTVAL (operand), c, p))
|
| 3363 |
|
|
win = 1;
|
| 3364 |
|
|
break;
|
| 3365 |
|
|
|
| 3366 |
|
|
case 'X':
|
| 3367 |
|
|
force_reload = 0;
|
| 3368 |
|
|
win = 1;
|
| 3369 |
|
|
break;
|
| 3370 |
|
|
|
| 3371 |
|
|
case 'g':
|
| 3372 |
|
|
if (! force_reload
|
| 3373 |
|
|
/* A PLUS is never a valid operand, but reload can make
|
| 3374 |
|
|
it from a register when eliminating registers. */
|
| 3375 |
|
|
&& GET_CODE (operand) != PLUS
|
| 3376 |
|
|
/* A SCRATCH is not a valid operand. */
|
| 3377 |
|
|
&& GET_CODE (operand) != SCRATCH
|
| 3378 |
|
|
&& (! CONSTANT_P (operand)
|
| 3379 |
|
|
|| ! flag_pic
|
| 3380 |
|
|
|| LEGITIMATE_PIC_OPERAND_P (operand))
|
| 3381 |
|
|
&& (GENERAL_REGS == ALL_REGS
|
| 3382 |
|
|
|| !REG_P (operand)
|
| 3383 |
|
|
|| (REGNO (operand) >= FIRST_PSEUDO_REGISTER
|
| 3384 |
|
|
&& reg_renumber[REGNO (operand)] < 0)))
|
| 3385 |
|
|
win = 1;
|
| 3386 |
|
|
/* Drop through into 'r' case. */
|
| 3387 |
|
|
|
| 3388 |
|
|
case 'r':
|
| 3389 |
|
|
this_alternative[i]
|
| 3390 |
|
|
= reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];
|
| 3391 |
|
|
goto reg;
|
| 3392 |
|
|
|
| 3393 |
|
|
default:
|
| 3394 |
|
|
if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS)
|
| 3395 |
|
|
{
|
| 3396 |
|
|
#ifdef EXTRA_CONSTRAINT_STR
|
| 3397 |
|
|
if (EXTRA_MEMORY_CONSTRAINT (c, p))
|
| 3398 |
|
|
{
|
| 3399 |
|
|
if (force_reload)
|
| 3400 |
|
|
break;
|
| 3401 |
|
|
if (EXTRA_CONSTRAINT_STR (operand, c, p))
|
| 3402 |
|
|
win = 1;
|
| 3403 |
|
|
/* If the address was already reloaded,
|
| 3404 |
|
|
we win as well. */
|
| 3405 |
|
|
else if (MEM_P (operand)
|
| 3406 |
|
|
&& address_reloaded[i] == 1)
|
| 3407 |
|
|
win = 1;
|
| 3408 |
|
|
/* Likewise if the address will be reloaded because
|
| 3409 |
|
|
reg_equiv_address is nonzero. For reg_equiv_mem
|
| 3410 |
|
|
we have to check. */
|
| 3411 |
|
|
else if (REG_P (operand)
|
| 3412 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER
|
| 3413 |
|
|
&& reg_renumber[REGNO (operand)] < 0
|
| 3414 |
|
|
&& ((reg_equiv_mem[REGNO (operand)] != 0
|
| 3415 |
|
|
&& EXTRA_CONSTRAINT_STR (reg_equiv_mem[REGNO (operand)], c, p))
|
| 3416 |
|
|
|| (reg_equiv_address[REGNO (operand)] != 0)))
|
| 3417 |
|
|
win = 1;
|
| 3418 |
|
|
|
| 3419 |
|
|
/* If we didn't already win, we can reload
|
| 3420 |
|
|
constants via force_const_mem, and other
|
| 3421 |
|
|
MEMs by reloading the address like for 'o'. */
|
| 3422 |
|
|
if (CONST_POOL_OK_P (operand)
|
| 3423 |
|
|
|| MEM_P (operand))
|
| 3424 |
|
|
badop = 0;
|
| 3425 |
|
|
constmemok = 1;
|
| 3426 |
|
|
offmemok = 1;
|
| 3427 |
|
|
break;
|
| 3428 |
|
|
}
|
| 3429 |
|
|
if (EXTRA_ADDRESS_CONSTRAINT (c, p))
|
| 3430 |
|
|
{
|
| 3431 |
|
|
if (EXTRA_CONSTRAINT_STR (operand, c, p))
|
| 3432 |
|
|
win = 1;
|
| 3433 |
|
|
|
| 3434 |
|
|
/* If we didn't already win, we can reload
|
| 3435 |
|
|
the address into a base register. */
|
| 3436 |
|
|
this_alternative[i] = base_reg_class (VOIDmode,
|
| 3437 |
|
|
ADDRESS,
|
| 3438 |
|
|
SCRATCH);
|
| 3439 |
|
|
badop = 0;
|
| 3440 |
|
|
break;
|
| 3441 |
|
|
}
|
| 3442 |
|
|
|
| 3443 |
|
|
if (EXTRA_CONSTRAINT_STR (operand, c, p))
|
| 3444 |
|
|
win = 1;
|
| 3445 |
|
|
#endif
|
| 3446 |
|
|
break;
|
| 3447 |
|
|
}
|
| 3448 |
|
|
|
| 3449 |
|
|
this_alternative[i]
|
| 3450 |
|
|
= (reg_class_subunion
|
| 3451 |
|
|
[this_alternative[i]]
|
| 3452 |
|
|
[(int) REG_CLASS_FROM_CONSTRAINT (c, p)]);
|
| 3453 |
|
|
reg:
|
| 3454 |
|
|
if (GET_MODE (operand) == BLKmode)
|
| 3455 |
|
|
break;
|
| 3456 |
|
|
winreg = 1;
|
| 3457 |
|
|
if (REG_P (operand)
|
| 3458 |
|
|
&& reg_fits_class_p (operand, this_alternative[i],
|
| 3459 |
|
|
offset, GET_MODE (recog_data.operand[i])))
|
| 3460 |
|
|
win = 1;
|
| 3461 |
|
|
break;
|
| 3462 |
|
|
}
|
| 3463 |
|
|
while ((p += len), c);
|
| 3464 |
|
|
|
| 3465 |
|
|
constraints[i] = p;
|
| 3466 |
|
|
|
| 3467 |
|
|
/* If this operand could be handled with a reg,
|
| 3468 |
|
|
and some reg is allowed, then this operand can be handled. */
|
| 3469 |
|
|
if (winreg && this_alternative[i] != NO_REGS)
|
| 3470 |
|
|
badop = 0;
|
| 3471 |
|
|
|
| 3472 |
|
|
/* Record which operands fit this alternative. */
|
| 3473 |
|
|
this_alternative_earlyclobber[i] = earlyclobber;
|
| 3474 |
|
|
if (win && ! force_reload)
|
| 3475 |
|
|
this_alternative_win[i] = 1;
|
| 3476 |
|
|
else if (did_match && ! force_reload)
|
| 3477 |
|
|
this_alternative_match_win[i] = 1;
|
| 3478 |
|
|
else
|
| 3479 |
|
|
{
|
| 3480 |
|
|
int const_to_mem = 0;
|
| 3481 |
|
|
|
| 3482 |
|
|
this_alternative_offmemok[i] = offmemok;
|
| 3483 |
|
|
losers++;
|
| 3484 |
|
|
if (badop)
|
| 3485 |
|
|
bad = 1;
|
| 3486 |
|
|
/* Alternative loses if it has no regs for a reg operand. */
|
| 3487 |
|
|
if (REG_P (operand)
|
| 3488 |
|
|
&& this_alternative[i] == NO_REGS
|
| 3489 |
|
|
&& this_alternative_matches[i] < 0)
|
| 3490 |
|
|
bad = 1;
|
| 3491 |
|
|
|
| 3492 |
|
|
/* If this is a constant that is reloaded into the desired
|
| 3493 |
|
|
class by copying it to memory first, count that as another
|
| 3494 |
|
|
reload. This is consistent with other code and is
|
| 3495 |
|
|
required to avoid choosing another alternative when
|
| 3496 |
|
|
the constant is moved into memory by this function on
|
| 3497 |
|
|
an early reload pass. Note that the test here is
|
| 3498 |
|
|
precisely the same as in the code below that calls
|
| 3499 |
|
|
force_const_mem. */
|
| 3500 |
|
|
if (CONST_POOL_OK_P (operand)
|
| 3501 |
|
|
&& ((PREFERRED_RELOAD_CLASS (operand, this_alternative[i])
|
| 3502 |
|
|
== NO_REGS)
|
| 3503 |
|
|
|| no_input_reloads)
|
| 3504 |
|
|
&& operand_mode[i] != VOIDmode)
|
| 3505 |
|
|
{
|
| 3506 |
|
|
const_to_mem = 1;
|
| 3507 |
|
|
if (this_alternative[i] != NO_REGS)
|
| 3508 |
|
|
losers++;
|
| 3509 |
|
|
}
|
| 3510 |
|
|
|
| 3511 |
|
|
/* Alternative loses if it requires a type of reload not
|
| 3512 |
|
|
permitted for this insn. We can always reload SCRATCH
|
| 3513 |
|
|
and objects with a REG_UNUSED note. */
|
| 3514 |
|
|
if (GET_CODE (operand) != SCRATCH
|
| 3515 |
|
|
&& modified[i] != RELOAD_READ && no_output_reloads
|
| 3516 |
|
|
&& ! find_reg_note (insn, REG_UNUSED, operand))
|
| 3517 |
|
|
bad = 1;
|
| 3518 |
|
|
else if (modified[i] != RELOAD_WRITE && no_input_reloads
|
| 3519 |
|
|
&& ! const_to_mem)
|
| 3520 |
|
|
bad = 1;
|
| 3521 |
|
|
|
| 3522 |
|
|
/* If we can't reload this value at all, reject this
|
| 3523 |
|
|
alternative. Note that we could also lose due to
|
| 3524 |
|
|
LIMIT_RELOAD_CLASS, but we don't check that
|
| 3525 |
|
|
here. */
|
| 3526 |
|
|
|
| 3527 |
|
|
if (! CONSTANT_P (operand) && this_alternative[i] != NO_REGS)
|
| 3528 |
|
|
{
|
| 3529 |
|
|
if (PREFERRED_RELOAD_CLASS (operand, this_alternative[i])
|
| 3530 |
|
|
== NO_REGS)
|
| 3531 |
|
|
reject = 600;
|
| 3532 |
|
|
|
| 3533 |
|
|
#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
|
| 3534 |
|
|
if (operand_type[i] == RELOAD_FOR_OUTPUT
|
| 3535 |
|
|
&& (PREFERRED_OUTPUT_RELOAD_CLASS (operand,
|
| 3536 |
|
|
this_alternative[i])
|
| 3537 |
|
|
== NO_REGS))
|
| 3538 |
|
|
reject = 600;
|
| 3539 |
|
|
#endif
|
| 3540 |
|
|
}
|
| 3541 |
|
|
|
| 3542 |
|
|
/* We prefer to reload pseudos over reloading other things,
|
| 3543 |
|
|
since such reloads may be able to be eliminated later.
|
| 3544 |
|
|
If we are reloading a SCRATCH, we won't be generating any
|
| 3545 |
|
|
insns, just using a register, so it is also preferred.
|
| 3546 |
|
|
So bump REJECT in other cases. Don't do this in the
|
| 3547 |
|
|
case where we are forcing a constant into memory and
|
| 3548 |
|
|
it will then win since we don't want to have a different
|
| 3549 |
|
|
alternative match then. */
|
| 3550 |
|
|
if (! (REG_P (operand)
|
| 3551 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER)
|
| 3552 |
|
|
&& GET_CODE (operand) != SCRATCH
|
| 3553 |
|
|
&& ! (const_to_mem && constmemok))
|
| 3554 |
|
|
reject += 2;
|
| 3555 |
|
|
|
| 3556 |
|
|
/* Input reloads can be inherited more often than output
|
| 3557 |
|
|
reloads can be removed, so penalize output reloads. */
|
| 3558 |
|
|
if (operand_type[i] != RELOAD_FOR_INPUT
|
| 3559 |
|
|
&& GET_CODE (operand) != SCRATCH)
|
| 3560 |
|
|
reject++;
|
| 3561 |
|
|
}
|
| 3562 |
|
|
|
| 3563 |
|
|
/* If this operand is a pseudo register that didn't get a hard
|
| 3564 |
|
|
reg and this alternative accepts some register, see if the
|
| 3565 |
|
|
class that we want is a subset of the preferred class for this
|
| 3566 |
|
|
register. If not, but it intersects that class, use the
|
| 3567 |
|
|
preferred class instead. If it does not intersect the preferred
|
| 3568 |
|
|
class, show that usage of this alternative should be discouraged;
|
| 3569 |
|
|
it will be discouraged more still if the register is `preferred
|
| 3570 |
|
|
or nothing'. We do this because it increases the chance of
|
| 3571 |
|
|
reusing our spill register in a later insn and avoiding a pair
|
| 3572 |
|
|
of memory stores and loads.
|
| 3573 |
|
|
|
| 3574 |
|
|
Don't bother with this if this alternative will accept this
|
| 3575 |
|
|
operand.
|
| 3576 |
|
|
|
| 3577 |
|
|
Don't do this for a multiword operand, since it is only a
|
| 3578 |
|
|
small win and has the risk of requiring more spill registers,
|
| 3579 |
|
|
which could cause a large loss.
|
| 3580 |
|
|
|
| 3581 |
|
|
Don't do this if the preferred class has only one register
|
| 3582 |
|
|
because we might otherwise exhaust the class. */
|
| 3583 |
|
|
|
| 3584 |
|
|
if (! win && ! did_match
|
| 3585 |
|
|
&& this_alternative[i] != NO_REGS
|
| 3586 |
|
|
&& GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
|
| 3587 |
|
|
&& reg_class_size [(int) preferred_class[i]] > 0
|
| 3588 |
|
|
&& ! SMALL_REGISTER_CLASS_P (preferred_class[i]))
|
| 3589 |
|
|
{
|
| 3590 |
|
|
if (! reg_class_subset_p (this_alternative[i],
|
| 3591 |
|
|
preferred_class[i]))
|
| 3592 |
|
|
{
|
| 3593 |
|
|
/* Since we don't have a way of forming the intersection,
|
| 3594 |
|
|
we just do something special if the preferred class
|
| 3595 |
|
|
is a subset of the class we have; that's the most
|
| 3596 |
|
|
common case anyway. */
|
| 3597 |
|
|
if (reg_class_subset_p (preferred_class[i],
|
| 3598 |
|
|
this_alternative[i]))
|
| 3599 |
|
|
this_alternative[i] = preferred_class[i];
|
| 3600 |
|
|
else
|
| 3601 |
|
|
reject += (2 + 2 * pref_or_nothing[i]);
|
| 3602 |
|
|
}
|
| 3603 |
|
|
}
|
| 3604 |
|
|
}
|
| 3605 |
|
|
|
| 3606 |
|
|
/* Now see if any output operands that are marked "earlyclobber"
|
| 3607 |
|
|
in this alternative conflict with any input operands
|
| 3608 |
|
|
or any memory addresses. */
|
| 3609 |
|
|
|
| 3610 |
|
|
for (i = 0; i < noperands; i++)
|
| 3611 |
|
|
if (this_alternative_earlyclobber[i]
|
| 3612 |
|
|
&& (this_alternative_win[i] || this_alternative_match_win[i]))
|
| 3613 |
|
|
{
|
| 3614 |
|
|
struct decomposition early_data;
|
| 3615 |
|
|
|
| 3616 |
|
|
early_data = decompose (recog_data.operand[i]);
|
| 3617 |
|
|
|
| 3618 |
|
|
gcc_assert (modified[i] != RELOAD_READ);
|
| 3619 |
|
|
|
| 3620 |
|
|
if (this_alternative[i] == NO_REGS)
|
| 3621 |
|
|
{
|
| 3622 |
|
|
this_alternative_earlyclobber[i] = 0;
|
| 3623 |
|
|
gcc_assert (this_insn_is_asm);
|
| 3624 |
|
|
error_for_asm (this_insn,
|
| 3625 |
|
|
"%<&%> constraint used with no register class");
|
| 3626 |
|
|
}
|
| 3627 |
|
|
|
| 3628 |
|
|
for (j = 0; j < noperands; j++)
|
| 3629 |
|
|
/* Is this an input operand or a memory ref? */
|
| 3630 |
|
|
if ((MEM_P (recog_data.operand[j])
|
| 3631 |
|
|
|| modified[j] != RELOAD_WRITE)
|
| 3632 |
|
|
&& j != i
|
| 3633 |
|
|
/* Ignore things like match_operator operands. */
|
| 3634 |
|
|
&& *recog_data.constraints[j] != 0
|
| 3635 |
|
|
/* Don't count an input operand that is constrained to match
|
| 3636 |
|
|
the early clobber operand. */
|
| 3637 |
|
|
&& ! (this_alternative_matches[j] == i
|
| 3638 |
|
|
&& rtx_equal_p (recog_data.operand[i],
|
| 3639 |
|
|
recog_data.operand[j]))
|
| 3640 |
|
|
/* Is it altered by storing the earlyclobber operand? */
|
| 3641 |
|
|
&& !immune_p (recog_data.operand[j], recog_data.operand[i],
|
| 3642 |
|
|
early_data))
|
| 3643 |
|
|
{
|
| 3644 |
|
|
/* If the output is in a non-empty few-regs class,
|
| 3645 |
|
|
it's costly to reload it, so reload the input instead. */
|
| 3646 |
|
|
if (SMALL_REGISTER_CLASS_P (this_alternative[i])
|
| 3647 |
|
|
&& (REG_P (recog_data.operand[j])
|
| 3648 |
|
|
|| GET_CODE (recog_data.operand[j]) == SUBREG))
|
| 3649 |
|
|
{
|
| 3650 |
|
|
losers++;
|
| 3651 |
|
|
this_alternative_win[j] = 0;
|
| 3652 |
|
|
this_alternative_match_win[j] = 0;
|
| 3653 |
|
|
}
|
| 3654 |
|
|
else
|
| 3655 |
|
|
break;
|
| 3656 |
|
|
}
|
| 3657 |
|
|
/* If an earlyclobber operand conflicts with something,
|
| 3658 |
|
|
it must be reloaded, so request this and count the cost. */
|
| 3659 |
|
|
if (j != noperands)
|
| 3660 |
|
|
{
|
| 3661 |
|
|
losers++;
|
| 3662 |
|
|
this_alternative_win[i] = 0;
|
| 3663 |
|
|
this_alternative_match_win[j] = 0;
|
| 3664 |
|
|
for (j = 0; j < noperands; j++)
|
| 3665 |
|
|
if (this_alternative_matches[j] == i
|
| 3666 |
|
|
&& this_alternative_match_win[j])
|
| 3667 |
|
|
{
|
| 3668 |
|
|
this_alternative_win[j] = 0;
|
| 3669 |
|
|
this_alternative_match_win[j] = 0;
|
| 3670 |
|
|
losers++;
|
| 3671 |
|
|
}
|
| 3672 |
|
|
}
|
| 3673 |
|
|
}
|
| 3674 |
|
|
|
| 3675 |
|
|
/* If one alternative accepts all the operands, no reload required,
|
| 3676 |
|
|
choose that alternative; don't consider the remaining ones. */
|
| 3677 |
|
|
if (losers == 0)
|
| 3678 |
|
|
{
|
| 3679 |
|
|
/* Unswap these so that they are never swapped at `finish'. */
|
| 3680 |
|
|
if (commutative >= 0)
|
| 3681 |
|
|
{
|
| 3682 |
|
|
recog_data.operand[commutative] = substed_operand[commutative];
|
| 3683 |
|
|
recog_data.operand[commutative + 1]
|
| 3684 |
|
|
= substed_operand[commutative + 1];
|
| 3685 |
|
|
}
|
| 3686 |
|
|
for (i = 0; i < noperands; i++)
|
| 3687 |
|
|
{
|
| 3688 |
|
|
goal_alternative_win[i] = this_alternative_win[i];
|
| 3689 |
|
|
goal_alternative_match_win[i] = this_alternative_match_win[i];
|
| 3690 |
|
|
goal_alternative[i] = this_alternative[i];
|
| 3691 |
|
|
goal_alternative_offmemok[i] = this_alternative_offmemok[i];
|
| 3692 |
|
|
goal_alternative_matches[i] = this_alternative_matches[i];
|
| 3693 |
|
|
goal_alternative_earlyclobber[i]
|
| 3694 |
|
|
= this_alternative_earlyclobber[i];
|
| 3695 |
|
|
}
|
| 3696 |
|
|
goal_alternative_number = this_alternative_number;
|
| 3697 |
|
|
goal_alternative_swapped = swapped;
|
| 3698 |
|
|
goal_earlyclobber = this_earlyclobber;
|
| 3699 |
|
|
goto finish;
|
| 3700 |
|
|
}
|
| 3701 |
|
|
|
| 3702 |
|
|
/* REJECT, set by the ! and ? constraint characters and when a register
|
| 3703 |
|
|
would be reloaded into a non-preferred class, discourages the use of
|
| 3704 |
|
|
this alternative for a reload goal. REJECT is incremented by six
|
| 3705 |
|
|
for each ? and two for each non-preferred class. */
|
| 3706 |
|
|
losers = losers * 6 + reject;
|
| 3707 |
|
|
|
| 3708 |
|
|
/* If this alternative can be made to work by reloading,
|
| 3709 |
|
|
and it needs less reloading than the others checked so far,
|
| 3710 |
|
|
record it as the chosen goal for reloading. */
|
| 3711 |
|
|
if (! bad)
|
| 3712 |
|
|
{
|
| 3713 |
|
|
bool change_p = false;
|
| 3714 |
|
|
int small_class_operands_num = 0;
|
| 3715 |
|
|
|
| 3716 |
|
|
if (best >= losers)
|
| 3717 |
|
|
{
|
| 3718 |
|
|
for (i = 0; i < noperands; i++)
|
| 3719 |
|
|
small_class_operands_num
|
| 3720 |
|
|
+= SMALL_REGISTER_CLASS_P (this_alternative[i]) ? 1 : 0;
|
| 3721 |
|
|
if (best > losers
|
| 3722 |
|
|
|| (best == losers
|
| 3723 |
|
|
/* If the cost of the reloads is the same,
|
| 3724 |
|
|
prefer alternative which requires minimal
|
| 3725 |
|
|
number of small register classes for the
|
| 3726 |
|
|
operands. This improves chances of reloads
|
| 3727 |
|
|
for insn requiring small register
|
| 3728 |
|
|
classes. */
|
| 3729 |
|
|
&& (small_class_operands_num
|
| 3730 |
|
|
< best_small_class_operands_num)))
|
| 3731 |
|
|
change_p = true;
|
| 3732 |
|
|
}
|
| 3733 |
|
|
if (change_p)
|
| 3734 |
|
|
{
|
| 3735 |
|
|
for (i = 0; i < noperands; i++)
|
| 3736 |
|
|
{
|
| 3737 |
|
|
goal_alternative[i] = this_alternative[i];
|
| 3738 |
|
|
goal_alternative_win[i] = this_alternative_win[i];
|
| 3739 |
|
|
goal_alternative_match_win[i]
|
| 3740 |
|
|
= this_alternative_match_win[i];
|
| 3741 |
|
|
goal_alternative_offmemok[i]
|
| 3742 |
|
|
= this_alternative_offmemok[i];
|
| 3743 |
|
|
goal_alternative_matches[i] = this_alternative_matches[i];
|
| 3744 |
|
|
goal_alternative_earlyclobber[i]
|
| 3745 |
|
|
= this_alternative_earlyclobber[i];
|
| 3746 |
|
|
}
|
| 3747 |
|
|
goal_alternative_swapped = swapped;
|
| 3748 |
|
|
best = losers;
|
| 3749 |
|
|
best_small_class_operands_num = small_class_operands_num;
|
| 3750 |
|
|
goal_alternative_number = this_alternative_number;
|
| 3751 |
|
|
goal_earlyclobber = this_earlyclobber;
|
| 3752 |
|
|
}
|
| 3753 |
|
|
}
|
| 3754 |
|
|
}
|
| 3755 |
|
|
|
| 3756 |
|
|
/* If insn is commutative (it's safe to exchange a certain pair of operands)
|
| 3757 |
|
|
then we need to try each alternative twice,
|
| 3758 |
|
|
the second time matching those two operands
|
| 3759 |
|
|
as if we had exchanged them.
|
| 3760 |
|
|
To do this, really exchange them in operands.
|
| 3761 |
|
|
|
| 3762 |
|
|
If we have just tried the alternatives the second time,
|
| 3763 |
|
|
return operands to normal and drop through. */
|
| 3764 |
|
|
|
| 3765 |
|
|
if (commutative >= 0)
|
| 3766 |
|
|
{
|
| 3767 |
|
|
swapped = !swapped;
|
| 3768 |
|
|
if (swapped)
|
| 3769 |
|
|
{
|
| 3770 |
|
|
enum reg_class tclass;
|
| 3771 |
|
|
int t;
|
| 3772 |
|
|
|
| 3773 |
|
|
recog_data.operand[commutative] = substed_operand[commutative + 1];
|
| 3774 |
|
|
recog_data.operand[commutative + 1] = substed_operand[commutative];
|
| 3775 |
|
|
/* Swap the duplicates too. */
|
| 3776 |
|
|
for (i = 0; i < recog_data.n_dups; i++)
|
| 3777 |
|
|
if (recog_data.dup_num[i] == commutative
|
| 3778 |
|
|
|| recog_data.dup_num[i] == commutative + 1)
|
| 3779 |
|
|
*recog_data.dup_loc[i]
|
| 3780 |
|
|
= recog_data.operand[(int) recog_data.dup_num[i]];
|
| 3781 |
|
|
|
| 3782 |
|
|
tclass = preferred_class[commutative];
|
| 3783 |
|
|
preferred_class[commutative] = preferred_class[commutative + 1];
|
| 3784 |
|
|
preferred_class[commutative + 1] = tclass;
|
| 3785 |
|
|
|
| 3786 |
|
|
t = pref_or_nothing[commutative];
|
| 3787 |
|
|
pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
|
| 3788 |
|
|
pref_or_nothing[commutative + 1] = t;
|
| 3789 |
|
|
|
| 3790 |
|
|
t = address_reloaded[commutative];
|
| 3791 |
|
|
address_reloaded[commutative] = address_reloaded[commutative + 1];
|
| 3792 |
|
|
address_reloaded[commutative + 1] = t;
|
| 3793 |
|
|
|
| 3794 |
|
|
memcpy (constraints, recog_data.constraints,
|
| 3795 |
|
|
noperands * sizeof (const char *));
|
| 3796 |
|
|
goto try_swapped;
|
| 3797 |
|
|
}
|
| 3798 |
|
|
else
|
| 3799 |
|
|
{
|
| 3800 |
|
|
recog_data.operand[commutative] = substed_operand[commutative];
|
| 3801 |
|
|
recog_data.operand[commutative + 1]
|
| 3802 |
|
|
= substed_operand[commutative + 1];
|
| 3803 |
|
|
/* Unswap the duplicates too. */
|
| 3804 |
|
|
for (i = 0; i < recog_data.n_dups; i++)
|
| 3805 |
|
|
if (recog_data.dup_num[i] == commutative
|
| 3806 |
|
|
|| recog_data.dup_num[i] == commutative + 1)
|
| 3807 |
|
|
*recog_data.dup_loc[i]
|
| 3808 |
|
|
= recog_data.operand[(int) recog_data.dup_num[i]];
|
| 3809 |
|
|
}
|
| 3810 |
|
|
}
|
| 3811 |
|
|
|
| 3812 |
|
|
/* The operands don't meet the constraints.
|
| 3813 |
|
|
goal_alternative describes the alternative
|
| 3814 |
|
|
that we could reach by reloading the fewest operands.
|
| 3815 |
|
|
Reload so as to fit it. */
|
| 3816 |
|
|
|
| 3817 |
|
|
if (best == MAX_RECOG_OPERANDS * 2 + 600)
|
| 3818 |
|
|
{
|
| 3819 |
|
|
/* No alternative works with reloads?? */
|
| 3820 |
|
|
if (insn_code_number >= 0)
|
| 3821 |
|
|
fatal_insn ("unable to generate reloads for:", insn);
|
| 3822 |
|
|
error_for_asm (insn, "inconsistent operand constraints in an %<asm%>");
|
| 3823 |
|
|
/* Avoid further trouble with this insn. */
|
| 3824 |
|
|
PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
|
| 3825 |
|
|
n_reloads = 0;
|
| 3826 |
|
|
return 0;
|
| 3827 |
|
|
}
|
| 3828 |
|
|
|
| 3829 |
|
|
/* Jump to `finish' from above if all operands are valid already.
|
| 3830 |
|
|
In that case, goal_alternative_win is all 1. */
|
| 3831 |
|
|
finish:
|
| 3832 |
|
|
|
| 3833 |
|
|
/* Right now, for any pair of operands I and J that are required to match,
|
| 3834 |
|
|
with I < J,
|
| 3835 |
|
|
goal_alternative_matches[J] is I.
|
| 3836 |
|
|
Set up goal_alternative_matched as the inverse function:
|
| 3837 |
|
|
goal_alternative_matched[I] = J. */
|
| 3838 |
|
|
|
| 3839 |
|
|
for (i = 0; i < noperands; i++)
|
| 3840 |
|
|
goal_alternative_matched[i] = -1;
|
| 3841 |
|
|
|
| 3842 |
|
|
for (i = 0; i < noperands; i++)
|
| 3843 |
|
|
if (! goal_alternative_win[i]
|
| 3844 |
|
|
&& goal_alternative_matches[i] >= 0)
|
| 3845 |
|
|
goal_alternative_matched[goal_alternative_matches[i]] = i;
|
| 3846 |
|
|
|
| 3847 |
|
|
for (i = 0; i < noperands; i++)
|
| 3848 |
|
|
goal_alternative_win[i] |= goal_alternative_match_win[i];
|
| 3849 |
|
|
|
| 3850 |
|
|
/* If the best alternative is with operands 1 and 2 swapped,
|
| 3851 |
|
|
consider them swapped before reporting the reloads. Update the
|
| 3852 |
|
|
operand numbers of any reloads already pushed. */
|
| 3853 |
|
|
|
| 3854 |
|
|
if (goal_alternative_swapped)
|
| 3855 |
|
|
{
|
| 3856 |
|
|
rtx tem;
|
| 3857 |
|
|
|
| 3858 |
|
|
tem = substed_operand[commutative];
|
| 3859 |
|
|
substed_operand[commutative] = substed_operand[commutative + 1];
|
| 3860 |
|
|
substed_operand[commutative + 1] = tem;
|
| 3861 |
|
|
tem = recog_data.operand[commutative];
|
| 3862 |
|
|
recog_data.operand[commutative] = recog_data.operand[commutative + 1];
|
| 3863 |
|
|
recog_data.operand[commutative + 1] = tem;
|
| 3864 |
|
|
tem = *recog_data.operand_loc[commutative];
|
| 3865 |
|
|
*recog_data.operand_loc[commutative]
|
| 3866 |
|
|
= *recog_data.operand_loc[commutative + 1];
|
| 3867 |
|
|
*recog_data.operand_loc[commutative + 1] = tem;
|
| 3868 |
|
|
|
| 3869 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 3870 |
|
|
{
|
| 3871 |
|
|
if (rld[i].opnum == commutative)
|
| 3872 |
|
|
rld[i].opnum = commutative + 1;
|
| 3873 |
|
|
else if (rld[i].opnum == commutative + 1)
|
| 3874 |
|
|
rld[i].opnum = commutative;
|
| 3875 |
|
|
}
|
| 3876 |
|
|
}
|
| 3877 |
|
|
|
| 3878 |
|
|
for (i = 0; i < noperands; i++)
|
| 3879 |
|
|
{
|
| 3880 |
|
|
operand_reloadnum[i] = -1;
|
| 3881 |
|
|
|
| 3882 |
|
|
/* If this is an earlyclobber operand, we need to widen the scope.
|
| 3883 |
|
|
The reload must remain valid from the start of the insn being
|
| 3884 |
|
|
reloaded until after the operand is stored into its destination.
|
| 3885 |
|
|
We approximate this with RELOAD_OTHER even though we know that we
|
| 3886 |
|
|
do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads.
|
| 3887 |
|
|
|
| 3888 |
|
|
One special case that is worth checking is when we have an
|
| 3889 |
|
|
output that is earlyclobber but isn't used past the insn (typically
|
| 3890 |
|
|
a SCRATCH). In this case, we only need have the reload live
|
| 3891 |
|
|
through the insn itself, but not for any of our input or output
|
| 3892 |
|
|
reloads.
|
| 3893 |
|
|
But we must not accidentally narrow the scope of an existing
|
| 3894 |
|
|
RELOAD_OTHER reload - leave these alone.
|
| 3895 |
|
|
|
| 3896 |
|
|
In any case, anything needed to address this operand can remain
|
| 3897 |
|
|
however they were previously categorized. */
|
| 3898 |
|
|
|
| 3899 |
|
|
if (goal_alternative_earlyclobber[i] && operand_type[i] != RELOAD_OTHER)
|
| 3900 |
|
|
operand_type[i]
|
| 3901 |
|
|
= (find_reg_note (insn, REG_UNUSED, recog_data.operand[i])
|
| 3902 |
|
|
? RELOAD_FOR_INSN : RELOAD_OTHER);
|
| 3903 |
|
|
}
|
| 3904 |
|
|
|
| 3905 |
|
|
/* Any constants that aren't allowed and can't be reloaded
|
| 3906 |
|
|
into registers are here changed into memory references. */
|
| 3907 |
|
|
for (i = 0; i < noperands; i++)
|
| 3908 |
|
|
if (! goal_alternative_win[i])
|
| 3909 |
|
|
{
|
| 3910 |
|
|
rtx op = recog_data.operand[i];
|
| 3911 |
|
|
rtx subreg = NULL_RTX;
|
| 3912 |
|
|
rtx plus = NULL_RTX;
|
| 3913 |
|
|
enum machine_mode mode = operand_mode[i];
|
| 3914 |
|
|
|
| 3915 |
|
|
/* Reloads of SUBREGs of CONSTANT RTXs are handled later in
|
| 3916 |
|
|
push_reload so we have to let them pass here. */
|
| 3917 |
|
|
if (GET_CODE (op) == SUBREG)
|
| 3918 |
|
|
{
|
| 3919 |
|
|
subreg = op;
|
| 3920 |
|
|
op = SUBREG_REG (op);
|
| 3921 |
|
|
mode = GET_MODE (op);
|
| 3922 |
|
|
}
|
| 3923 |
|
|
|
| 3924 |
|
|
if (GET_CODE (op) == PLUS)
|
| 3925 |
|
|
{
|
| 3926 |
|
|
plus = op;
|
| 3927 |
|
|
op = XEXP (op, 1);
|
| 3928 |
|
|
}
|
| 3929 |
|
|
|
| 3930 |
|
|
if (CONST_POOL_OK_P (op)
|
| 3931 |
|
|
&& ((PREFERRED_RELOAD_CLASS (op,
|
| 3932 |
|
|
(enum reg_class) goal_alternative[i])
|
| 3933 |
|
|
== NO_REGS)
|
| 3934 |
|
|
|| no_input_reloads)
|
| 3935 |
|
|
&& mode != VOIDmode)
|
| 3936 |
|
|
{
|
| 3937 |
|
|
int this_address_reloaded;
|
| 3938 |
|
|
rtx tem = force_const_mem (mode, op);
|
| 3939 |
|
|
|
| 3940 |
|
|
/* If we stripped a SUBREG or a PLUS above add it back. */
|
| 3941 |
|
|
if (plus != NULL_RTX)
|
| 3942 |
|
|
tem = gen_rtx_PLUS (mode, XEXP (plus, 0), tem);
|
| 3943 |
|
|
|
| 3944 |
|
|
if (subreg != NULL_RTX)
|
| 3945 |
|
|
tem = gen_rtx_SUBREG (operand_mode[i], tem, SUBREG_BYTE (subreg));
|
| 3946 |
|
|
|
| 3947 |
|
|
this_address_reloaded = 0;
|
| 3948 |
|
|
substed_operand[i] = recog_data.operand[i]
|
| 3949 |
|
|
= find_reloads_toplev (tem, i, address_type[i], ind_levels,
|
| 3950 |
|
|
0, insn, &this_address_reloaded);
|
| 3951 |
|
|
|
| 3952 |
|
|
/* If the alternative accepts constant pool refs directly
|
| 3953 |
|
|
there will be no reload needed at all. */
|
| 3954 |
|
|
if (plus == NULL_RTX
|
| 3955 |
|
|
&& subreg == NULL_RTX
|
| 3956 |
|
|
&& alternative_allows_const_pool_ref (this_address_reloaded == 0
|
| 3957 |
|
|
? substed_operand[i]
|
| 3958 |
|
|
: NULL,
|
| 3959 |
|
|
recog_data.constraints[i],
|
| 3960 |
|
|
goal_alternative_number))
|
| 3961 |
|
|
goal_alternative_win[i] = 1;
|
| 3962 |
|
|
}
|
| 3963 |
|
|
}
|
| 3964 |
|
|
|
| 3965 |
|
|
/* Record the values of the earlyclobber operands for the caller. */
|
| 3966 |
|
|
if (goal_earlyclobber)
|
| 3967 |
|
|
for (i = 0; i < noperands; i++)
|
| 3968 |
|
|
if (goal_alternative_earlyclobber[i])
|
| 3969 |
|
|
reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i];
|
| 3970 |
|
|
|
| 3971 |
|
|
/* Now record reloads for all the operands that need them. */
|
| 3972 |
|
|
for (i = 0; i < noperands; i++)
|
| 3973 |
|
|
if (! goal_alternative_win[i])
|
| 3974 |
|
|
{
|
| 3975 |
|
|
/* Operands that match previous ones have already been handled. */
|
| 3976 |
|
|
if (goal_alternative_matches[i] >= 0)
|
| 3977 |
|
|
;
|
| 3978 |
|
|
/* Handle an operand with a nonoffsettable address
|
| 3979 |
|
|
appearing where an offsettable address will do
|
| 3980 |
|
|
by reloading the address into a base register.
|
| 3981 |
|
|
|
| 3982 |
|
|
??? We can also do this when the operand is a register and
|
| 3983 |
|
|
reg_equiv_mem is not offsettable, but this is a bit tricky,
|
| 3984 |
|
|
so we don't bother with it. It may not be worth doing. */
|
| 3985 |
|
|
else if (goal_alternative_matched[i] == -1
|
| 3986 |
|
|
&& goal_alternative_offmemok[i]
|
| 3987 |
|
|
&& MEM_P (recog_data.operand[i]))
|
| 3988 |
|
|
{
|
| 3989 |
|
|
/* If the address to be reloaded is a VOIDmode constant,
|
| 3990 |
|
|
use the default address mode as mode of the reload register,
|
| 3991 |
|
|
as would have been done by find_reloads_address. */
|
| 3992 |
|
|
enum machine_mode address_mode;
|
| 3993 |
|
|
address_mode = GET_MODE (XEXP (recog_data.operand[i], 0));
|
| 3994 |
|
|
if (address_mode == VOIDmode)
|
| 3995 |
|
|
{
|
| 3996 |
|
|
addr_space_t as = MEM_ADDR_SPACE (recog_data.operand[i]);
|
| 3997 |
|
|
address_mode = targetm.addr_space.address_mode (as);
|
| 3998 |
|
|
}
|
| 3999 |
|
|
|
| 4000 |
|
|
operand_reloadnum[i]
|
| 4001 |
|
|
= push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX,
|
| 4002 |
|
|
&XEXP (recog_data.operand[i], 0), (rtx*) 0,
|
| 4003 |
|
|
base_reg_class (VOIDmode, MEM, SCRATCH),
|
| 4004 |
|
|
address_mode,
|
| 4005 |
|
|
VOIDmode, 0, 0, i, RELOAD_FOR_INPUT);
|
| 4006 |
|
|
rld[operand_reloadnum[i]].inc
|
| 4007 |
|
|
= GET_MODE_SIZE (GET_MODE (recog_data.operand[i]));
|
| 4008 |
|
|
|
| 4009 |
|
|
/* If this operand is an output, we will have made any
|
| 4010 |
|
|
reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but
|
| 4011 |
|
|
now we are treating part of the operand as an input, so
|
| 4012 |
|
|
we must change these to RELOAD_FOR_INPUT_ADDRESS. */
|
| 4013 |
|
|
|
| 4014 |
|
|
if (modified[i] == RELOAD_WRITE)
|
| 4015 |
|
|
{
|
| 4016 |
|
|
for (j = 0; j < n_reloads; j++)
|
| 4017 |
|
|
{
|
| 4018 |
|
|
if (rld[j].opnum == i)
|
| 4019 |
|
|
{
|
| 4020 |
|
|
if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS)
|
| 4021 |
|
|
rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS;
|
| 4022 |
|
|
else if (rld[j].when_needed
|
| 4023 |
|
|
== RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4024 |
|
|
rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS;
|
| 4025 |
|
|
}
|
| 4026 |
|
|
}
|
| 4027 |
|
|
}
|
| 4028 |
|
|
}
|
| 4029 |
|
|
else if (goal_alternative_matched[i] == -1)
|
| 4030 |
|
|
{
|
| 4031 |
|
|
operand_reloadnum[i]
|
| 4032 |
|
|
= push_reload ((modified[i] != RELOAD_WRITE
|
| 4033 |
|
|
? recog_data.operand[i] : 0),
|
| 4034 |
|
|
(modified[i] != RELOAD_READ
|
| 4035 |
|
|
? recog_data.operand[i] : 0),
|
| 4036 |
|
|
(modified[i] != RELOAD_WRITE
|
| 4037 |
|
|
? recog_data.operand_loc[i] : 0),
|
| 4038 |
|
|
(modified[i] != RELOAD_READ
|
| 4039 |
|
|
? recog_data.operand_loc[i] : 0),
|
| 4040 |
|
|
(enum reg_class) goal_alternative[i],
|
| 4041 |
|
|
(modified[i] == RELOAD_WRITE
|
| 4042 |
|
|
? VOIDmode : operand_mode[i]),
|
| 4043 |
|
|
(modified[i] == RELOAD_READ
|
| 4044 |
|
|
? VOIDmode : operand_mode[i]),
|
| 4045 |
|
|
(insn_code_number < 0 ? 0
|
| 4046 |
|
|
: insn_data[insn_code_number].operand[i].strict_low),
|
| 4047 |
|
|
0, i, operand_type[i]);
|
| 4048 |
|
|
}
|
| 4049 |
|
|
/* In a matching pair of operands, one must be input only
|
| 4050 |
|
|
and the other must be output only.
|
| 4051 |
|
|
Pass the input operand as IN and the other as OUT. */
|
| 4052 |
|
|
else if (modified[i] == RELOAD_READ
|
| 4053 |
|
|
&& modified[goal_alternative_matched[i]] == RELOAD_WRITE)
|
| 4054 |
|
|
{
|
| 4055 |
|
|
operand_reloadnum[i]
|
| 4056 |
|
|
= push_reload (recog_data.operand[i],
|
| 4057 |
|
|
recog_data.operand[goal_alternative_matched[i]],
|
| 4058 |
|
|
recog_data.operand_loc[i],
|
| 4059 |
|
|
recog_data.operand_loc[goal_alternative_matched[i]],
|
| 4060 |
|
|
(enum reg_class) goal_alternative[i],
|
| 4061 |
|
|
operand_mode[i],
|
| 4062 |
|
|
operand_mode[goal_alternative_matched[i]],
|
| 4063 |
|
|
0, 0, i, RELOAD_OTHER);
|
| 4064 |
|
|
operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
|
| 4065 |
|
|
}
|
| 4066 |
|
|
else if (modified[i] == RELOAD_WRITE
|
| 4067 |
|
|
&& modified[goal_alternative_matched[i]] == RELOAD_READ)
|
| 4068 |
|
|
{
|
| 4069 |
|
|
operand_reloadnum[goal_alternative_matched[i]]
|
| 4070 |
|
|
= push_reload (recog_data.operand[goal_alternative_matched[i]],
|
| 4071 |
|
|
recog_data.operand[i],
|
| 4072 |
|
|
recog_data.operand_loc[goal_alternative_matched[i]],
|
| 4073 |
|
|
recog_data.operand_loc[i],
|
| 4074 |
|
|
(enum reg_class) goal_alternative[i],
|
| 4075 |
|
|
operand_mode[goal_alternative_matched[i]],
|
| 4076 |
|
|
operand_mode[i],
|
| 4077 |
|
|
0, 0, i, RELOAD_OTHER);
|
| 4078 |
|
|
operand_reloadnum[i] = output_reloadnum;
|
| 4079 |
|
|
}
|
| 4080 |
|
|
else
|
| 4081 |
|
|
{
|
| 4082 |
|
|
gcc_assert (insn_code_number < 0);
|
| 4083 |
|
|
error_for_asm (insn, "inconsistent operand constraints "
|
| 4084 |
|
|
"in an %<asm%>");
|
| 4085 |
|
|
/* Avoid further trouble with this insn. */
|
| 4086 |
|
|
PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
|
| 4087 |
|
|
n_reloads = 0;
|
| 4088 |
|
|
return 0;
|
| 4089 |
|
|
}
|
| 4090 |
|
|
}
|
| 4091 |
|
|
else if (goal_alternative_matched[i] < 0
|
| 4092 |
|
|
&& goal_alternative_matches[i] < 0
|
| 4093 |
|
|
&& address_operand_reloaded[i] != 1
|
| 4094 |
|
|
&& optimize)
|
| 4095 |
|
|
{
|
| 4096 |
|
|
/* For each non-matching operand that's a MEM or a pseudo-register
|
| 4097 |
|
|
that didn't get a hard register, make an optional reload.
|
| 4098 |
|
|
This may get done even if the insn needs no reloads otherwise. */
|
| 4099 |
|
|
|
| 4100 |
|
|
rtx operand = recog_data.operand[i];
|
| 4101 |
|
|
|
| 4102 |
|
|
while (GET_CODE (operand) == SUBREG)
|
| 4103 |
|
|
operand = SUBREG_REG (operand);
|
| 4104 |
|
|
if ((MEM_P (operand)
|
| 4105 |
|
|
|| (REG_P (operand)
|
| 4106 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER))
|
| 4107 |
|
|
/* If this is only for an output, the optional reload would not
|
| 4108 |
|
|
actually cause us to use a register now, just note that
|
| 4109 |
|
|
something is stored here. */
|
| 4110 |
|
|
&& ((enum reg_class) goal_alternative[i] != NO_REGS
|
| 4111 |
|
|
|| modified[i] == RELOAD_WRITE)
|
| 4112 |
|
|
&& ! no_input_reloads
|
| 4113 |
|
|
/* An optional output reload might allow to delete INSN later.
|
| 4114 |
|
|
We mustn't make in-out reloads on insns that are not permitted
|
| 4115 |
|
|
output reloads.
|
| 4116 |
|
|
If this is an asm, we can't delete it; we must not even call
|
| 4117 |
|
|
push_reload for an optional output reload in this case,
|
| 4118 |
|
|
because we can't be sure that the constraint allows a register,
|
| 4119 |
|
|
and push_reload verifies the constraints for asms. */
|
| 4120 |
|
|
&& (modified[i] == RELOAD_READ
|
| 4121 |
|
|
|| (! no_output_reloads && ! this_insn_is_asm)))
|
| 4122 |
|
|
operand_reloadnum[i]
|
| 4123 |
|
|
= push_reload ((modified[i] != RELOAD_WRITE
|
| 4124 |
|
|
? recog_data.operand[i] : 0),
|
| 4125 |
|
|
(modified[i] != RELOAD_READ
|
| 4126 |
|
|
? recog_data.operand[i] : 0),
|
| 4127 |
|
|
(modified[i] != RELOAD_WRITE
|
| 4128 |
|
|
? recog_data.operand_loc[i] : 0),
|
| 4129 |
|
|
(modified[i] != RELOAD_READ
|
| 4130 |
|
|
? recog_data.operand_loc[i] : 0),
|
| 4131 |
|
|
(enum reg_class) goal_alternative[i],
|
| 4132 |
|
|
(modified[i] == RELOAD_WRITE
|
| 4133 |
|
|
? VOIDmode : operand_mode[i]),
|
| 4134 |
|
|
(modified[i] == RELOAD_READ
|
| 4135 |
|
|
? VOIDmode : operand_mode[i]),
|
| 4136 |
|
|
(insn_code_number < 0 ? 0
|
| 4137 |
|
|
: insn_data[insn_code_number].operand[i].strict_low),
|
| 4138 |
|
|
1, i, operand_type[i]);
|
| 4139 |
|
|
/* If a memory reference remains (either as a MEM or a pseudo that
|
| 4140 |
|
|
did not get a hard register), yet we can't make an optional
|
| 4141 |
|
|
reload, check if this is actually a pseudo register reference;
|
| 4142 |
|
|
we then need to emit a USE and/or a CLOBBER so that reload
|
| 4143 |
|
|
inheritance will do the right thing. */
|
| 4144 |
|
|
else if (replace
|
| 4145 |
|
|
&& (MEM_P (operand)
|
| 4146 |
|
|
|| (REG_P (operand)
|
| 4147 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER
|
| 4148 |
|
|
&& reg_renumber [REGNO (operand)] < 0)))
|
| 4149 |
|
|
{
|
| 4150 |
|
|
operand = *recog_data.operand_loc[i];
|
| 4151 |
|
|
|
| 4152 |
|
|
while (GET_CODE (operand) == SUBREG)
|
| 4153 |
|
|
operand = SUBREG_REG (operand);
|
| 4154 |
|
|
if (REG_P (operand))
|
| 4155 |
|
|
{
|
| 4156 |
|
|
if (modified[i] != RELOAD_WRITE)
|
| 4157 |
|
|
/* We mark the USE with QImode so that we recognize
|
| 4158 |
|
|
it as one that can be safely deleted at the end
|
| 4159 |
|
|
of reload. */
|
| 4160 |
|
|
PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand),
|
| 4161 |
|
|
insn), QImode);
|
| 4162 |
|
|
if (modified[i] != RELOAD_READ)
|
| 4163 |
|
|
emit_insn_after (gen_clobber (operand), insn);
|
| 4164 |
|
|
}
|
| 4165 |
|
|
}
|
| 4166 |
|
|
}
|
| 4167 |
|
|
else if (goal_alternative_matches[i] >= 0
|
| 4168 |
|
|
&& goal_alternative_win[goal_alternative_matches[i]]
|
| 4169 |
|
|
&& modified[i] == RELOAD_READ
|
| 4170 |
|
|
&& modified[goal_alternative_matches[i]] == RELOAD_WRITE
|
| 4171 |
|
|
&& ! no_input_reloads && ! no_output_reloads
|
| 4172 |
|
|
&& optimize)
|
| 4173 |
|
|
{
|
| 4174 |
|
|
/* Similarly, make an optional reload for a pair of matching
|
| 4175 |
|
|
objects that are in MEM or a pseudo that didn't get a hard reg. */
|
| 4176 |
|
|
|
| 4177 |
|
|
rtx operand = recog_data.operand[i];
|
| 4178 |
|
|
|
| 4179 |
|
|
while (GET_CODE (operand) == SUBREG)
|
| 4180 |
|
|
operand = SUBREG_REG (operand);
|
| 4181 |
|
|
if ((MEM_P (operand)
|
| 4182 |
|
|
|| (REG_P (operand)
|
| 4183 |
|
|
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER))
|
| 4184 |
|
|
&& ((enum reg_class) goal_alternative[goal_alternative_matches[i]]
|
| 4185 |
|
|
!= NO_REGS))
|
| 4186 |
|
|
operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]]
|
| 4187 |
|
|
= push_reload (recog_data.operand[goal_alternative_matches[i]],
|
| 4188 |
|
|
recog_data.operand[i],
|
| 4189 |
|
|
recog_data.operand_loc[goal_alternative_matches[i]],
|
| 4190 |
|
|
recog_data.operand_loc[i],
|
| 4191 |
|
|
(enum reg_class) goal_alternative[goal_alternative_matches[i]],
|
| 4192 |
|
|
operand_mode[goal_alternative_matches[i]],
|
| 4193 |
|
|
operand_mode[i],
|
| 4194 |
|
|
0, 1, goal_alternative_matches[i], RELOAD_OTHER);
|
| 4195 |
|
|
}
|
| 4196 |
|
|
|
| 4197 |
|
|
/* Perform whatever substitutions on the operands we are supposed
|
| 4198 |
|
|
to make due to commutativity or replacement of registers
|
| 4199 |
|
|
with equivalent constants or memory slots. */
|
| 4200 |
|
|
|
| 4201 |
|
|
for (i = 0; i < noperands; i++)
|
| 4202 |
|
|
{
|
| 4203 |
|
|
/* We only do this on the last pass through reload, because it is
|
| 4204 |
|
|
possible for some data (like reg_equiv_address) to be changed during
|
| 4205 |
|
|
later passes. Moreover, we lose the opportunity to get a useful
|
| 4206 |
|
|
reload_{in,out}_reg when we do these replacements. */
|
| 4207 |
|
|
|
| 4208 |
|
|
if (replace)
|
| 4209 |
|
|
{
|
| 4210 |
|
|
rtx substitution = substed_operand[i];
|
| 4211 |
|
|
|
| 4212 |
|
|
*recog_data.operand_loc[i] = substitution;
|
| 4213 |
|
|
|
| 4214 |
|
|
/* If we're replacing an operand with a LABEL_REF, we need to
|
| 4215 |
|
|
make sure that there's a REG_LABEL_OPERAND note attached to
|
| 4216 |
|
|
this instruction. */
|
| 4217 |
|
|
if (GET_CODE (substitution) == LABEL_REF
|
| 4218 |
|
|
&& !find_reg_note (insn, REG_LABEL_OPERAND,
|
| 4219 |
|
|
XEXP (substitution, 0))
|
| 4220 |
|
|
/* For a JUMP_P, if it was a branch target it must have
|
| 4221 |
|
|
already been recorded as such. */
|
| 4222 |
|
|
&& (!JUMP_P (insn)
|
| 4223 |
|
|
|| !label_is_jump_target_p (XEXP (substitution, 0),
|
| 4224 |
|
|
insn)))
|
| 4225 |
|
|
add_reg_note (insn, REG_LABEL_OPERAND, XEXP (substitution, 0));
|
| 4226 |
|
|
}
|
| 4227 |
|
|
else
|
| 4228 |
|
|
retval |= (substed_operand[i] != *recog_data.operand_loc[i]);
|
| 4229 |
|
|
}
|
| 4230 |
|
|
|
| 4231 |
|
|
/* If this insn pattern contains any MATCH_DUP's, make sure that
|
| 4232 |
|
|
they will be substituted if the operands they match are substituted.
|
| 4233 |
|
|
Also do now any substitutions we already did on the operands.
|
| 4234 |
|
|
|
| 4235 |
|
|
Don't do this if we aren't making replacements because we might be
|
| 4236 |
|
|
propagating things allocated by frame pointer elimination into places
|
| 4237 |
|
|
it doesn't expect. */
|
| 4238 |
|
|
|
| 4239 |
|
|
if (insn_code_number >= 0 && replace)
|
| 4240 |
|
|
for (i = insn_data[insn_code_number].n_dups - 1; i >= 0; i--)
|
| 4241 |
|
|
{
|
| 4242 |
|
|
int opno = recog_data.dup_num[i];
|
| 4243 |
|
|
*recog_data.dup_loc[i] = *recog_data.operand_loc[opno];
|
| 4244 |
|
|
dup_replacements (recog_data.dup_loc[i], recog_data.operand_loc[opno]);
|
| 4245 |
|
|
}
|
| 4246 |
|
|
|
| 4247 |
|
|
#if 0
|
| 4248 |
|
|
/* This loses because reloading of prior insns can invalidate the equivalence
|
| 4249 |
|
|
(or at least find_equiv_reg isn't smart enough to find it any more),
|
| 4250 |
|
|
causing this insn to need more reload regs than it needed before.
|
| 4251 |
|
|
It may be too late to make the reload regs available.
|
| 4252 |
|
|
Now this optimization is done safely in choose_reload_regs. */
|
| 4253 |
|
|
|
| 4254 |
|
|
/* For each reload of a reg into some other class of reg,
|
| 4255 |
|
|
search for an existing equivalent reg (same value now) in the right class.
|
| 4256 |
|
|
We can use it as long as we don't need to change its contents. */
|
| 4257 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4258 |
|
|
if (rld[i].reg_rtx == 0
|
| 4259 |
|
|
&& rld[i].in != 0
|
| 4260 |
|
|
&& REG_P (rld[i].in)
|
| 4261 |
|
|
&& rld[i].out == 0)
|
| 4262 |
|
|
{
|
| 4263 |
|
|
rld[i].reg_rtx
|
| 4264 |
|
|
= find_equiv_reg (rld[i].in, insn, rld[i].rclass, -1,
|
| 4265 |
|
|
static_reload_reg_p, 0, rld[i].inmode);
|
| 4266 |
|
|
/* Prevent generation of insn to load the value
|
| 4267 |
|
|
because the one we found already has the value. */
|
| 4268 |
|
|
if (rld[i].reg_rtx)
|
| 4269 |
|
|
rld[i].in = rld[i].reg_rtx;
|
| 4270 |
|
|
}
|
| 4271 |
|
|
#endif
|
| 4272 |
|
|
|
| 4273 |
|
|
/* If we detected error and replaced asm instruction by USE, forget about the
|
| 4274 |
|
|
reloads. */
|
| 4275 |
|
|
if (GET_CODE (PATTERN (insn)) == USE
|
| 4276 |
|
|
&& CONST_INT_P (XEXP (PATTERN (insn), 0)))
|
| 4277 |
|
|
n_reloads = 0;
|
| 4278 |
|
|
|
| 4279 |
|
|
/* Perhaps an output reload can be combined with another
|
| 4280 |
|
|
to reduce needs by one. */
|
| 4281 |
|
|
if (!goal_earlyclobber)
|
| 4282 |
|
|
combine_reloads ();
|
| 4283 |
|
|
|
| 4284 |
|
|
/* If we have a pair of reloads for parts of an address, they are reloading
|
| 4285 |
|
|
the same object, the operands themselves were not reloaded, and they
|
| 4286 |
|
|
are for two operands that are supposed to match, merge the reloads and
|
| 4287 |
|
|
change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */
|
| 4288 |
|
|
|
| 4289 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4290 |
|
|
{
|
| 4291 |
|
|
int k;
|
| 4292 |
|
|
|
| 4293 |
|
|
for (j = i + 1; j < n_reloads; j++)
|
| 4294 |
|
|
if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
|
| 4295 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
|
| 4296 |
|
|
|| rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
|
| 4297 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4298 |
|
|
&& (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
|
| 4299 |
|
|
|| rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
|
| 4300 |
|
|
|| rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS
|
| 4301 |
|
|
|| rld[j].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4302 |
|
|
&& rtx_equal_p (rld[i].in, rld[j].in)
|
| 4303 |
|
|
&& (operand_reloadnum[rld[i].opnum] < 0
|
| 4304 |
|
|
|| rld[operand_reloadnum[rld[i].opnum]].optional)
|
| 4305 |
|
|
&& (operand_reloadnum[rld[j].opnum] < 0
|
| 4306 |
|
|
|| rld[operand_reloadnum[rld[j].opnum]].optional)
|
| 4307 |
|
|
&& (goal_alternative_matches[rld[i].opnum] == rld[j].opnum
|
| 4308 |
|
|
|| (goal_alternative_matches[rld[j].opnum]
|
| 4309 |
|
|
== rld[i].opnum)))
|
| 4310 |
|
|
{
|
| 4311 |
|
|
for (k = 0; k < n_replacements; k++)
|
| 4312 |
|
|
if (replacements[k].what == j)
|
| 4313 |
|
|
replacements[k].what = i;
|
| 4314 |
|
|
|
| 4315 |
|
|
if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
|
| 4316 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4317 |
|
|
rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR;
|
| 4318 |
|
|
else
|
| 4319 |
|
|
rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS;
|
| 4320 |
|
|
rld[j].in = 0;
|
| 4321 |
|
|
}
|
| 4322 |
|
|
}
|
| 4323 |
|
|
|
| 4324 |
|
|
/* Scan all the reloads and update their type.
|
| 4325 |
|
|
If a reload is for the address of an operand and we didn't reload
|
| 4326 |
|
|
that operand, change the type. Similarly, change the operand number
|
| 4327 |
|
|
of a reload when two operands match. If a reload is optional, treat it
|
| 4328 |
|
|
as though the operand isn't reloaded.
|
| 4329 |
|
|
|
| 4330 |
|
|
??? This latter case is somewhat odd because if we do the optional
|
| 4331 |
|
|
reload, it means the object is hanging around. Thus we need only
|
| 4332 |
|
|
do the address reload if the optional reload was NOT done.
|
| 4333 |
|
|
|
| 4334 |
|
|
Change secondary reloads to be the address type of their operand, not
|
| 4335 |
|
|
the normal type.
|
| 4336 |
|
|
|
| 4337 |
|
|
If an operand's reload is now RELOAD_OTHER, change any
|
| 4338 |
|
|
RELOAD_FOR_INPUT_ADDRESS reloads of that operand to
|
| 4339 |
|
|
RELOAD_FOR_OTHER_ADDRESS. */
|
| 4340 |
|
|
|
| 4341 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4342 |
|
|
{
|
| 4343 |
|
|
if (rld[i].secondary_p
|
| 4344 |
|
|
&& rld[i].when_needed == operand_type[rld[i].opnum])
|
| 4345 |
|
|
rld[i].when_needed = address_type[rld[i].opnum];
|
| 4346 |
|
|
|
| 4347 |
|
|
if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
|
| 4348 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
|
| 4349 |
|
|
|| rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
|
| 4350 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4351 |
|
|
&& (operand_reloadnum[rld[i].opnum] < 0
|
| 4352 |
|
|
|| rld[operand_reloadnum[rld[i].opnum]].optional))
|
| 4353 |
|
|
{
|
| 4354 |
|
|
/* If we have a secondary reload to go along with this reload,
|
| 4355 |
|
|
change its type to RELOAD_FOR_OPADDR_ADDR. */
|
| 4356 |
|
|
|
| 4357 |
|
|
if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
|
| 4358 |
|
|
|| rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
|
| 4359 |
|
|
&& rld[i].secondary_in_reload != -1)
|
| 4360 |
|
|
{
|
| 4361 |
|
|
int secondary_in_reload = rld[i].secondary_in_reload;
|
| 4362 |
|
|
|
| 4363 |
|
|
rld[secondary_in_reload].when_needed = RELOAD_FOR_OPADDR_ADDR;
|
| 4364 |
|
|
|
| 4365 |
|
|
/* If there's a tertiary reload we have to change it also. */
|
| 4366 |
|
|
if (secondary_in_reload > 0
|
| 4367 |
|
|
&& rld[secondary_in_reload].secondary_in_reload != -1)
|
| 4368 |
|
|
rld[rld[secondary_in_reload].secondary_in_reload].when_needed
|
| 4369 |
|
|
= RELOAD_FOR_OPADDR_ADDR;
|
| 4370 |
|
|
}
|
| 4371 |
|
|
|
| 4372 |
|
|
if ((rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
|
| 4373 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4374 |
|
|
&& rld[i].secondary_out_reload != -1)
|
| 4375 |
|
|
{
|
| 4376 |
|
|
int secondary_out_reload = rld[i].secondary_out_reload;
|
| 4377 |
|
|
|
| 4378 |
|
|
rld[secondary_out_reload].when_needed = RELOAD_FOR_OPADDR_ADDR;
|
| 4379 |
|
|
|
| 4380 |
|
|
/* If there's a tertiary reload we have to change it also. */
|
| 4381 |
|
|
if (secondary_out_reload
|
| 4382 |
|
|
&& rld[secondary_out_reload].secondary_out_reload != -1)
|
| 4383 |
|
|
rld[rld[secondary_out_reload].secondary_out_reload].when_needed
|
| 4384 |
|
|
= RELOAD_FOR_OPADDR_ADDR;
|
| 4385 |
|
|
}
|
| 4386 |
|
|
|
| 4387 |
|
|
if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
|
| 4388 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
|
| 4389 |
|
|
rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR;
|
| 4390 |
|
|
else
|
| 4391 |
|
|
rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS;
|
| 4392 |
|
|
}
|
| 4393 |
|
|
|
| 4394 |
|
|
if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
|
| 4395 |
|
|
|| rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
|
| 4396 |
|
|
&& operand_reloadnum[rld[i].opnum] >= 0
|
| 4397 |
|
|
&& (rld[operand_reloadnum[rld[i].opnum]].when_needed
|
| 4398 |
|
|
== RELOAD_OTHER))
|
| 4399 |
|
|
rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS;
|
| 4400 |
|
|
|
| 4401 |
|
|
if (goal_alternative_matches[rld[i].opnum] >= 0)
|
| 4402 |
|
|
rld[i].opnum = goal_alternative_matches[rld[i].opnum];
|
| 4403 |
|
|
}
|
| 4404 |
|
|
|
| 4405 |
|
|
/* Scan all the reloads, and check for RELOAD_FOR_OPERAND_ADDRESS reloads.
|
| 4406 |
|
|
If we have more than one, then convert all RELOAD_FOR_OPADDR_ADDR
|
| 4407 |
|
|
reloads to RELOAD_FOR_OPERAND_ADDRESS reloads.
|
| 4408 |
|
|
|
| 4409 |
|
|
choose_reload_regs assumes that RELOAD_FOR_OPADDR_ADDR reloads never
|
| 4410 |
|
|
conflict with RELOAD_FOR_OPERAND_ADDRESS reloads. This is true for a
|
| 4411 |
|
|
single pair of RELOAD_FOR_OPADDR_ADDR/RELOAD_FOR_OPERAND_ADDRESS reloads.
|
| 4412 |
|
|
However, if there is more than one RELOAD_FOR_OPERAND_ADDRESS reload,
|
| 4413 |
|
|
then a RELOAD_FOR_OPADDR_ADDR reload conflicts with all
|
| 4414 |
|
|
RELOAD_FOR_OPERAND_ADDRESS reloads other than the one that uses it.
|
| 4415 |
|
|
This is complicated by the fact that a single operand can have more
|
| 4416 |
|
|
than one RELOAD_FOR_OPERAND_ADDRESS reload. It is very difficult to fix
|
| 4417 |
|
|
choose_reload_regs without affecting code quality, and cases that
|
| 4418 |
|
|
actually fail are extremely rare, so it turns out to be better to fix
|
| 4419 |
|
|
the problem here by not generating cases that choose_reload_regs will
|
| 4420 |
|
|
fail for. */
|
| 4421 |
|
|
/* There is a similar problem with RELOAD_FOR_INPUT_ADDRESS /
|
| 4422 |
|
|
RELOAD_FOR_OUTPUT_ADDRESS when there is more than one of a kind for
|
| 4423 |
|
|
a single operand.
|
| 4424 |
|
|
We can reduce the register pressure by exploiting that a
|
| 4425 |
|
|
RELOAD_FOR_X_ADDR_ADDR that precedes all RELOAD_FOR_X_ADDRESS reloads
|
| 4426 |
|
|
does not conflict with any of them, if it is only used for the first of
|
| 4427 |
|
|
the RELOAD_FOR_X_ADDRESS reloads. */
|
| 4428 |
|
|
{
|
| 4429 |
|
|
int first_op_addr_num = -2;
|
| 4430 |
|
|
int first_inpaddr_num[MAX_RECOG_OPERANDS];
|
| 4431 |
|
|
int first_outpaddr_num[MAX_RECOG_OPERANDS];
|
| 4432 |
|
|
int need_change = 0;
|
| 4433 |
|
|
/* We use last_op_addr_reload and the contents of the above arrays
|
| 4434 |
|
|
first as flags - -2 means no instance encountered, -1 means exactly
|
| 4435 |
|
|
one instance encountered.
|
| 4436 |
|
|
If more than one instance has been encountered, we store the reload
|
| 4437 |
|
|
number of the first reload of the kind in question; reload numbers
|
| 4438 |
|
|
are known to be non-negative. */
|
| 4439 |
|
|
for (i = 0; i < noperands; i++)
|
| 4440 |
|
|
first_inpaddr_num[i] = first_outpaddr_num[i] = -2;
|
| 4441 |
|
|
for (i = n_reloads - 1; i >= 0; i--)
|
| 4442 |
|
|
{
|
| 4443 |
|
|
switch (rld[i].when_needed)
|
| 4444 |
|
|
{
|
| 4445 |
|
|
case RELOAD_FOR_OPERAND_ADDRESS:
|
| 4446 |
|
|
if (++first_op_addr_num >= 0)
|
| 4447 |
|
|
{
|
| 4448 |
|
|
first_op_addr_num = i;
|
| 4449 |
|
|
need_change = 1;
|
| 4450 |
|
|
}
|
| 4451 |
|
|
break;
|
| 4452 |
|
|
case RELOAD_FOR_INPUT_ADDRESS:
|
| 4453 |
|
|
if (++first_inpaddr_num[rld[i].opnum] >= 0)
|
| 4454 |
|
|
{
|
| 4455 |
|
|
first_inpaddr_num[rld[i].opnum] = i;
|
| 4456 |
|
|
need_change = 1;
|
| 4457 |
|
|
}
|
| 4458 |
|
|
break;
|
| 4459 |
|
|
case RELOAD_FOR_OUTPUT_ADDRESS:
|
| 4460 |
|
|
if (++first_outpaddr_num[rld[i].opnum] >= 0)
|
| 4461 |
|
|
{
|
| 4462 |
|
|
first_outpaddr_num[rld[i].opnum] = i;
|
| 4463 |
|
|
need_change = 1;
|
| 4464 |
|
|
}
|
| 4465 |
|
|
break;
|
| 4466 |
|
|
default:
|
| 4467 |
|
|
break;
|
| 4468 |
|
|
}
|
| 4469 |
|
|
}
|
| 4470 |
|
|
|
| 4471 |
|
|
if (need_change)
|
| 4472 |
|
|
{
|
| 4473 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4474 |
|
|
{
|
| 4475 |
|
|
int first_num;
|
| 4476 |
|
|
enum reload_type type;
|
| 4477 |
|
|
|
| 4478 |
|
|
switch (rld[i].when_needed)
|
| 4479 |
|
|
{
|
| 4480 |
|
|
case RELOAD_FOR_OPADDR_ADDR:
|
| 4481 |
|
|
first_num = first_op_addr_num;
|
| 4482 |
|
|
type = RELOAD_FOR_OPERAND_ADDRESS;
|
| 4483 |
|
|
break;
|
| 4484 |
|
|
case RELOAD_FOR_INPADDR_ADDRESS:
|
| 4485 |
|
|
first_num = first_inpaddr_num[rld[i].opnum];
|
| 4486 |
|
|
type = RELOAD_FOR_INPUT_ADDRESS;
|
| 4487 |
|
|
break;
|
| 4488 |
|
|
case RELOAD_FOR_OUTADDR_ADDRESS:
|
| 4489 |
|
|
first_num = first_outpaddr_num[rld[i].opnum];
|
| 4490 |
|
|
type = RELOAD_FOR_OUTPUT_ADDRESS;
|
| 4491 |
|
|
break;
|
| 4492 |
|
|
default:
|
| 4493 |
|
|
continue;
|
| 4494 |
|
|
}
|
| 4495 |
|
|
if (first_num < 0)
|
| 4496 |
|
|
continue;
|
| 4497 |
|
|
else if (i > first_num)
|
| 4498 |
|
|
rld[i].when_needed = type;
|
| 4499 |
|
|
else
|
| 4500 |
|
|
{
|
| 4501 |
|
|
/* Check if the only TYPE reload that uses reload I is
|
| 4502 |
|
|
reload FIRST_NUM. */
|
| 4503 |
|
|
for (j = n_reloads - 1; j > first_num; j--)
|
| 4504 |
|
|
{
|
| 4505 |
|
|
if (rld[j].when_needed == type
|
| 4506 |
|
|
&& (rld[i].secondary_p
|
| 4507 |
|
|
? rld[j].secondary_in_reload == i
|
| 4508 |
|
|
: reg_mentioned_p (rld[i].in, rld[j].in)))
|
| 4509 |
|
|
{
|
| 4510 |
|
|
rld[i].when_needed = type;
|
| 4511 |
|
|
break;
|
| 4512 |
|
|
}
|
| 4513 |
|
|
}
|
| 4514 |
|
|
}
|
| 4515 |
|
|
}
|
| 4516 |
|
|
}
|
| 4517 |
|
|
}
|
| 4518 |
|
|
|
| 4519 |
|
|
/* See if we have any reloads that are now allowed to be merged
|
| 4520 |
|
|
because we've changed when the reload is needed to
|
| 4521 |
|
|
RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only
|
| 4522 |
|
|
check for the most common cases. */
|
| 4523 |
|
|
|
| 4524 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4525 |
|
|
if (rld[i].in != 0 && rld[i].out == 0
|
| 4526 |
|
|
&& (rld[i].when_needed == RELOAD_FOR_OPERAND_ADDRESS
|
| 4527 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OPADDR_ADDR
|
| 4528 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OTHER_ADDRESS))
|
| 4529 |
|
|
for (j = 0; j < n_reloads; j++)
|
| 4530 |
|
|
if (i != j && rld[j].in != 0 && rld[j].out == 0
|
| 4531 |
|
|
&& rld[j].when_needed == rld[i].when_needed
|
| 4532 |
|
|
&& MATCHES (rld[i].in, rld[j].in)
|
| 4533 |
|
|
&& rld[i].rclass == rld[j].rclass
|
| 4534 |
|
|
&& !rld[i].nocombine && !rld[j].nocombine
|
| 4535 |
|
|
&& rld[i].reg_rtx == rld[j].reg_rtx)
|
| 4536 |
|
|
{
|
| 4537 |
|
|
rld[i].opnum = MIN (rld[i].opnum, rld[j].opnum);
|
| 4538 |
|
|
transfer_replacements (i, j);
|
| 4539 |
|
|
rld[j].in = 0;
|
| 4540 |
|
|
}
|
| 4541 |
|
|
|
| 4542 |
|
|
#ifdef HAVE_cc0
|
| 4543 |
|
|
/* If we made any reloads for addresses, see if they violate a
|
| 4544 |
|
|
"no input reloads" requirement for this insn. But loads that we
|
| 4545 |
|
|
do after the insn (such as for output addresses) are fine. */
|
| 4546 |
|
|
if (no_input_reloads)
|
| 4547 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4548 |
|
|
gcc_assert (rld[i].in == 0
|
| 4549 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS
|
| 4550 |
|
|
|| rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS);
|
| 4551 |
|
|
#endif
|
| 4552 |
|
|
|
| 4553 |
|
|
/* Compute reload_mode and reload_nregs. */
|
| 4554 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4555 |
|
|
{
|
| 4556 |
|
|
rld[i].mode
|
| 4557 |
|
|
= (rld[i].inmode == VOIDmode
|
| 4558 |
|
|
|| (GET_MODE_SIZE (rld[i].outmode)
|
| 4559 |
|
|
> GET_MODE_SIZE (rld[i].inmode)))
|
| 4560 |
|
|
? rld[i].outmode : rld[i].inmode;
|
| 4561 |
|
|
|
| 4562 |
|
|
rld[i].nregs = CLASS_MAX_NREGS (rld[i].rclass, rld[i].mode);
|
| 4563 |
|
|
}
|
| 4564 |
|
|
|
| 4565 |
|
|
/* Special case a simple move with an input reload and a
|
| 4566 |
|
|
destination of a hard reg, if the hard reg is ok, use it. */
|
| 4567 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 4568 |
|
|
if (rld[i].when_needed == RELOAD_FOR_INPUT
|
| 4569 |
|
|
&& GET_CODE (PATTERN (insn)) == SET
|
| 4570 |
|
|
&& REG_P (SET_DEST (PATTERN (insn)))
|
| 4571 |
|
|
&& (SET_SRC (PATTERN (insn)) == rld[i].in
|
| 4572 |
|
|
|| SET_SRC (PATTERN (insn)) == rld[i].in_reg)
|
| 4573 |
|
|
&& !elimination_target_reg_p (SET_DEST (PATTERN (insn))))
|
| 4574 |
|
|
{
|
| 4575 |
|
|
rtx dest = SET_DEST (PATTERN (insn));
|
| 4576 |
|
|
unsigned int regno = REGNO (dest);
|
| 4577 |
|
|
|
| 4578 |
|
|
if (regno < FIRST_PSEUDO_REGISTER
|
| 4579 |
|
|
&& TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno)
|
| 4580 |
|
|
&& HARD_REGNO_MODE_OK (regno, rld[i].mode))
|
| 4581 |
|
|
{
|
| 4582 |
|
|
int nr = hard_regno_nregs[regno][rld[i].mode];
|
| 4583 |
|
|
int ok = 1, nri;
|
| 4584 |
|
|
|
| 4585 |
|
|
for (nri = 1; nri < nr; nri ++)
|
| 4586 |
|
|
if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno + nri))
|
| 4587 |
|
|
ok = 0;
|
| 4588 |
|
|
|
| 4589 |
|
|
if (ok)
|
| 4590 |
|
|
rld[i].reg_rtx = dest;
|
| 4591 |
|
|
}
|
| 4592 |
|
|
}
|
| 4593 |
|
|
|
| 4594 |
|
|
return retval;
|
| 4595 |
|
|
}
|
| 4596 |
|
|
|
| 4597 |
|
|
/* Return true if alternative number ALTNUM in constraint-string
|
| 4598 |
|
|
CONSTRAINT is guaranteed to accept a reloaded constant-pool reference.
|
| 4599 |
|
|
MEM gives the reference if it didn't need any reloads, otherwise it
|
| 4600 |
|
|
is null. */
|
| 4601 |
|
|
|
| 4602 |
|
|
static bool
|
| 4603 |
|
|
alternative_allows_const_pool_ref (rtx mem ATTRIBUTE_UNUSED,
|
| 4604 |
|
|
const char *constraint, int altnum)
|
| 4605 |
|
|
{
|
| 4606 |
|
|
int c;
|
| 4607 |
|
|
|
| 4608 |
|
|
/* Skip alternatives before the one requested. */
|
| 4609 |
|
|
while (altnum > 0)
|
| 4610 |
|
|
{
|
| 4611 |
|
|
while (*constraint++ != ',');
|
| 4612 |
|
|
altnum--;
|
| 4613 |
|
|
}
|
| 4614 |
|
|
/* Scan the requested alternative for TARGET_MEM_CONSTRAINT or 'o'.
|
| 4615 |
|
|
If one of them is present, this alternative accepts the result of
|
| 4616 |
|
|
passing a constant-pool reference through find_reloads_toplev.
|
| 4617 |
|
|
|
| 4618 |
|
|
The same is true of extra memory constraints if the address
|
| 4619 |
|
|
was reloaded into a register. However, the target may elect
|
| 4620 |
|
|
to disallow the original constant address, forcing it to be
|
| 4621 |
|
|
reloaded into a register instead. */
|
| 4622 |
|
|
for (; (c = *constraint) && c != ',' && c != '#';
|
| 4623 |
|
|
constraint += CONSTRAINT_LEN (c, constraint))
|
| 4624 |
|
|
{
|
| 4625 |
|
|
if (c == TARGET_MEM_CONSTRAINT || c == 'o')
|
| 4626 |
|
|
return true;
|
| 4627 |
|
|
#ifdef EXTRA_CONSTRAINT_STR
|
| 4628 |
|
|
if (EXTRA_MEMORY_CONSTRAINT (c, constraint)
|
| 4629 |
|
|
&& (mem == NULL || EXTRA_CONSTRAINT_STR (mem, c, constraint)))
|
| 4630 |
|
|
return true;
|
| 4631 |
|
|
#endif
|
| 4632 |
|
|
}
|
| 4633 |
|
|
return false;
|
| 4634 |
|
|
}
|
| 4635 |
|
|
|
| 4636 |
|
|
/* Scan X for memory references and scan the addresses for reloading.
|
| 4637 |
|
|
Also checks for references to "constant" regs that we want to eliminate
|
| 4638 |
|
|
and replaces them with the values they stand for.
|
| 4639 |
|
|
We may alter X destructively if it contains a reference to such.
|
| 4640 |
|
|
If X is just a constant reg, we return the equivalent value
|
| 4641 |
|
|
instead of X.
|
| 4642 |
|
|
|
| 4643 |
|
|
IND_LEVELS says how many levels of indirect addressing this machine
|
| 4644 |
|
|
supports.
|
| 4645 |
|
|
|
| 4646 |
|
|
OPNUM and TYPE identify the purpose of the reload.
|
| 4647 |
|
|
|
| 4648 |
|
|
IS_SET_DEST is true if X is the destination of a SET, which is not
|
| 4649 |
|
|
appropriate to be replaced by a constant.
|
| 4650 |
|
|
|
| 4651 |
|
|
INSN, if nonzero, is the insn in which we do the reload. It is used
|
| 4652 |
|
|
to determine if we may generate output reloads, and where to put USEs
|
| 4653 |
|
|
for pseudos that we have to replace with stack slots.
|
| 4654 |
|
|
|
| 4655 |
|
|
ADDRESS_RELOADED. If nonzero, is a pointer to where we put the
|
| 4656 |
|
|
result of find_reloads_address. */
|
| 4657 |
|
|
|
| 4658 |
|
|
static rtx
|
| 4659 |
|
|
find_reloads_toplev (rtx x, int opnum, enum reload_type type,
|
| 4660 |
|
|
int ind_levels, int is_set_dest, rtx insn,
|
| 4661 |
|
|
int *address_reloaded)
|
| 4662 |
|
|
{
|
| 4663 |
|
|
RTX_CODE code = GET_CODE (x);
|
| 4664 |
|
|
|
| 4665 |
|
|
const char *fmt = GET_RTX_FORMAT (code);
|
| 4666 |
|
|
int i;
|
| 4667 |
|
|
int copied;
|
| 4668 |
|
|
|
| 4669 |
|
|
if (code == REG)
|
| 4670 |
|
|
{
|
| 4671 |
|
|
/* This code is duplicated for speed in find_reloads. */
|
| 4672 |
|
|
int regno = REGNO (x);
|
| 4673 |
|
|
if (reg_equiv_constant[regno] != 0 && !is_set_dest)
|
| 4674 |
|
|
x = reg_equiv_constant[regno];
|
| 4675 |
|
|
#if 0
|
| 4676 |
|
|
/* This creates (subreg (mem...)) which would cause an unnecessary
|
| 4677 |
|
|
reload of the mem. */
|
| 4678 |
|
|
else if (reg_equiv_mem[regno] != 0)
|
| 4679 |
|
|
x = reg_equiv_mem[regno];
|
| 4680 |
|
|
#endif
|
| 4681 |
|
|
else if (reg_equiv_memory_loc[regno]
|
| 4682 |
|
|
&& (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
|
| 4683 |
|
|
{
|
| 4684 |
|
|
rtx mem = make_memloc (x, regno);
|
| 4685 |
|
|
if (reg_equiv_address[regno]
|
| 4686 |
|
|
|| ! rtx_equal_p (mem, reg_equiv_mem[regno]))
|
| 4687 |
|
|
{
|
| 4688 |
|
|
/* If this is not a toplevel operand, find_reloads doesn't see
|
| 4689 |
|
|
this substitution. We have to emit a USE of the pseudo so
|
| 4690 |
|
|
that delete_output_reload can see it. */
|
| 4691 |
|
|
if (replace_reloads && recog_data.operand[opnum] != x)
|
| 4692 |
|
|
/* We mark the USE with QImode so that we recognize it
|
| 4693 |
|
|
as one that can be safely deleted at the end of
|
| 4694 |
|
|
reload. */
|
| 4695 |
|
|
PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn),
|
| 4696 |
|
|
QImode);
|
| 4697 |
|
|
x = mem;
|
| 4698 |
|
|
i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0),
|
| 4699 |
|
|
opnum, type, ind_levels, insn);
|
| 4700 |
|
|
if (!rtx_equal_p (x, mem))
|
| 4701 |
|
|
push_reg_equiv_alt_mem (regno, x);
|
| 4702 |
|
|
if (address_reloaded)
|
| 4703 |
|
|
*address_reloaded = i;
|
| 4704 |
|
|
}
|
| 4705 |
|
|
}
|
| 4706 |
|
|
return x;
|
| 4707 |
|
|
}
|
| 4708 |
|
|
if (code == MEM)
|
| 4709 |
|
|
{
|
| 4710 |
|
|
rtx tem = x;
|
| 4711 |
|
|
|
| 4712 |
|
|
i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
|
| 4713 |
|
|
opnum, type, ind_levels, insn);
|
| 4714 |
|
|
if (address_reloaded)
|
| 4715 |
|
|
*address_reloaded = i;
|
| 4716 |
|
|
|
| 4717 |
|
|
return tem;
|
| 4718 |
|
|
}
|
| 4719 |
|
|
|
| 4720 |
|
|
if (code == SUBREG && REG_P (SUBREG_REG (x)))
|
| 4721 |
|
|
{
|
| 4722 |
|
|
/* Check for SUBREG containing a REG that's equivalent to a
|
| 4723 |
|
|
constant. If the constant has a known value, truncate it
|
| 4724 |
|
|
right now. Similarly if we are extracting a single-word of a
|
| 4725 |
|
|
multi-word constant. If the constant is symbolic, allow it
|
| 4726 |
|
|
to be substituted normally. push_reload will strip the
|
| 4727 |
|
|
subreg later. The constant must not be VOIDmode, because we
|
| 4728 |
|
|
will lose the mode of the register (this should never happen
|
| 4729 |
|
|
because one of the cases above should handle it). */
|
| 4730 |
|
|
|
| 4731 |
|
|
int regno = REGNO (SUBREG_REG (x));
|
| 4732 |
|
|
rtx tem;
|
| 4733 |
|
|
|
| 4734 |
|
|
if (regno >= FIRST_PSEUDO_REGISTER
|
| 4735 |
|
|
&& reg_renumber[regno] < 0
|
| 4736 |
|
|
&& reg_equiv_constant[regno] != 0)
|
| 4737 |
|
|
{
|
| 4738 |
|
|
tem =
|
| 4739 |
|
|
simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
|
| 4740 |
|
|
GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
|
| 4741 |
|
|
gcc_assert (tem);
|
| 4742 |
|
|
if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
|
| 4743 |
|
|
{
|
| 4744 |
|
|
tem = force_const_mem (GET_MODE (x), tem);
|
| 4745 |
|
|
i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
|
| 4746 |
|
|
&XEXP (tem, 0), opnum, type,
|
| 4747 |
|
|
ind_levels, insn);
|
| 4748 |
|
|
if (address_reloaded)
|
| 4749 |
|
|
*address_reloaded = i;
|
| 4750 |
|
|
}
|
| 4751 |
|
|
return tem;
|
| 4752 |
|
|
}
|
| 4753 |
|
|
|
| 4754 |
|
|
/* If the subreg contains a reg that will be converted to a mem,
|
| 4755 |
|
|
convert the subreg to a narrower memref now.
|
| 4756 |
|
|
Otherwise, we would get (subreg (mem ...) ...),
|
| 4757 |
|
|
which would force reload of the mem.
|
| 4758 |
|
|
|
| 4759 |
|
|
We also need to do this if there is an equivalent MEM that is
|
| 4760 |
|
|
not offsettable. In that case, alter_subreg would produce an
|
| 4761 |
|
|
invalid address on big-endian machines.
|
| 4762 |
|
|
|
| 4763 |
|
|
For machines that extend byte loads, we must not reload using
|
| 4764 |
|
|
a wider mode if we have a paradoxical SUBREG. find_reloads will
|
| 4765 |
|
|
force a reload in that case. So we should not do anything here. */
|
| 4766 |
|
|
|
| 4767 |
|
|
if (regno >= FIRST_PSEUDO_REGISTER
|
| 4768 |
|
|
#ifdef LOAD_EXTEND_OP
|
| 4769 |
|
|
&& (GET_MODE_SIZE (GET_MODE (x))
|
| 4770 |
|
|
<= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
|
| 4771 |
|
|
#endif
|
| 4772 |
|
|
&& (reg_equiv_address[regno] != 0
|
| 4773 |
|
|
|| (reg_equiv_mem[regno] != 0
|
| 4774 |
|
|
&& (! strict_memory_address_addr_space_p
|
| 4775 |
|
|
(GET_MODE (x), XEXP (reg_equiv_mem[regno], 0),
|
| 4776 |
|
|
MEM_ADDR_SPACE (reg_equiv_mem[regno]))
|
| 4777 |
|
|
|| ! offsettable_memref_p (reg_equiv_mem[regno])
|
| 4778 |
|
|
|| num_not_at_initial_offset))))
|
| 4779 |
|
|
x = find_reloads_subreg_address (x, 1, opnum, type, ind_levels,
|
| 4780 |
|
|
insn);
|
| 4781 |
|
|
}
|
| 4782 |
|
|
|
| 4783 |
|
|
for (copied = 0, i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 4784 |
|
|
{
|
| 4785 |
|
|
if (fmt[i] == 'e')
|
| 4786 |
|
|
{
|
| 4787 |
|
|
rtx new_part = find_reloads_toplev (XEXP (x, i), opnum, type,
|
| 4788 |
|
|
ind_levels, is_set_dest, insn,
|
| 4789 |
|
|
address_reloaded);
|
| 4790 |
|
|
/* If we have replaced a reg with it's equivalent memory loc -
|
| 4791 |
|
|
that can still be handled here e.g. if it's in a paradoxical
|
| 4792 |
|
|
subreg - we must make the change in a copy, rather than using
|
| 4793 |
|
|
a destructive change. This way, find_reloads can still elect
|
| 4794 |
|
|
not to do the change. */
|
| 4795 |
|
|
if (new_part != XEXP (x, i) && ! CONSTANT_P (new_part) && ! copied)
|
| 4796 |
|
|
{
|
| 4797 |
|
|
x = shallow_copy_rtx (x);
|
| 4798 |
|
|
copied = 1;
|
| 4799 |
|
|
}
|
| 4800 |
|
|
XEXP (x, i) = new_part;
|
| 4801 |
|
|
}
|
| 4802 |
|
|
}
|
| 4803 |
|
|
return x;
|
| 4804 |
|
|
}
|
| 4805 |
|
|
|
| 4806 |
|
|
/* Return a mem ref for the memory equivalent of reg REGNO.
|
| 4807 |
|
|
This mem ref is not shared with anything. */
|
| 4808 |
|
|
|
| 4809 |
|
|
static rtx
|
| 4810 |
|
|
make_memloc (rtx ad, int regno)
|
| 4811 |
|
|
{
|
| 4812 |
|
|
/* We must rerun eliminate_regs, in case the elimination
|
| 4813 |
|
|
offsets have changed. */
|
| 4814 |
|
|
rtx tem
|
| 4815 |
|
|
= XEXP (eliminate_regs (reg_equiv_memory_loc[regno], VOIDmode, NULL_RTX),
|
| 4816 |
|
|
0);
|
| 4817 |
|
|
|
| 4818 |
|
|
/* If TEM might contain a pseudo, we must copy it to avoid
|
| 4819 |
|
|
modifying it when we do the substitution for the reload. */
|
| 4820 |
|
|
if (rtx_varies_p (tem, 0))
|
| 4821 |
|
|
tem = copy_rtx (tem);
|
| 4822 |
|
|
|
| 4823 |
|
|
tem = replace_equiv_address_nv (reg_equiv_memory_loc[regno], tem);
|
| 4824 |
|
|
tem = adjust_address_nv (tem, GET_MODE (ad), 0);
|
| 4825 |
|
|
|
| 4826 |
|
|
/* Copy the result if it's still the same as the equivalence, to avoid
|
| 4827 |
|
|
modifying it when we do the substitution for the reload. */
|
| 4828 |
|
|
if (tem == reg_equiv_memory_loc[regno])
|
| 4829 |
|
|
tem = copy_rtx (tem);
|
| 4830 |
|
|
return tem;
|
| 4831 |
|
|
}
|
| 4832 |
|
|
|
| 4833 |
|
|
/* Returns true if AD could be turned into a valid memory reference
|
| 4834 |
|
|
to mode MODE in address space AS by reloading the part pointed to
|
| 4835 |
|
|
by PART into a register. */
|
| 4836 |
|
|
|
| 4837 |
|
|
static int
|
| 4838 |
|
|
maybe_memory_address_addr_space_p (enum machine_mode mode, rtx ad,
|
| 4839 |
|
|
addr_space_t as, rtx *part)
|
| 4840 |
|
|
{
|
| 4841 |
|
|
int retv;
|
| 4842 |
|
|
rtx tem = *part;
|
| 4843 |
|
|
rtx reg = gen_rtx_REG (GET_MODE (tem), max_reg_num ());
|
| 4844 |
|
|
|
| 4845 |
|
|
*part = reg;
|
| 4846 |
|
|
retv = memory_address_addr_space_p (mode, ad, as);
|
| 4847 |
|
|
*part = tem;
|
| 4848 |
|
|
|
| 4849 |
|
|
return retv;
|
| 4850 |
|
|
}
|
| 4851 |
|
|
|
| 4852 |
|
|
/* Record all reloads needed for handling memory address AD
|
| 4853 |
|
|
which appears in *LOC in a memory reference to mode MODE
|
| 4854 |
|
|
which itself is found in location *MEMREFLOC.
|
| 4855 |
|
|
Note that we take shortcuts assuming that no multi-reg machine mode
|
| 4856 |
|
|
occurs as part of an address.
|
| 4857 |
|
|
|
| 4858 |
|
|
OPNUM and TYPE specify the purpose of this reload.
|
| 4859 |
|
|
|
| 4860 |
|
|
IND_LEVELS says how many levels of indirect addressing this machine
|
| 4861 |
|
|
supports.
|
| 4862 |
|
|
|
| 4863 |
|
|
INSN, if nonzero, is the insn in which we do the reload. It is used
|
| 4864 |
|
|
to determine if we may generate output reloads, and where to put USEs
|
| 4865 |
|
|
for pseudos that we have to replace with stack slots.
|
| 4866 |
|
|
|
| 4867 |
|
|
Value is one if this address is reloaded or replaced as a whole; it is
|
| 4868 |
|
|
zero if the top level of this address was not reloaded or replaced, and
|
| 4869 |
|
|
it is -1 if it may or may not have been reloaded or replaced.
|
| 4870 |
|
|
|
| 4871 |
|
|
Note that there is no verification that the address will be valid after
|
| 4872 |
|
|
this routine does its work. Instead, we rely on the fact that the address
|
| 4873 |
|
|
was valid when reload started. So we need only undo things that reload
|
| 4874 |
|
|
could have broken. These are wrong register types, pseudos not allocated
|
| 4875 |
|
|
to a hard register, and frame pointer elimination. */
|
| 4876 |
|
|
|
| 4877 |
|
|
static int
|
| 4878 |
|
|
find_reloads_address (enum machine_mode mode, rtx *memrefloc, rtx ad,
|
| 4879 |
|
|
rtx *loc, int opnum, enum reload_type type,
|
| 4880 |
|
|
int ind_levels, rtx insn)
|
| 4881 |
|
|
{
|
| 4882 |
|
|
addr_space_t as = memrefloc? MEM_ADDR_SPACE (*memrefloc)
|
| 4883 |
|
|
: ADDR_SPACE_GENERIC;
|
| 4884 |
|
|
int regno;
|
| 4885 |
|
|
int removed_and = 0;
|
| 4886 |
|
|
int op_index;
|
| 4887 |
|
|
rtx tem;
|
| 4888 |
|
|
|
| 4889 |
|
|
/* If the address is a register, see if it is a legitimate address and
|
| 4890 |
|
|
reload if not. We first handle the cases where we need not reload
|
| 4891 |
|
|
or where we must reload in a non-standard way. */
|
| 4892 |
|
|
|
| 4893 |
|
|
if (REG_P (ad))
|
| 4894 |
|
|
{
|
| 4895 |
|
|
regno = REGNO (ad);
|
| 4896 |
|
|
|
| 4897 |
|
|
if (reg_equiv_constant[regno] != 0)
|
| 4898 |
|
|
{
|
| 4899 |
|
|
find_reloads_address_part (reg_equiv_constant[regno], loc,
|
| 4900 |
|
|
base_reg_class (mode, MEM, SCRATCH),
|
| 4901 |
|
|
GET_MODE (ad), opnum, type, ind_levels);
|
| 4902 |
|
|
return 1;
|
| 4903 |
|
|
}
|
| 4904 |
|
|
|
| 4905 |
|
|
tem = reg_equiv_memory_loc[regno];
|
| 4906 |
|
|
if (tem != 0)
|
| 4907 |
|
|
{
|
| 4908 |
|
|
if (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)
|
| 4909 |
|
|
{
|
| 4910 |
|
|
tem = make_memloc (ad, regno);
|
| 4911 |
|
|
if (! strict_memory_address_addr_space_p (GET_MODE (tem),
|
| 4912 |
|
|
XEXP (tem, 0),
|
| 4913 |
|
|
MEM_ADDR_SPACE (tem)))
|
| 4914 |
|
|
{
|
| 4915 |
|
|
rtx orig = tem;
|
| 4916 |
|
|
|
| 4917 |
|
|
find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
|
| 4918 |
|
|
&XEXP (tem, 0), opnum,
|
| 4919 |
|
|
ADDR_TYPE (type), ind_levels, insn);
|
| 4920 |
|
|
if (!rtx_equal_p (tem, orig))
|
| 4921 |
|
|
push_reg_equiv_alt_mem (regno, tem);
|
| 4922 |
|
|
}
|
| 4923 |
|
|
/* We can avoid a reload if the register's equivalent memory
|
| 4924 |
|
|
expression is valid as an indirect memory address.
|
| 4925 |
|
|
But not all addresses are valid in a mem used as an indirect
|
| 4926 |
|
|
address: only reg or reg+constant. */
|
| 4927 |
|
|
|
| 4928 |
|
|
if (ind_levels > 0
|
| 4929 |
|
|
&& strict_memory_address_addr_space_p (mode, tem, as)
|
| 4930 |
|
|
&& (REG_P (XEXP (tem, 0))
|
| 4931 |
|
|
|| (GET_CODE (XEXP (tem, 0)) == PLUS
|
| 4932 |
|
|
&& REG_P (XEXP (XEXP (tem, 0), 0))
|
| 4933 |
|
|
&& CONSTANT_P (XEXP (XEXP (tem, 0), 1)))))
|
| 4934 |
|
|
{
|
| 4935 |
|
|
/* TEM is not the same as what we'll be replacing the
|
| 4936 |
|
|
pseudo with after reload, put a USE in front of INSN
|
| 4937 |
|
|
in the final reload pass. */
|
| 4938 |
|
|
if (replace_reloads
|
| 4939 |
|
|
&& num_not_at_initial_offset
|
| 4940 |
|
|
&& ! rtx_equal_p (tem, reg_equiv_mem[regno]))
|
| 4941 |
|
|
{
|
| 4942 |
|
|
*loc = tem;
|
| 4943 |
|
|
/* We mark the USE with QImode so that we
|
| 4944 |
|
|
recognize it as one that can be safely
|
| 4945 |
|
|
deleted at the end of reload. */
|
| 4946 |
|
|
PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad),
|
| 4947 |
|
|
insn), QImode);
|
| 4948 |
|
|
|
| 4949 |
|
|
/* This doesn't really count as replacing the address
|
| 4950 |
|
|
as a whole, since it is still a memory access. */
|
| 4951 |
|
|
}
|
| 4952 |
|
|
return 0;
|
| 4953 |
|
|
}
|
| 4954 |
|
|
ad = tem;
|
| 4955 |
|
|
}
|
| 4956 |
|
|
}
|
| 4957 |
|
|
|
| 4958 |
|
|
/* The only remaining case where we can avoid a reload is if this is a
|
| 4959 |
|
|
hard register that is valid as a base register and which is not the
|
| 4960 |
|
|
subject of a CLOBBER in this insn. */
|
| 4961 |
|
|
|
| 4962 |
|
|
else if (regno < FIRST_PSEUDO_REGISTER
|
| 4963 |
|
|
&& regno_ok_for_base_p (regno, mode, MEM, SCRATCH)
|
| 4964 |
|
|
&& ! regno_clobbered_p (regno, this_insn, mode, 0))
|
| 4965 |
|
|
return 0;
|
| 4966 |
|
|
|
| 4967 |
|
|
/* If we do not have one of the cases above, we must do the reload. */
|
| 4968 |
|
|
push_reload (ad, NULL_RTX, loc, (rtx*) 0, base_reg_class (mode, MEM, SCRATCH),
|
| 4969 |
|
|
GET_MODE (ad), VOIDmode, 0, 0, opnum, type);
|
| 4970 |
|
|
return 1;
|
| 4971 |
|
|
}
|
| 4972 |
|
|
|
| 4973 |
|
|
if (strict_memory_address_addr_space_p (mode, ad, as))
|
| 4974 |
|
|
{
|
| 4975 |
|
|
/* The address appears valid, so reloads are not needed.
|
| 4976 |
|
|
But the address may contain an eliminable register.
|
| 4977 |
|
|
This can happen because a machine with indirect addressing
|
| 4978 |
|
|
may consider a pseudo register by itself a valid address even when
|
| 4979 |
|
|
it has failed to get a hard reg.
|
| 4980 |
|
|
So do a tree-walk to find and eliminate all such regs. */
|
| 4981 |
|
|
|
| 4982 |
|
|
/* But first quickly dispose of a common case. */
|
| 4983 |
|
|
if (GET_CODE (ad) == PLUS
|
| 4984 |
|
|
&& CONST_INT_P (XEXP (ad, 1))
|
| 4985 |
|
|
&& REG_P (XEXP (ad, 0))
|
| 4986 |
|
|
&& reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
|
| 4987 |
|
|
return 0;
|
| 4988 |
|
|
|
| 4989 |
|
|
subst_reg_equivs_changed = 0;
|
| 4990 |
|
|
*loc = subst_reg_equivs (ad, insn);
|
| 4991 |
|
|
|
| 4992 |
|
|
if (! subst_reg_equivs_changed)
|
| 4993 |
|
|
return 0;
|
| 4994 |
|
|
|
| 4995 |
|
|
/* Check result for validity after substitution. */
|
| 4996 |
|
|
if (strict_memory_address_addr_space_p (mode, ad, as))
|
| 4997 |
|
|
return 0;
|
| 4998 |
|
|
}
|
| 4999 |
|
|
|
| 5000 |
|
|
#ifdef LEGITIMIZE_RELOAD_ADDRESS
|
| 5001 |
|
|
do
|
| 5002 |
|
|
{
|
| 5003 |
|
|
if (memrefloc && ADDR_SPACE_GENERIC_P (as))
|
| 5004 |
|
|
{
|
| 5005 |
|
|
LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type,
|
| 5006 |
|
|
ind_levels, win);
|
| 5007 |
|
|
}
|
| 5008 |
|
|
break;
|
| 5009 |
|
|
win:
|
| 5010 |
|
|
*memrefloc = copy_rtx (*memrefloc);
|
| 5011 |
|
|
XEXP (*memrefloc, 0) = ad;
|
| 5012 |
|
|
move_replacements (&ad, &XEXP (*memrefloc, 0));
|
| 5013 |
|
|
return -1;
|
| 5014 |
|
|
}
|
| 5015 |
|
|
while (0);
|
| 5016 |
|
|
#endif
|
| 5017 |
|
|
|
| 5018 |
|
|
/* The address is not valid. We have to figure out why. First see if
|
| 5019 |
|
|
we have an outer AND and remove it if so. Then analyze what's inside. */
|
| 5020 |
|
|
|
| 5021 |
|
|
if (GET_CODE (ad) == AND)
|
| 5022 |
|
|
{
|
| 5023 |
|
|
removed_and = 1;
|
| 5024 |
|
|
loc = &XEXP (ad, 0);
|
| 5025 |
|
|
ad = *loc;
|
| 5026 |
|
|
}
|
| 5027 |
|
|
|
| 5028 |
|
|
/* One possibility for why the address is invalid is that it is itself
|
| 5029 |
|
|
a MEM. This can happen when the frame pointer is being eliminated, a
|
| 5030 |
|
|
pseudo is not allocated to a hard register, and the offset between the
|
| 5031 |
|
|
frame and stack pointers is not its initial value. In that case the
|
| 5032 |
|
|
pseudo will have been replaced by a MEM referring to the
|
| 5033 |
|
|
stack pointer. */
|
| 5034 |
|
|
if (MEM_P (ad))
|
| 5035 |
|
|
{
|
| 5036 |
|
|
/* First ensure that the address in this MEM is valid. Then, unless
|
| 5037 |
|
|
indirect addresses are valid, reload the MEM into a register. */
|
| 5038 |
|
|
tem = ad;
|
| 5039 |
|
|
find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
|
| 5040 |
|
|
opnum, ADDR_TYPE (type),
|
| 5041 |
|
|
ind_levels == 0 ? 0 : ind_levels - 1, insn);
|
| 5042 |
|
|
|
| 5043 |
|
|
/* If tem was changed, then we must create a new memory reference to
|
| 5044 |
|
|
hold it and store it back into memrefloc. */
|
| 5045 |
|
|
if (tem != ad && memrefloc)
|
| 5046 |
|
|
{
|
| 5047 |
|
|
*memrefloc = copy_rtx (*memrefloc);
|
| 5048 |
|
|
copy_replacements (tem, XEXP (*memrefloc, 0));
|
| 5049 |
|
|
loc = &XEXP (*memrefloc, 0);
|
| 5050 |
|
|
if (removed_and)
|
| 5051 |
|
|
loc = &XEXP (*loc, 0);
|
| 5052 |
|
|
}
|
| 5053 |
|
|
|
| 5054 |
|
|
/* Check similar cases as for indirect addresses as above except
|
| 5055 |
|
|
that we can allow pseudos and a MEM since they should have been
|
| 5056 |
|
|
taken care of above. */
|
| 5057 |
|
|
|
| 5058 |
|
|
if (ind_levels == 0
|
| 5059 |
|
|
|| (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
|
| 5060 |
|
|
|| MEM_P (XEXP (tem, 0))
|
| 5061 |
|
|
|| ! (REG_P (XEXP (tem, 0))
|
| 5062 |
|
|
|| (GET_CODE (XEXP (tem, 0)) == PLUS
|
| 5063 |
|
|
&& REG_P (XEXP (XEXP (tem, 0), 0))
|
| 5064 |
|
|
&& CONST_INT_P (XEXP (XEXP (tem, 0), 1)))))
|
| 5065 |
|
|
{
|
| 5066 |
|
|
/* Must use TEM here, not AD, since it is the one that will
|
| 5067 |
|
|
have any subexpressions reloaded, if needed. */
|
| 5068 |
|
|
push_reload (tem, NULL_RTX, loc, (rtx*) 0,
|
| 5069 |
|
|
base_reg_class (mode, MEM, SCRATCH), GET_MODE (tem),
|
| 5070 |
|
|
VOIDmode, 0,
|
| 5071 |
|
|
0, opnum, type);
|
| 5072 |
|
|
return ! removed_and;
|
| 5073 |
|
|
}
|
| 5074 |
|
|
else
|
| 5075 |
|
|
return 0;
|
| 5076 |
|
|
}
|
| 5077 |
|
|
|
| 5078 |
|
|
/* If we have address of a stack slot but it's not valid because the
|
| 5079 |
|
|
displacement is too large, compute the sum in a register.
|
| 5080 |
|
|
Handle all base registers here, not just fp/ap/sp, because on some
|
| 5081 |
|
|
targets (namely SH) we can also get too large displacements from
|
| 5082 |
|
|
big-endian corrections. */
|
| 5083 |
|
|
else if (GET_CODE (ad) == PLUS
|
| 5084 |
|
|
&& REG_P (XEXP (ad, 0))
|
| 5085 |
|
|
&& REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER
|
| 5086 |
|
|
&& CONST_INT_P (XEXP (ad, 1))
|
| 5087 |
|
|
&& regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, PLUS,
|
| 5088 |
|
|
CONST_INT))
|
| 5089 |
|
|
|
| 5090 |
|
|
{
|
| 5091 |
|
|
/* Unshare the MEM rtx so we can safely alter it. */
|
| 5092 |
|
|
if (memrefloc)
|
| 5093 |
|
|
{
|
| 5094 |
|
|
*memrefloc = copy_rtx (*memrefloc);
|
| 5095 |
|
|
loc = &XEXP (*memrefloc, 0);
|
| 5096 |
|
|
if (removed_and)
|
| 5097 |
|
|
loc = &XEXP (*loc, 0);
|
| 5098 |
|
|
}
|
| 5099 |
|
|
|
| 5100 |
|
|
if (double_reg_address_ok)
|
| 5101 |
|
|
{
|
| 5102 |
|
|
/* Unshare the sum as well. */
|
| 5103 |
|
|
*loc = ad = copy_rtx (ad);
|
| 5104 |
|
|
|
| 5105 |
|
|
/* Reload the displacement into an index reg.
|
| 5106 |
|
|
We assume the frame pointer or arg pointer is a base reg. */
|
| 5107 |
|
|
find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
|
| 5108 |
|
|
INDEX_REG_CLASS, GET_MODE (ad), opnum,
|
| 5109 |
|
|
type, ind_levels);
|
| 5110 |
|
|
return 0;
|
| 5111 |
|
|
}
|
| 5112 |
|
|
else
|
| 5113 |
|
|
{
|
| 5114 |
|
|
/* If the sum of two regs is not necessarily valid,
|
| 5115 |
|
|
reload the sum into a base reg.
|
| 5116 |
|
|
That will at least work. */
|
| 5117 |
|
|
find_reloads_address_part (ad, loc,
|
| 5118 |
|
|
base_reg_class (mode, MEM, SCRATCH),
|
| 5119 |
|
|
GET_MODE (ad), opnum, type, ind_levels);
|
| 5120 |
|
|
}
|
| 5121 |
|
|
return ! removed_and;
|
| 5122 |
|
|
}
|
| 5123 |
|
|
|
| 5124 |
|
|
/* If we have an indexed stack slot, there are three possible reasons why
|
| 5125 |
|
|
it might be invalid: The index might need to be reloaded, the address
|
| 5126 |
|
|
might have been made by frame pointer elimination and hence have a
|
| 5127 |
|
|
constant out of range, or both reasons might apply.
|
| 5128 |
|
|
|
| 5129 |
|
|
We can easily check for an index needing reload, but even if that is the
|
| 5130 |
|
|
case, we might also have an invalid constant. To avoid making the
|
| 5131 |
|
|
conservative assumption and requiring two reloads, we see if this address
|
| 5132 |
|
|
is valid when not interpreted strictly. If it is, the only problem is
|
| 5133 |
|
|
that the index needs a reload and find_reloads_address_1 will take care
|
| 5134 |
|
|
of it.
|
| 5135 |
|
|
|
| 5136 |
|
|
Handle all base registers here, not just fp/ap/sp, because on some
|
| 5137 |
|
|
targets (namely SPARC) we can also get invalid addresses from preventive
|
| 5138 |
|
|
subreg big-endian corrections made by find_reloads_toplev. We
|
| 5139 |
|
|
can also get expressions involving LO_SUM (rather than PLUS) from
|
| 5140 |
|
|
find_reloads_subreg_address.
|
| 5141 |
|
|
|
| 5142 |
|
|
If we decide to do something, it must be that `double_reg_address_ok'
|
| 5143 |
|
|
is true. We generate a reload of the base register + constant and
|
| 5144 |
|
|
rework the sum so that the reload register will be added to the index.
|
| 5145 |
|
|
This is safe because we know the address isn't shared.
|
| 5146 |
|
|
|
| 5147 |
|
|
We check for the base register as both the first and second operand of
|
| 5148 |
|
|
the innermost PLUS and/or LO_SUM. */
|
| 5149 |
|
|
|
| 5150 |
|
|
for (op_index = 0; op_index < 2; ++op_index)
|
| 5151 |
|
|
{
|
| 5152 |
|
|
rtx operand, addend;
|
| 5153 |
|
|
enum rtx_code inner_code;
|
| 5154 |
|
|
|
| 5155 |
|
|
if (GET_CODE (ad) != PLUS)
|
| 5156 |
|
|
continue;
|
| 5157 |
|
|
|
| 5158 |
|
|
inner_code = GET_CODE (XEXP (ad, 0));
|
| 5159 |
|
|
if (!(GET_CODE (ad) == PLUS
|
| 5160 |
|
|
&& CONST_INT_P (XEXP (ad, 1))
|
| 5161 |
|
|
&& (inner_code == PLUS || inner_code == LO_SUM)))
|
| 5162 |
|
|
continue;
|
| 5163 |
|
|
|
| 5164 |
|
|
operand = XEXP (XEXP (ad, 0), op_index);
|
| 5165 |
|
|
if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER)
|
| 5166 |
|
|
continue;
|
| 5167 |
|
|
|
| 5168 |
|
|
addend = XEXP (XEXP (ad, 0), 1 - op_index);
|
| 5169 |
|
|
|
| 5170 |
|
|
if ((regno_ok_for_base_p (REGNO (operand), mode, inner_code,
|
| 5171 |
|
|
GET_CODE (addend))
|
| 5172 |
|
|
|| operand == frame_pointer_rtx
|
| 5173 |
|
|
#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
|
| 5174 |
|
|
|| operand == hard_frame_pointer_rtx
|
| 5175 |
|
|
#endif
|
| 5176 |
|
|
#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
|
| 5177 |
|
|
|| operand == arg_pointer_rtx
|
| 5178 |
|
|
#endif
|
| 5179 |
|
|
|| operand == stack_pointer_rtx)
|
| 5180 |
|
|
&& ! maybe_memory_address_addr_space_p
|
| 5181 |
|
|
(mode, ad, as, &XEXP (XEXP (ad, 0), 1 - op_index)))
|
| 5182 |
|
|
{
|
| 5183 |
|
|
rtx offset_reg;
|
| 5184 |
|
|
enum reg_class cls;
|
| 5185 |
|
|
|
| 5186 |
|
|
offset_reg = plus_constant (operand, INTVAL (XEXP (ad, 1)));
|
| 5187 |
|
|
|
| 5188 |
|
|
/* Form the adjusted address. */
|
| 5189 |
|
|
if (GET_CODE (XEXP (ad, 0)) == PLUS)
|
| 5190 |
|
|
ad = gen_rtx_PLUS (GET_MODE (ad),
|
| 5191 |
|
|
op_index == 0 ? offset_reg : addend,
|
| 5192 |
|
|
op_index == 0 ? addend : offset_reg);
|
| 5193 |
|
|
else
|
| 5194 |
|
|
ad = gen_rtx_LO_SUM (GET_MODE (ad),
|
| 5195 |
|
|
op_index == 0 ? offset_reg : addend,
|
| 5196 |
|
|
op_index == 0 ? addend : offset_reg);
|
| 5197 |
|
|
*loc = ad;
|
| 5198 |
|
|
|
| 5199 |
|
|
cls = base_reg_class (mode, MEM, GET_CODE (addend));
|
| 5200 |
|
|
find_reloads_address_part (XEXP (ad, op_index),
|
| 5201 |
|
|
&XEXP (ad, op_index), cls,
|
| 5202 |
|
|
GET_MODE (ad), opnum, type, ind_levels);
|
| 5203 |
|
|
find_reloads_address_1 (mode,
|
| 5204 |
|
|
XEXP (ad, 1 - op_index), 1, GET_CODE (ad),
|
| 5205 |
|
|
GET_CODE (XEXP (ad, op_index)),
|
| 5206 |
|
|
&XEXP (ad, 1 - op_index), opnum,
|
| 5207 |
|
|
type, 0, insn);
|
| 5208 |
|
|
|
| 5209 |
|
|
return 0;
|
| 5210 |
|
|
}
|
| 5211 |
|
|
}
|
| 5212 |
|
|
|
| 5213 |
|
|
/* See if address becomes valid when an eliminable register
|
| 5214 |
|
|
in a sum is replaced. */
|
| 5215 |
|
|
|
| 5216 |
|
|
tem = ad;
|
| 5217 |
|
|
if (GET_CODE (ad) == PLUS)
|
| 5218 |
|
|
tem = subst_indexed_address (ad);
|
| 5219 |
|
|
if (tem != ad && strict_memory_address_addr_space_p (mode, tem, as))
|
| 5220 |
|
|
{
|
| 5221 |
|
|
/* Ok, we win that way. Replace any additional eliminable
|
| 5222 |
|
|
registers. */
|
| 5223 |
|
|
|
| 5224 |
|
|
subst_reg_equivs_changed = 0;
|
| 5225 |
|
|
tem = subst_reg_equivs (tem, insn);
|
| 5226 |
|
|
|
| 5227 |
|
|
/* Make sure that didn't make the address invalid again. */
|
| 5228 |
|
|
|
| 5229 |
|
|
if (! subst_reg_equivs_changed
|
| 5230 |
|
|
|| strict_memory_address_addr_space_p (mode, tem, as))
|
| 5231 |
|
|
{
|
| 5232 |
|
|
*loc = tem;
|
| 5233 |
|
|
return 0;
|
| 5234 |
|
|
}
|
| 5235 |
|
|
}
|
| 5236 |
|
|
|
| 5237 |
|
|
/* If constants aren't valid addresses, reload the constant address
|
| 5238 |
|
|
into a register. */
|
| 5239 |
|
|
if (CONSTANT_P (ad) && ! strict_memory_address_addr_space_p (mode, ad, as))
|
| 5240 |
|
|
{
|
| 5241 |
|
|
enum machine_mode address_mode = GET_MODE (ad);
|
| 5242 |
|
|
if (address_mode == VOIDmode)
|
| 5243 |
|
|
address_mode = targetm.addr_space.address_mode (as);
|
| 5244 |
|
|
|
| 5245 |
|
|
/* If AD is an address in the constant pool, the MEM rtx may be shared.
|
| 5246 |
|
|
Unshare it so we can safely alter it. */
|
| 5247 |
|
|
if (memrefloc && GET_CODE (ad) == SYMBOL_REF
|
| 5248 |
|
|
&& CONSTANT_POOL_ADDRESS_P (ad))
|
| 5249 |
|
|
{
|
| 5250 |
|
|
*memrefloc = copy_rtx (*memrefloc);
|
| 5251 |
|
|
loc = &XEXP (*memrefloc, 0);
|
| 5252 |
|
|
if (removed_and)
|
| 5253 |
|
|
loc = &XEXP (*loc, 0);
|
| 5254 |
|
|
}
|
| 5255 |
|
|
|
| 5256 |
|
|
find_reloads_address_part (ad, loc, base_reg_class (mode, MEM, SCRATCH),
|
| 5257 |
|
|
address_mode, opnum, type, ind_levels);
|
| 5258 |
|
|
return ! removed_and;
|
| 5259 |
|
|
}
|
| 5260 |
|
|
|
| 5261 |
|
|
return find_reloads_address_1 (mode, ad, 0, MEM, SCRATCH, loc, opnum, type,
|
| 5262 |
|
|
ind_levels, insn);
|
| 5263 |
|
|
}
|
| 5264 |
|
|
|
| 5265 |
|
|
/* Find all pseudo regs appearing in AD
|
| 5266 |
|
|
that are eliminable in favor of equivalent values
|
| 5267 |
|
|
and do not have hard regs; replace them by their equivalents.
|
| 5268 |
|
|
INSN, if nonzero, is the insn in which we do the reload. We put USEs in
|
| 5269 |
|
|
front of it for pseudos that we have to replace with stack slots. */
|
| 5270 |
|
|
|
| 5271 |
|
|
static rtx
|
| 5272 |
|
|
subst_reg_equivs (rtx ad, rtx insn)
|
| 5273 |
|
|
{
|
| 5274 |
|
|
RTX_CODE code = GET_CODE (ad);
|
| 5275 |
|
|
int i;
|
| 5276 |
|
|
const char *fmt;
|
| 5277 |
|
|
|
| 5278 |
|
|
switch (code)
|
| 5279 |
|
|
{
|
| 5280 |
|
|
case HIGH:
|
| 5281 |
|
|
case CONST_INT:
|
| 5282 |
|
|
case CONST:
|
| 5283 |
|
|
case CONST_DOUBLE:
|
| 5284 |
|
|
case CONST_FIXED:
|
| 5285 |
|
|
case CONST_VECTOR:
|
| 5286 |
|
|
case SYMBOL_REF:
|
| 5287 |
|
|
case LABEL_REF:
|
| 5288 |
|
|
case PC:
|
| 5289 |
|
|
case CC0:
|
| 5290 |
|
|
return ad;
|
| 5291 |
|
|
|
| 5292 |
|
|
case REG:
|
| 5293 |
|
|
{
|
| 5294 |
|
|
int regno = REGNO (ad);
|
| 5295 |
|
|
|
| 5296 |
|
|
if (reg_equiv_constant[regno] != 0)
|
| 5297 |
|
|
{
|
| 5298 |
|
|
subst_reg_equivs_changed = 1;
|
| 5299 |
|
|
return reg_equiv_constant[regno];
|
| 5300 |
|
|
}
|
| 5301 |
|
|
if (reg_equiv_memory_loc[regno] && num_not_at_initial_offset)
|
| 5302 |
|
|
{
|
| 5303 |
|
|
rtx mem = make_memloc (ad, regno);
|
| 5304 |
|
|
if (! rtx_equal_p (mem, reg_equiv_mem[regno]))
|
| 5305 |
|
|
{
|
| 5306 |
|
|
subst_reg_equivs_changed = 1;
|
| 5307 |
|
|
/* We mark the USE with QImode so that we recognize it
|
| 5308 |
|
|
as one that can be safely deleted at the end of
|
| 5309 |
|
|
reload. */
|
| 5310 |
|
|
PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, ad), insn),
|
| 5311 |
|
|
QImode);
|
| 5312 |
|
|
return mem;
|
| 5313 |
|
|
}
|
| 5314 |
|
|
}
|
| 5315 |
|
|
}
|
| 5316 |
|
|
return ad;
|
| 5317 |
|
|
|
| 5318 |
|
|
case PLUS:
|
| 5319 |
|
|
/* Quickly dispose of a common case. */
|
| 5320 |
|
|
if (XEXP (ad, 0) == frame_pointer_rtx
|
| 5321 |
|
|
&& CONST_INT_P (XEXP (ad, 1)))
|
| 5322 |
|
|
return ad;
|
| 5323 |
|
|
break;
|
| 5324 |
|
|
|
| 5325 |
|
|
default:
|
| 5326 |
|
|
break;
|
| 5327 |
|
|
}
|
| 5328 |
|
|
|
| 5329 |
|
|
fmt = GET_RTX_FORMAT (code);
|
| 5330 |
|
|
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 5331 |
|
|
if (fmt[i] == 'e')
|
| 5332 |
|
|
XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i), insn);
|
| 5333 |
|
|
return ad;
|
| 5334 |
|
|
}
|
| 5335 |
|
|
|
| 5336 |
|
|
/* Compute the sum of X and Y, making canonicalizations assumed in an
|
| 5337 |
|
|
address, namely: sum constant integers, surround the sum of two
|
| 5338 |
|
|
constants with a CONST, put the constant as the second operand, and
|
| 5339 |
|
|
group the constant on the outermost sum.
|
| 5340 |
|
|
|
| 5341 |
|
|
This routine assumes both inputs are already in canonical form. */
|
| 5342 |
|
|
|
| 5343 |
|
|
rtx
|
| 5344 |
|
|
form_sum (enum machine_mode mode, rtx x, rtx y)
|
| 5345 |
|
|
{
|
| 5346 |
|
|
rtx tem;
|
| 5347 |
|
|
|
| 5348 |
|
|
gcc_assert (GET_MODE (x) == mode || GET_MODE (x) == VOIDmode);
|
| 5349 |
|
|
gcc_assert (GET_MODE (y) == mode || GET_MODE (y) == VOIDmode);
|
| 5350 |
|
|
|
| 5351 |
|
|
if (CONST_INT_P (x))
|
| 5352 |
|
|
return plus_constant (y, INTVAL (x));
|
| 5353 |
|
|
else if (CONST_INT_P (y))
|
| 5354 |
|
|
return plus_constant (x, INTVAL (y));
|
| 5355 |
|
|
else if (CONSTANT_P (x))
|
| 5356 |
|
|
tem = x, x = y, y = tem;
|
| 5357 |
|
|
|
| 5358 |
|
|
if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
|
| 5359 |
|
|
return form_sum (mode, XEXP (x, 0), form_sum (mode, XEXP (x, 1), y));
|
| 5360 |
|
|
|
| 5361 |
|
|
/* Note that if the operands of Y are specified in the opposite
|
| 5362 |
|
|
order in the recursive calls below, infinite recursion will occur. */
|
| 5363 |
|
|
if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
|
| 5364 |
|
|
return form_sum (mode, form_sum (mode, x, XEXP (y, 0)), XEXP (y, 1));
|
| 5365 |
|
|
|
| 5366 |
|
|
/* If both constant, encapsulate sum. Otherwise, just form sum. A
|
| 5367 |
|
|
constant will have been placed second. */
|
| 5368 |
|
|
if (CONSTANT_P (x) && CONSTANT_P (y))
|
| 5369 |
|
|
{
|
| 5370 |
|
|
if (GET_CODE (x) == CONST)
|
| 5371 |
|
|
x = XEXP (x, 0);
|
| 5372 |
|
|
if (GET_CODE (y) == CONST)
|
| 5373 |
|
|
y = XEXP (y, 0);
|
| 5374 |
|
|
|
| 5375 |
|
|
return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));
|
| 5376 |
|
|
}
|
| 5377 |
|
|
|
| 5378 |
|
|
return gen_rtx_PLUS (mode, x, y);
|
| 5379 |
|
|
}
|
| 5380 |
|
|
|
| 5381 |
|
|
/* If ADDR is a sum containing a pseudo register that should be
|
| 5382 |
|
|
replaced with a constant (from reg_equiv_constant),
|
| 5383 |
|
|
return the result of doing so, and also apply the associative
|
| 5384 |
|
|
law so that the result is more likely to be a valid address.
|
| 5385 |
|
|
(But it is not guaranteed to be one.)
|
| 5386 |
|
|
|
| 5387 |
|
|
Note that at most one register is replaced, even if more are
|
| 5388 |
|
|
replaceable. Also, we try to put the result into a canonical form
|
| 5389 |
|
|
so it is more likely to be a valid address.
|
| 5390 |
|
|
|
| 5391 |
|
|
In all other cases, return ADDR. */
|
| 5392 |
|
|
|
| 5393 |
|
|
static rtx
|
| 5394 |
|
|
subst_indexed_address (rtx addr)
|
| 5395 |
|
|
{
|
| 5396 |
|
|
rtx op0 = 0, op1 = 0, op2 = 0;
|
| 5397 |
|
|
rtx tem;
|
| 5398 |
|
|
int regno;
|
| 5399 |
|
|
|
| 5400 |
|
|
if (GET_CODE (addr) == PLUS)
|
| 5401 |
|
|
{
|
| 5402 |
|
|
/* Try to find a register to replace. */
|
| 5403 |
|
|
op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
|
| 5404 |
|
|
if (REG_P (op0)
|
| 5405 |
|
|
&& (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
|
| 5406 |
|
|
&& reg_renumber[regno] < 0
|
| 5407 |
|
|
&& reg_equiv_constant[regno] != 0)
|
| 5408 |
|
|
op0 = reg_equiv_constant[regno];
|
| 5409 |
|
|
else if (REG_P (op1)
|
| 5410 |
|
|
&& (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
|
| 5411 |
|
|
&& reg_renumber[regno] < 0
|
| 5412 |
|
|
&& reg_equiv_constant[regno] != 0)
|
| 5413 |
|
|
op1 = reg_equiv_constant[regno];
|
| 5414 |
|
|
else if (GET_CODE (op0) == PLUS
|
| 5415 |
|
|
&& (tem = subst_indexed_address (op0)) != op0)
|
| 5416 |
|
|
op0 = tem;
|
| 5417 |
|
|
else if (GET_CODE (op1) == PLUS
|
| 5418 |
|
|
&& (tem = subst_indexed_address (op1)) != op1)
|
| 5419 |
|
|
op1 = tem;
|
| 5420 |
|
|
else
|
| 5421 |
|
|
return addr;
|
| 5422 |
|
|
|
| 5423 |
|
|
/* Pick out up to three things to add. */
|
| 5424 |
|
|
if (GET_CODE (op1) == PLUS)
|
| 5425 |
|
|
op2 = XEXP (op1, 1), op1 = XEXP (op1, 0);
|
| 5426 |
|
|
else if (GET_CODE (op0) == PLUS)
|
| 5427 |
|
|
op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
|
| 5428 |
|
|
|
| 5429 |
|
|
/* Compute the sum. */
|
| 5430 |
|
|
if (op2 != 0)
|
| 5431 |
|
|
op1 = form_sum (GET_MODE (addr), op1, op2);
|
| 5432 |
|
|
if (op1 != 0)
|
| 5433 |
|
|
op0 = form_sum (GET_MODE (addr), op0, op1);
|
| 5434 |
|
|
|
| 5435 |
|
|
return op0;
|
| 5436 |
|
|
}
|
| 5437 |
|
|
return addr;
|
| 5438 |
|
|
}
|
| 5439 |
|
|
|
| 5440 |
|
|
/* Update the REG_INC notes for an insn. It updates all REG_INC
|
| 5441 |
|
|
notes for the instruction which refer to REGNO the to refer
|
| 5442 |
|
|
to the reload number.
|
| 5443 |
|
|
|
| 5444 |
|
|
INSN is the insn for which any REG_INC notes need updating.
|
| 5445 |
|
|
|
| 5446 |
|
|
REGNO is the register number which has been reloaded.
|
| 5447 |
|
|
|
| 5448 |
|
|
RELOADNUM is the reload number. */
|
| 5449 |
|
|
|
| 5450 |
|
|
static void
|
| 5451 |
|
|
update_auto_inc_notes (rtx insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED,
|
| 5452 |
|
|
int reloadnum ATTRIBUTE_UNUSED)
|
| 5453 |
|
|
{
|
| 5454 |
|
|
#ifdef AUTO_INC_DEC
|
| 5455 |
|
|
rtx link;
|
| 5456 |
|
|
|
| 5457 |
|
|
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
|
| 5458 |
|
|
if (REG_NOTE_KIND (link) == REG_INC
|
| 5459 |
|
|
&& (int) REGNO (XEXP (link, 0)) == regno)
|
| 5460 |
|
|
push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
|
| 5461 |
|
|
#endif
|
| 5462 |
|
|
}
|
| 5463 |
|
|
|
| 5464 |
|
|
/* Record the pseudo registers we must reload into hard registers in a
|
| 5465 |
|
|
subexpression of a would-be memory address, X referring to a value
|
| 5466 |
|
|
in mode MODE. (This function is not called if the address we find
|
| 5467 |
|
|
is strictly valid.)
|
| 5468 |
|
|
|
| 5469 |
|
|
CONTEXT = 1 means we are considering regs as index regs,
|
| 5470 |
|
|
= 0 means we are considering them as base regs.
|
| 5471 |
|
|
OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS,
|
| 5472 |
|
|
or an autoinc code.
|
| 5473 |
|
|
If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE
|
| 5474 |
|
|
is the code of the index part of the address. Otherwise, pass SCRATCH
|
| 5475 |
|
|
for this argument.
|
| 5476 |
|
|
OPNUM and TYPE specify the purpose of any reloads made.
|
| 5477 |
|
|
|
| 5478 |
|
|
IND_LEVELS says how many levels of indirect addressing are
|
| 5479 |
|
|
supported at this point in the address.
|
| 5480 |
|
|
|
| 5481 |
|
|
INSN, if nonzero, is the insn in which we do the reload. It is used
|
| 5482 |
|
|
to determine if we may generate output reloads.
|
| 5483 |
|
|
|
| 5484 |
|
|
We return nonzero if X, as a whole, is reloaded or replaced. */
|
| 5485 |
|
|
|
| 5486 |
|
|
/* Note that we take shortcuts assuming that no multi-reg machine mode
|
| 5487 |
|
|
occurs as part of an address.
|
| 5488 |
|
|
Also, this is not fully machine-customizable; it works for machines
|
| 5489 |
|
|
such as VAXen and 68000's and 32000's, but other possible machines
|
| 5490 |
|
|
could have addressing modes that this does not handle right.
|
| 5491 |
|
|
If you add push_reload calls here, you need to make sure gen_reload
|
| 5492 |
|
|
handles those cases gracefully. */
|
| 5493 |
|
|
|
| 5494 |
|
|
static int
|
| 5495 |
|
|
find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
| 5496 |
|
|
enum rtx_code outer_code, enum rtx_code index_code,
|
| 5497 |
|
|
rtx *loc, int opnum, enum reload_type type,
|
| 5498 |
|
|
int ind_levels, rtx insn)
|
| 5499 |
|
|
{
|
| 5500 |
|
|
#define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, OUTER, INDEX) \
|
| 5501 |
|
|
((CONTEXT) == 0 \
|
| 5502 |
|
|
? regno_ok_for_base_p (REGNO, MODE, OUTER, INDEX) \
|
| 5503 |
|
|
: REGNO_OK_FOR_INDEX_P (REGNO))
|
| 5504 |
|
|
|
| 5505 |
|
|
enum reg_class context_reg_class;
|
| 5506 |
|
|
RTX_CODE code = GET_CODE (x);
|
| 5507 |
|
|
|
| 5508 |
|
|
if (context == 1)
|
| 5509 |
|
|
context_reg_class = INDEX_REG_CLASS;
|
| 5510 |
|
|
else
|
| 5511 |
|
|
context_reg_class = base_reg_class (mode, outer_code, index_code);
|
| 5512 |
|
|
|
| 5513 |
|
|
switch (code)
|
| 5514 |
|
|
{
|
| 5515 |
|
|
case PLUS:
|
| 5516 |
|
|
{
|
| 5517 |
|
|
rtx orig_op0 = XEXP (x, 0);
|
| 5518 |
|
|
rtx orig_op1 = XEXP (x, 1);
|
| 5519 |
|
|
RTX_CODE code0 = GET_CODE (orig_op0);
|
| 5520 |
|
|
RTX_CODE code1 = GET_CODE (orig_op1);
|
| 5521 |
|
|
rtx op0 = orig_op0;
|
| 5522 |
|
|
rtx op1 = orig_op1;
|
| 5523 |
|
|
|
| 5524 |
|
|
if (GET_CODE (op0) == SUBREG)
|
| 5525 |
|
|
{
|
| 5526 |
|
|
op0 = SUBREG_REG (op0);
|
| 5527 |
|
|
code0 = GET_CODE (op0);
|
| 5528 |
|
|
if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER)
|
| 5529 |
|
|
op0 = gen_rtx_REG (word_mode,
|
| 5530 |
|
|
(REGNO (op0) +
|
| 5531 |
|
|
subreg_regno_offset (REGNO (SUBREG_REG (orig_op0)),
|
| 5532 |
|
|
GET_MODE (SUBREG_REG (orig_op0)),
|
| 5533 |
|
|
SUBREG_BYTE (orig_op0),
|
| 5534 |
|
|
GET_MODE (orig_op0))));
|
| 5535 |
|
|
}
|
| 5536 |
|
|
|
| 5537 |
|
|
if (GET_CODE (op1) == SUBREG)
|
| 5538 |
|
|
{
|
| 5539 |
|
|
op1 = SUBREG_REG (op1);
|
| 5540 |
|
|
code1 = GET_CODE (op1);
|
| 5541 |
|
|
if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER)
|
| 5542 |
|
|
/* ??? Why is this given op1's mode and above for
|
| 5543 |
|
|
??? op0 SUBREGs we use word_mode? */
|
| 5544 |
|
|
op1 = gen_rtx_REG (GET_MODE (op1),
|
| 5545 |
|
|
(REGNO (op1) +
|
| 5546 |
|
|
subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)),
|
| 5547 |
|
|
GET_MODE (SUBREG_REG (orig_op1)),
|
| 5548 |
|
|
SUBREG_BYTE (orig_op1),
|
| 5549 |
|
|
GET_MODE (orig_op1))));
|
| 5550 |
|
|
}
|
| 5551 |
|
|
/* Plus in the index register may be created only as a result of
|
| 5552 |
|
|
register rematerialization for expression like &localvar*4. Reload it.
|
| 5553 |
|
|
It may be possible to combine the displacement on the outer level,
|
| 5554 |
|
|
but it is probably not worthwhile to do so. */
|
| 5555 |
|
|
if (context == 1)
|
| 5556 |
|
|
{
|
| 5557 |
|
|
find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
|
| 5558 |
|
|
opnum, ADDR_TYPE (type), ind_levels, insn);
|
| 5559 |
|
|
push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
|
| 5560 |
|
|
context_reg_class,
|
| 5561 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5562 |
|
|
return 1;
|
| 5563 |
|
|
}
|
| 5564 |
|
|
|
| 5565 |
|
|
if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
|
| 5566 |
|
|
|| code0 == ZERO_EXTEND || code1 == MEM)
|
| 5567 |
|
|
{
|
| 5568 |
|
|
find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
|
| 5569 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5570 |
|
|
insn);
|
| 5571 |
|
|
find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0,
|
| 5572 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5573 |
|
|
insn);
|
| 5574 |
|
|
}
|
| 5575 |
|
|
|
| 5576 |
|
|
else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
|
| 5577 |
|
|
|| code1 == ZERO_EXTEND || code0 == MEM)
|
| 5578 |
|
|
{
|
| 5579 |
|
|
find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1,
|
| 5580 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5581 |
|
|
insn);
|
| 5582 |
|
|
find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
|
| 5583 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5584 |
|
|
insn);
|
| 5585 |
|
|
}
|
| 5586 |
|
|
|
| 5587 |
|
|
else if (code0 == CONST_INT || code0 == CONST
|
| 5588 |
|
|
|| code0 == SYMBOL_REF || code0 == LABEL_REF)
|
| 5589 |
|
|
find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0,
|
| 5590 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5591 |
|
|
insn);
|
| 5592 |
|
|
|
| 5593 |
|
|
else if (code1 == CONST_INT || code1 == CONST
|
| 5594 |
|
|
|| code1 == SYMBOL_REF || code1 == LABEL_REF)
|
| 5595 |
|
|
find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1,
|
| 5596 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5597 |
|
|
insn);
|
| 5598 |
|
|
|
| 5599 |
|
|
else if (code0 == REG && code1 == REG)
|
| 5600 |
|
|
{
|
| 5601 |
|
|
if (REGNO_OK_FOR_INDEX_P (REGNO (op1))
|
| 5602 |
|
|
&& regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
|
| 5603 |
|
|
return 0;
|
| 5604 |
|
|
else if (REGNO_OK_FOR_INDEX_P (REGNO (op0))
|
| 5605 |
|
|
&& regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
|
| 5606 |
|
|
return 0;
|
| 5607 |
|
|
else if (regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
|
| 5608 |
|
|
find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
|
| 5609 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5610 |
|
|
insn);
|
| 5611 |
|
|
else if (REGNO_OK_FOR_INDEX_P (REGNO (op1)))
|
| 5612 |
|
|
find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
|
| 5613 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5614 |
|
|
insn);
|
| 5615 |
|
|
else if (regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
|
| 5616 |
|
|
find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
|
| 5617 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5618 |
|
|
insn);
|
| 5619 |
|
|
else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)))
|
| 5620 |
|
|
find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
|
| 5621 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5622 |
|
|
insn);
|
| 5623 |
|
|
else
|
| 5624 |
|
|
{
|
| 5625 |
|
|
find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
|
| 5626 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5627 |
|
|
insn);
|
| 5628 |
|
|
find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
|
| 5629 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5630 |
|
|
insn);
|
| 5631 |
|
|
}
|
| 5632 |
|
|
}
|
| 5633 |
|
|
|
| 5634 |
|
|
else if (code0 == REG)
|
| 5635 |
|
|
{
|
| 5636 |
|
|
find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
|
| 5637 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5638 |
|
|
insn);
|
| 5639 |
|
|
find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
|
| 5640 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5641 |
|
|
insn);
|
| 5642 |
|
|
}
|
| 5643 |
|
|
|
| 5644 |
|
|
else if (code1 == REG)
|
| 5645 |
|
|
{
|
| 5646 |
|
|
find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
|
| 5647 |
|
|
&XEXP (x, 1), opnum, type, ind_levels,
|
| 5648 |
|
|
insn);
|
| 5649 |
|
|
find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
|
| 5650 |
|
|
&XEXP (x, 0), opnum, type, ind_levels,
|
| 5651 |
|
|
insn);
|
| 5652 |
|
|
}
|
| 5653 |
|
|
}
|
| 5654 |
|
|
|
| 5655 |
|
|
return 0;
|
| 5656 |
|
|
|
| 5657 |
|
|
case POST_MODIFY:
|
| 5658 |
|
|
case PRE_MODIFY:
|
| 5659 |
|
|
{
|
| 5660 |
|
|
rtx op0 = XEXP (x, 0);
|
| 5661 |
|
|
rtx op1 = XEXP (x, 1);
|
| 5662 |
|
|
enum rtx_code index_code;
|
| 5663 |
|
|
int regno;
|
| 5664 |
|
|
int reloadnum;
|
| 5665 |
|
|
|
| 5666 |
|
|
if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
|
| 5667 |
|
|
return 0;
|
| 5668 |
|
|
|
| 5669 |
|
|
/* Currently, we only support {PRE,POST}_MODIFY constructs
|
| 5670 |
|
|
where a base register is {inc,dec}remented by the contents
|
| 5671 |
|
|
of another register or by a constant value. Thus, these
|
| 5672 |
|
|
operands must match. */
|
| 5673 |
|
|
gcc_assert (op0 == XEXP (op1, 0));
|
| 5674 |
|
|
|
| 5675 |
|
|
/* Require index register (or constant). Let's just handle the
|
| 5676 |
|
|
register case in the meantime... If the target allows
|
| 5677 |
|
|
auto-modify by a constant then we could try replacing a pseudo
|
| 5678 |
|
|
register with its equivalent constant where applicable.
|
| 5679 |
|
|
|
| 5680 |
|
|
We also handle the case where the register was eliminated
|
| 5681 |
|
|
resulting in a PLUS subexpression.
|
| 5682 |
|
|
|
| 5683 |
|
|
If we later decide to reload the whole PRE_MODIFY or
|
| 5684 |
|
|
POST_MODIFY, inc_for_reload might clobber the reload register
|
| 5685 |
|
|
before reading the index. The index register might therefore
|
| 5686 |
|
|
need to live longer than a TYPE reload normally would, so be
|
| 5687 |
|
|
conservative and class it as RELOAD_OTHER. */
|
| 5688 |
|
|
if ((REG_P (XEXP (op1, 1))
|
| 5689 |
|
|
&& !REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1))))
|
| 5690 |
|
|
|| GET_CODE (XEXP (op1, 1)) == PLUS)
|
| 5691 |
|
|
find_reloads_address_1 (mode, XEXP (op1, 1), 1, code, SCRATCH,
|
| 5692 |
|
|
&XEXP (op1, 1), opnum, RELOAD_OTHER,
|
| 5693 |
|
|
ind_levels, insn);
|
| 5694 |
|
|
|
| 5695 |
|
|
gcc_assert (REG_P (XEXP (op1, 0)));
|
| 5696 |
|
|
|
| 5697 |
|
|
regno = REGNO (XEXP (op1, 0));
|
| 5698 |
|
|
index_code = GET_CODE (XEXP (op1, 1));
|
| 5699 |
|
|
|
| 5700 |
|
|
/* A register that is incremented cannot be constant! */
|
| 5701 |
|
|
gcc_assert (regno < FIRST_PSEUDO_REGISTER
|
| 5702 |
|
|
|| reg_equiv_constant[regno] == 0);
|
| 5703 |
|
|
|
| 5704 |
|
|
/* Handle a register that is equivalent to a memory location
|
| 5705 |
|
|
which cannot be addressed directly. */
|
| 5706 |
|
|
if (reg_equiv_memory_loc[regno] != 0
|
| 5707 |
|
|
&& (reg_equiv_address[regno] != 0
|
| 5708 |
|
|
|| num_not_at_initial_offset))
|
| 5709 |
|
|
{
|
| 5710 |
|
|
rtx tem = make_memloc (XEXP (x, 0), regno);
|
| 5711 |
|
|
|
| 5712 |
|
|
if (reg_equiv_address[regno]
|
| 5713 |
|
|
|| ! rtx_equal_p (tem, reg_equiv_mem[regno]))
|
| 5714 |
|
|
{
|
| 5715 |
|
|
rtx orig = tem;
|
| 5716 |
|
|
|
| 5717 |
|
|
/* First reload the memory location's address.
|
| 5718 |
|
|
We can't use ADDR_TYPE (type) here, because we need to
|
| 5719 |
|
|
write back the value after reading it, hence we actually
|
| 5720 |
|
|
need two registers. */
|
| 5721 |
|
|
find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
|
| 5722 |
|
|
&XEXP (tem, 0), opnum,
|
| 5723 |
|
|
RELOAD_OTHER,
|
| 5724 |
|
|
ind_levels, insn);
|
| 5725 |
|
|
|
| 5726 |
|
|
if (!rtx_equal_p (tem, orig))
|
| 5727 |
|
|
push_reg_equiv_alt_mem (regno, tem);
|
| 5728 |
|
|
|
| 5729 |
|
|
/* Then reload the memory location into a base
|
| 5730 |
|
|
register. */
|
| 5731 |
|
|
reloadnum = push_reload (tem, tem, &XEXP (x, 0),
|
| 5732 |
|
|
&XEXP (op1, 0),
|
| 5733 |
|
|
base_reg_class (mode, code,
|
| 5734 |
|
|
index_code),
|
| 5735 |
|
|
GET_MODE (x), GET_MODE (x), 0,
|
| 5736 |
|
|
0, opnum, RELOAD_OTHER);
|
| 5737 |
|
|
|
| 5738 |
|
|
update_auto_inc_notes (this_insn, regno, reloadnum);
|
| 5739 |
|
|
return 0;
|
| 5740 |
|
|
}
|
| 5741 |
|
|
}
|
| 5742 |
|
|
|
| 5743 |
|
|
if (reg_renumber[regno] >= 0)
|
| 5744 |
|
|
regno = reg_renumber[regno];
|
| 5745 |
|
|
|
| 5746 |
|
|
/* We require a base register here... */
|
| 5747 |
|
|
if (!regno_ok_for_base_p (regno, GET_MODE (x), code, index_code))
|
| 5748 |
|
|
{
|
| 5749 |
|
|
reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0),
|
| 5750 |
|
|
&XEXP (op1, 0), &XEXP (x, 0),
|
| 5751 |
|
|
base_reg_class (mode, code, index_code),
|
| 5752 |
|
|
GET_MODE (x), GET_MODE (x), 0, 0,
|
| 5753 |
|
|
opnum, RELOAD_OTHER);
|
| 5754 |
|
|
|
| 5755 |
|
|
update_auto_inc_notes (this_insn, regno, reloadnum);
|
| 5756 |
|
|
return 0;
|
| 5757 |
|
|
}
|
| 5758 |
|
|
}
|
| 5759 |
|
|
return 0;
|
| 5760 |
|
|
|
| 5761 |
|
|
case POST_INC:
|
| 5762 |
|
|
case POST_DEC:
|
| 5763 |
|
|
case PRE_INC:
|
| 5764 |
|
|
case PRE_DEC:
|
| 5765 |
|
|
if (REG_P (XEXP (x, 0)))
|
| 5766 |
|
|
{
|
| 5767 |
|
|
int regno = REGNO (XEXP (x, 0));
|
| 5768 |
|
|
int value = 0;
|
| 5769 |
|
|
rtx x_orig = x;
|
| 5770 |
|
|
|
| 5771 |
|
|
/* A register that is incremented cannot be constant! */
|
| 5772 |
|
|
gcc_assert (regno < FIRST_PSEUDO_REGISTER
|
| 5773 |
|
|
|| reg_equiv_constant[regno] == 0);
|
| 5774 |
|
|
|
| 5775 |
|
|
/* Handle a register that is equivalent to a memory location
|
| 5776 |
|
|
which cannot be addressed directly. */
|
| 5777 |
|
|
if (reg_equiv_memory_loc[regno] != 0
|
| 5778 |
|
|
&& (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
|
| 5779 |
|
|
{
|
| 5780 |
|
|
rtx tem = make_memloc (XEXP (x, 0), regno);
|
| 5781 |
|
|
if (reg_equiv_address[regno]
|
| 5782 |
|
|
|| ! rtx_equal_p (tem, reg_equiv_mem[regno]))
|
| 5783 |
|
|
{
|
| 5784 |
|
|
rtx orig = tem;
|
| 5785 |
|
|
|
| 5786 |
|
|
/* First reload the memory location's address.
|
| 5787 |
|
|
We can't use ADDR_TYPE (type) here, because we need to
|
| 5788 |
|
|
write back the value after reading it, hence we actually
|
| 5789 |
|
|
need two registers. */
|
| 5790 |
|
|
find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
|
| 5791 |
|
|
&XEXP (tem, 0), opnum, type,
|
| 5792 |
|
|
ind_levels, insn);
|
| 5793 |
|
|
if (!rtx_equal_p (tem, orig))
|
| 5794 |
|
|
push_reg_equiv_alt_mem (regno, tem);
|
| 5795 |
|
|
/* Put this inside a new increment-expression. */
|
| 5796 |
|
|
x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem);
|
| 5797 |
|
|
/* Proceed to reload that, as if it contained a register. */
|
| 5798 |
|
|
}
|
| 5799 |
|
|
}
|
| 5800 |
|
|
|
| 5801 |
|
|
/* If we have a hard register that is ok in this incdec context,
|
| 5802 |
|
|
don't make a reload. If the register isn't nice enough for
|
| 5803 |
|
|
autoincdec, we can reload it. But, if an autoincrement of a
|
| 5804 |
|
|
register that we here verified as playing nice, still outside
|
| 5805 |
|
|
isn't "valid", it must be that no autoincrement is "valid".
|
| 5806 |
|
|
If that is true and something made an autoincrement anyway,
|
| 5807 |
|
|
this must be a special context where one is allowed.
|
| 5808 |
|
|
(For example, a "push" instruction.)
|
| 5809 |
|
|
We can't improve this address, so leave it alone. */
|
| 5810 |
|
|
|
| 5811 |
|
|
/* Otherwise, reload the autoincrement into a suitable hard reg
|
| 5812 |
|
|
and record how much to increment by. */
|
| 5813 |
|
|
|
| 5814 |
|
|
if (reg_renumber[regno] >= 0)
|
| 5815 |
|
|
regno = reg_renumber[regno];
|
| 5816 |
|
|
if (regno >= FIRST_PSEUDO_REGISTER
|
| 5817 |
|
|
|| !REG_OK_FOR_CONTEXT (context, regno, mode, code,
|
| 5818 |
|
|
index_code))
|
| 5819 |
|
|
{
|
| 5820 |
|
|
int reloadnum;
|
| 5821 |
|
|
|
| 5822 |
|
|
/* If we can output the register afterwards, do so, this
|
| 5823 |
|
|
saves the extra update.
|
| 5824 |
|
|
We can do so if we have an INSN - i.e. no JUMP_INSN nor
|
| 5825 |
|
|
CALL_INSN - and it does not set CC0.
|
| 5826 |
|
|
But don't do this if we cannot directly address the
|
| 5827 |
|
|
memory location, since this will make it harder to
|
| 5828 |
|
|
reuse address reloads, and increases register pressure.
|
| 5829 |
|
|
Also don't do this if we can probably update x directly. */
|
| 5830 |
|
|
rtx equiv = (MEM_P (XEXP (x, 0))
|
| 5831 |
|
|
? XEXP (x, 0)
|
| 5832 |
|
|
: reg_equiv_mem[regno]);
|
| 5833 |
|
|
int icode
|
| 5834 |
|
|
= (int) optab_handler (add_optab, GET_MODE (x))->insn_code;
|
| 5835 |
|
|
if (insn && NONJUMP_INSN_P (insn) && equiv
|
| 5836 |
|
|
&& memory_operand (equiv, GET_MODE (equiv))
|
| 5837 |
|
|
#ifdef HAVE_cc0
|
| 5838 |
|
|
&& ! sets_cc0_p (PATTERN (insn))
|
| 5839 |
|
|
#endif
|
| 5840 |
|
|
&& ! (icode != CODE_FOR_nothing
|
| 5841 |
|
|
&& ((*insn_data[icode].operand[0].predicate)
|
| 5842 |
|
|
(equiv, GET_MODE (x)))
|
| 5843 |
|
|
&& ((*insn_data[icode].operand[1].predicate)
|
| 5844 |
|
|
(equiv, GET_MODE (x)))))
|
| 5845 |
|
|
{
|
| 5846 |
|
|
/* We use the original pseudo for loc, so that
|
| 5847 |
|
|
emit_reload_insns() knows which pseudo this
|
| 5848 |
|
|
reload refers to and updates the pseudo rtx, not
|
| 5849 |
|
|
its equivalent memory location, as well as the
|
| 5850 |
|
|
corresponding entry in reg_last_reload_reg. */
|
| 5851 |
|
|
loc = &XEXP (x_orig, 0);
|
| 5852 |
|
|
x = XEXP (x, 0);
|
| 5853 |
|
|
reloadnum
|
| 5854 |
|
|
= push_reload (x, x, loc, loc,
|
| 5855 |
|
|
context_reg_class,
|
| 5856 |
|
|
GET_MODE (x), GET_MODE (x), 0, 0,
|
| 5857 |
|
|
opnum, RELOAD_OTHER);
|
| 5858 |
|
|
}
|
| 5859 |
|
|
else
|
| 5860 |
|
|
{
|
| 5861 |
|
|
reloadnum
|
| 5862 |
|
|
= push_reload (x, x, loc, (rtx*) 0,
|
| 5863 |
|
|
context_reg_class,
|
| 5864 |
|
|
GET_MODE (x), GET_MODE (x), 0, 0,
|
| 5865 |
|
|
opnum, type);
|
| 5866 |
|
|
rld[reloadnum].inc
|
| 5867 |
|
|
= find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
|
| 5868 |
|
|
|
| 5869 |
|
|
value = 1;
|
| 5870 |
|
|
}
|
| 5871 |
|
|
|
| 5872 |
|
|
update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)),
|
| 5873 |
|
|
reloadnum);
|
| 5874 |
|
|
}
|
| 5875 |
|
|
return value;
|
| 5876 |
|
|
}
|
| 5877 |
|
|
return 0;
|
| 5878 |
|
|
|
| 5879 |
|
|
case TRUNCATE:
|
| 5880 |
|
|
case SIGN_EXTEND:
|
| 5881 |
|
|
case ZERO_EXTEND:
|
| 5882 |
|
|
/* Look for parts to reload in the inner expression and reload them
|
| 5883 |
|
|
too, in addition to this operation. Reloading all inner parts in
|
| 5884 |
|
|
addition to this one shouldn't be necessary, but at this point,
|
| 5885 |
|
|
we don't know if we can possibly omit any part that *can* be
|
| 5886 |
|
|
reloaded. Targets that are better off reloading just either part
|
| 5887 |
|
|
(or perhaps even a different part of an outer expression), should
|
| 5888 |
|
|
define LEGITIMIZE_RELOAD_ADDRESS. */
|
| 5889 |
|
|
find_reloads_address_1 (GET_MODE (XEXP (x, 0)), XEXP (x, 0),
|
| 5890 |
|
|
context, code, SCRATCH, &XEXP (x, 0), opnum,
|
| 5891 |
|
|
type, ind_levels, insn);
|
| 5892 |
|
|
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
| 5893 |
|
|
context_reg_class,
|
| 5894 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5895 |
|
|
return 1;
|
| 5896 |
|
|
|
| 5897 |
|
|
case MEM:
|
| 5898 |
|
|
/* This is probably the result of a substitution, by eliminate_regs, of
|
| 5899 |
|
|
an equivalent address for a pseudo that was not allocated to a hard
|
| 5900 |
|
|
register. Verify that the specified address is valid and reload it
|
| 5901 |
|
|
into a register.
|
| 5902 |
|
|
|
| 5903 |
|
|
Since we know we are going to reload this item, don't decrement for
|
| 5904 |
|
|
the indirection level.
|
| 5905 |
|
|
|
| 5906 |
|
|
Note that this is actually conservative: it would be slightly more
|
| 5907 |
|
|
efficient to use the value of SPILL_INDIRECT_LEVELS from
|
| 5908 |
|
|
reload1.c here. */
|
| 5909 |
|
|
|
| 5910 |
|
|
find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
|
| 5911 |
|
|
opnum, ADDR_TYPE (type), ind_levels, insn);
|
| 5912 |
|
|
push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
|
| 5913 |
|
|
context_reg_class,
|
| 5914 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5915 |
|
|
return 1;
|
| 5916 |
|
|
|
| 5917 |
|
|
case REG:
|
| 5918 |
|
|
{
|
| 5919 |
|
|
int regno = REGNO (x);
|
| 5920 |
|
|
|
| 5921 |
|
|
if (reg_equiv_constant[regno] != 0)
|
| 5922 |
|
|
{
|
| 5923 |
|
|
find_reloads_address_part (reg_equiv_constant[regno], loc,
|
| 5924 |
|
|
context_reg_class,
|
| 5925 |
|
|
GET_MODE (x), opnum, type, ind_levels);
|
| 5926 |
|
|
return 1;
|
| 5927 |
|
|
}
|
| 5928 |
|
|
|
| 5929 |
|
|
#if 0 /* This might screw code in reload1.c to delete prior output-reload
|
| 5930 |
|
|
that feeds this insn. */
|
| 5931 |
|
|
if (reg_equiv_mem[regno] != 0)
|
| 5932 |
|
|
{
|
| 5933 |
|
|
push_reload (reg_equiv_mem[regno], NULL_RTX, loc, (rtx*) 0,
|
| 5934 |
|
|
context_reg_class,
|
| 5935 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5936 |
|
|
return 1;
|
| 5937 |
|
|
}
|
| 5938 |
|
|
#endif
|
| 5939 |
|
|
|
| 5940 |
|
|
if (reg_equiv_memory_loc[regno]
|
| 5941 |
|
|
&& (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
|
| 5942 |
|
|
{
|
| 5943 |
|
|
rtx tem = make_memloc (x, regno);
|
| 5944 |
|
|
if (reg_equiv_address[regno] != 0
|
| 5945 |
|
|
|| ! rtx_equal_p (tem, reg_equiv_mem[regno]))
|
| 5946 |
|
|
{
|
| 5947 |
|
|
x = tem;
|
| 5948 |
|
|
find_reloads_address (GET_MODE (x), &x, XEXP (x, 0),
|
| 5949 |
|
|
&XEXP (x, 0), opnum, ADDR_TYPE (type),
|
| 5950 |
|
|
ind_levels, insn);
|
| 5951 |
|
|
if (!rtx_equal_p (x, tem))
|
| 5952 |
|
|
push_reg_equiv_alt_mem (regno, x);
|
| 5953 |
|
|
}
|
| 5954 |
|
|
}
|
| 5955 |
|
|
|
| 5956 |
|
|
if (reg_renumber[regno] >= 0)
|
| 5957 |
|
|
regno = reg_renumber[regno];
|
| 5958 |
|
|
|
| 5959 |
|
|
if (regno >= FIRST_PSEUDO_REGISTER
|
| 5960 |
|
|
|| !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
|
| 5961 |
|
|
index_code))
|
| 5962 |
|
|
{
|
| 5963 |
|
|
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
| 5964 |
|
|
context_reg_class,
|
| 5965 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5966 |
|
|
return 1;
|
| 5967 |
|
|
}
|
| 5968 |
|
|
|
| 5969 |
|
|
/* If a register appearing in an address is the subject of a CLOBBER
|
| 5970 |
|
|
in this insn, reload it into some other register to be safe.
|
| 5971 |
|
|
The CLOBBER is supposed to make the register unavailable
|
| 5972 |
|
|
from before this insn to after it. */
|
| 5973 |
|
|
if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0))
|
| 5974 |
|
|
{
|
| 5975 |
|
|
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
| 5976 |
|
|
context_reg_class,
|
| 5977 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5978 |
|
|
return 1;
|
| 5979 |
|
|
}
|
| 5980 |
|
|
}
|
| 5981 |
|
|
return 0;
|
| 5982 |
|
|
|
| 5983 |
|
|
case SUBREG:
|
| 5984 |
|
|
if (REG_P (SUBREG_REG (x)))
|
| 5985 |
|
|
{
|
| 5986 |
|
|
/* If this is a SUBREG of a hard register and the resulting register
|
| 5987 |
|
|
is of the wrong class, reload the whole SUBREG. This avoids
|
| 5988 |
|
|
needless copies if SUBREG_REG is multi-word. */
|
| 5989 |
|
|
if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
|
| 5990 |
|
|
{
|
| 5991 |
|
|
int regno ATTRIBUTE_UNUSED = subreg_regno (x);
|
| 5992 |
|
|
|
| 5993 |
|
|
if (!REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
|
| 5994 |
|
|
index_code))
|
| 5995 |
|
|
{
|
| 5996 |
|
|
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
| 5997 |
|
|
context_reg_class,
|
| 5998 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 5999 |
|
|
return 1;
|
| 6000 |
|
|
}
|
| 6001 |
|
|
}
|
| 6002 |
|
|
/* If this is a SUBREG of a pseudo-register, and the pseudo-register
|
| 6003 |
|
|
is larger than the class size, then reload the whole SUBREG. */
|
| 6004 |
|
|
else
|
| 6005 |
|
|
{
|
| 6006 |
|
|
enum reg_class rclass = context_reg_class;
|
| 6007 |
|
|
if ((unsigned) CLASS_MAX_NREGS (rclass, GET_MODE (SUBREG_REG (x)))
|
| 6008 |
|
|
> reg_class_size[rclass])
|
| 6009 |
|
|
{
|
| 6010 |
|
|
x = find_reloads_subreg_address (x, 0, opnum,
|
| 6011 |
|
|
ADDR_TYPE (type),
|
| 6012 |
|
|
ind_levels, insn);
|
| 6013 |
|
|
push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass,
|
| 6014 |
|
|
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
| 6015 |
|
|
return 1;
|
| 6016 |
|
|
}
|
| 6017 |
|
|
}
|
| 6018 |
|
|
}
|
| 6019 |
|
|
break;
|
| 6020 |
|
|
|
| 6021 |
|
|
default:
|
| 6022 |
|
|
break;
|
| 6023 |
|
|
}
|
| 6024 |
|
|
|
| 6025 |
|
|
{
|
| 6026 |
|
|
const char *fmt = GET_RTX_FORMAT (code);
|
| 6027 |
|
|
int i;
|
| 6028 |
|
|
|
| 6029 |
|
|
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 6030 |
|
|
{
|
| 6031 |
|
|
if (fmt[i] == 'e')
|
| 6032 |
|
|
/* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once
|
| 6033 |
|
|
we get here. */
|
| 6034 |
|
|
find_reloads_address_1 (mode, XEXP (x, i), context, code, SCRATCH,
|
| 6035 |
|
|
&XEXP (x, i), opnum, type, ind_levels, insn);
|
| 6036 |
|
|
}
|
| 6037 |
|
|
}
|
| 6038 |
|
|
|
| 6039 |
|
|
#undef REG_OK_FOR_CONTEXT
|
| 6040 |
|
|
return 0;
|
| 6041 |
|
|
}
|
| 6042 |
|
|
|
| 6043 |
|
|
/* X, which is found at *LOC, is a part of an address that needs to be
|
| 6044 |
|
|
reloaded into a register of class RCLASS. If X is a constant, or if
|
| 6045 |
|
|
X is a PLUS that contains a constant, check that the constant is a
|
| 6046 |
|
|
legitimate operand and that we are supposed to be able to load
|
| 6047 |
|
|
it into the register.
|
| 6048 |
|
|
|
| 6049 |
|
|
If not, force the constant into memory and reload the MEM instead.
|
| 6050 |
|
|
|
| 6051 |
|
|
MODE is the mode to use, in case X is an integer constant.
|
| 6052 |
|
|
|
| 6053 |
|
|
OPNUM and TYPE describe the purpose of any reloads made.
|
| 6054 |
|
|
|
| 6055 |
|
|
IND_LEVELS says how many levels of indirect addressing this machine
|
| 6056 |
|
|
supports. */
|
| 6057 |
|
|
|
| 6058 |
|
|
static void
|
| 6059 |
|
|
find_reloads_address_part (rtx x, rtx *loc, enum reg_class rclass,
|
| 6060 |
|
|
enum machine_mode mode, int opnum,
|
| 6061 |
|
|
enum reload_type type, int ind_levels)
|
| 6062 |
|
|
{
|
| 6063 |
|
|
if (CONSTANT_P (x)
|
| 6064 |
|
|
&& (! LEGITIMATE_CONSTANT_P (x)
|
| 6065 |
|
|
|| PREFERRED_RELOAD_CLASS (x, rclass) == NO_REGS))
|
| 6066 |
|
|
{
|
| 6067 |
|
|
x = force_const_mem (mode, x);
|
| 6068 |
|
|
find_reloads_address (mode, &x, XEXP (x, 0), &XEXP (x, 0),
|
| 6069 |
|
|
opnum, type, ind_levels, 0);
|
| 6070 |
|
|
}
|
| 6071 |
|
|
|
| 6072 |
|
|
else if (GET_CODE (x) == PLUS
|
| 6073 |
|
|
&& CONSTANT_P (XEXP (x, 1))
|
| 6074 |
|
|
&& (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
|
| 6075 |
|
|
|| PREFERRED_RELOAD_CLASS (XEXP (x, 1), rclass) == NO_REGS))
|
| 6076 |
|
|
{
|
| 6077 |
|
|
rtx tem;
|
| 6078 |
|
|
|
| 6079 |
|
|
tem = force_const_mem (GET_MODE (x), XEXP (x, 1));
|
| 6080 |
|
|
x = gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), tem);
|
| 6081 |
|
|
find_reloads_address (mode, &XEXP (x, 1), XEXP (tem, 0), &XEXP (tem, 0),
|
| 6082 |
|
|
opnum, type, ind_levels, 0);
|
| 6083 |
|
|
}
|
| 6084 |
|
|
|
| 6085 |
|
|
push_reload (x, NULL_RTX, loc, (rtx*) 0, rclass,
|
| 6086 |
|
|
mode, VOIDmode, 0, 0, opnum, type);
|
| 6087 |
|
|
}
|
| 6088 |
|
|
|
| 6089 |
|
|
/* X, a subreg of a pseudo, is a part of an address that needs to be
|
| 6090 |
|
|
reloaded.
|
| 6091 |
|
|
|
| 6092 |
|
|
If the pseudo is equivalent to a memory location that cannot be directly
|
| 6093 |
|
|
addressed, make the necessary address reloads.
|
| 6094 |
|
|
|
| 6095 |
|
|
If address reloads have been necessary, or if the address is changed
|
| 6096 |
|
|
by register elimination, return the rtx of the memory location;
|
| 6097 |
|
|
otherwise, return X.
|
| 6098 |
|
|
|
| 6099 |
|
|
If FORCE_REPLACE is nonzero, unconditionally replace the subreg with the
|
| 6100 |
|
|
memory location.
|
| 6101 |
|
|
|
| 6102 |
|
|
OPNUM and TYPE identify the purpose of the reload.
|
| 6103 |
|
|
|
| 6104 |
|
|
IND_LEVELS says how many levels of indirect addressing are
|
| 6105 |
|
|
supported at this point in the address.
|
| 6106 |
|
|
|
| 6107 |
|
|
INSN, if nonzero, is the insn in which we do the reload. It is used
|
| 6108 |
|
|
to determine where to put USEs for pseudos that we have to replace with
|
| 6109 |
|
|
stack slots. */
|
| 6110 |
|
|
|
| 6111 |
|
|
static rtx
|
| 6112 |
|
|
find_reloads_subreg_address (rtx x, int force_replace, int opnum,
|
| 6113 |
|
|
enum reload_type type, int ind_levels, rtx insn)
|
| 6114 |
|
|
{
|
| 6115 |
|
|
int regno = REGNO (SUBREG_REG (x));
|
| 6116 |
|
|
|
| 6117 |
|
|
if (reg_equiv_memory_loc[regno])
|
| 6118 |
|
|
{
|
| 6119 |
|
|
/* If the address is not directly addressable, or if the address is not
|
| 6120 |
|
|
offsettable, then it must be replaced. */
|
| 6121 |
|
|
if (! force_replace
|
| 6122 |
|
|
&& (reg_equiv_address[regno]
|
| 6123 |
|
|
|| ! offsettable_memref_p (reg_equiv_mem[regno])))
|
| 6124 |
|
|
force_replace = 1;
|
| 6125 |
|
|
|
| 6126 |
|
|
if (force_replace || num_not_at_initial_offset)
|
| 6127 |
|
|
{
|
| 6128 |
|
|
rtx tem = make_memloc (SUBREG_REG (x), regno);
|
| 6129 |
|
|
|
| 6130 |
|
|
/* If the address changes because of register elimination, then
|
| 6131 |
|
|
it must be replaced. */
|
| 6132 |
|
|
if (force_replace
|
| 6133 |
|
|
|| ! rtx_equal_p (tem, reg_equiv_mem[regno]))
|
| 6134 |
|
|
{
|
| 6135 |
|
|
unsigned outer_size = GET_MODE_SIZE (GET_MODE (x));
|
| 6136 |
|
|
unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
|
| 6137 |
|
|
int offset;
|
| 6138 |
|
|
rtx orig = tem;
|
| 6139 |
|
|
int reloaded;
|
| 6140 |
|
|
|
| 6141 |
|
|
/* For big-endian paradoxical subregs, SUBREG_BYTE does not
|
| 6142 |
|
|
hold the correct (negative) byte offset. */
|
| 6143 |
|
|
if (BYTES_BIG_ENDIAN && outer_size > inner_size)
|
| 6144 |
|
|
offset = inner_size - outer_size;
|
| 6145 |
|
|
else
|
| 6146 |
|
|
offset = SUBREG_BYTE (x);
|
| 6147 |
|
|
|
| 6148 |
|
|
XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset);
|
| 6149 |
|
|
PUT_MODE (tem, GET_MODE (x));
|
| 6150 |
|
|
if (MEM_OFFSET (tem))
|
| 6151 |
|
|
set_mem_offset (tem, plus_constant (MEM_OFFSET (tem), offset));
|
| 6152 |
|
|
if (MEM_SIZE (tem)
|
| 6153 |
|
|
&& INTVAL (MEM_SIZE (tem)) != (HOST_WIDE_INT) outer_size)
|
| 6154 |
|
|
set_mem_size (tem, GEN_INT (outer_size));
|
| 6155 |
|
|
|
| 6156 |
|
|
/* If this was a paradoxical subreg that we replaced, the
|
| 6157 |
|
|
resulting memory must be sufficiently aligned to allow
|
| 6158 |
|
|
us to widen the mode of the memory. */
|
| 6159 |
|
|
if (outer_size > inner_size)
|
| 6160 |
|
|
{
|
| 6161 |
|
|
rtx base;
|
| 6162 |
|
|
|
| 6163 |
|
|
base = XEXP (tem, 0);
|
| 6164 |
|
|
if (GET_CODE (base) == PLUS)
|
| 6165 |
|
|
{
|
| 6166 |
|
|
if (CONST_INT_P (XEXP (base, 1))
|
| 6167 |
|
|
&& INTVAL (XEXP (base, 1)) % outer_size != 0)
|
| 6168 |
|
|
return x;
|
| 6169 |
|
|
base = XEXP (base, 0);
|
| 6170 |
|
|
}
|
| 6171 |
|
|
if (!REG_P (base)
|
| 6172 |
|
|
|| (REGNO_POINTER_ALIGN (REGNO (base))
|
| 6173 |
|
|
< outer_size * BITS_PER_UNIT))
|
| 6174 |
|
|
return x;
|
| 6175 |
|
|
}
|
| 6176 |
|
|
|
| 6177 |
|
|
reloaded = find_reloads_address (GET_MODE (tem), &tem,
|
| 6178 |
|
|
XEXP (tem, 0), &XEXP (tem, 0),
|
| 6179 |
|
|
opnum, type, ind_levels, insn);
|
| 6180 |
|
|
/* ??? Do we need to handle nonzero offsets somehow? */
|
| 6181 |
|
|
if (!offset && !rtx_equal_p (tem, orig))
|
| 6182 |
|
|
push_reg_equiv_alt_mem (regno, tem);
|
| 6183 |
|
|
|
| 6184 |
|
|
/* For some processors an address may be valid in the
|
| 6185 |
|
|
original mode but not in a smaller mode. For
|
| 6186 |
|
|
example, ARM accepts a scaled index register in
|
| 6187 |
|
|
SImode but not in HImode. Note that this is only
|
| 6188 |
|
|
a problem if the address in reg_equiv_mem is already
|
| 6189 |
|
|
invalid in the new mode; other cases would be fixed
|
| 6190 |
|
|
by find_reloads_address as usual.
|
| 6191 |
|
|
|
| 6192 |
|
|
??? We attempt to handle such cases here by doing an
|
| 6193 |
|
|
additional reload of the full address after the
|
| 6194 |
|
|
usual processing by find_reloads_address. Note that
|
| 6195 |
|
|
this may not work in the general case, but it seems
|
| 6196 |
|
|
to cover the cases where this situation currently
|
| 6197 |
|
|
occurs. A more general fix might be to reload the
|
| 6198 |
|
|
*value* instead of the address, but this would not
|
| 6199 |
|
|
be expected by the callers of this routine as-is.
|
| 6200 |
|
|
|
| 6201 |
|
|
If find_reloads_address already completed replaced
|
| 6202 |
|
|
the address, there is nothing further to do. */
|
| 6203 |
|
|
if (reloaded == 0
|
| 6204 |
|
|
&& reg_equiv_mem[regno] != 0
|
| 6205 |
|
|
&& !strict_memory_address_addr_space_p
|
| 6206 |
|
|
(GET_MODE (x), XEXP (reg_equiv_mem[regno], 0),
|
| 6207 |
|
|
MEM_ADDR_SPACE (reg_equiv_mem[regno])))
|
| 6208 |
|
|
push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0,
|
| 6209 |
|
|
base_reg_class (GET_MODE (tem), MEM, SCRATCH),
|
| 6210 |
|
|
GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0,
|
| 6211 |
|
|
opnum, type);
|
| 6212 |
|
|
|
| 6213 |
|
|
/* If this is not a toplevel operand, find_reloads doesn't see
|
| 6214 |
|
|
this substitution. We have to emit a USE of the pseudo so
|
| 6215 |
|
|
that delete_output_reload can see it. */
|
| 6216 |
|
|
if (replace_reloads && recog_data.operand[opnum] != x)
|
| 6217 |
|
|
/* We mark the USE with QImode so that we recognize it
|
| 6218 |
|
|
as one that can be safely deleted at the end of
|
| 6219 |
|
|
reload. */
|
| 6220 |
|
|
PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode,
|
| 6221 |
|
|
SUBREG_REG (x)),
|
| 6222 |
|
|
insn), QImode);
|
| 6223 |
|
|
x = tem;
|
| 6224 |
|
|
}
|
| 6225 |
|
|
}
|
| 6226 |
|
|
}
|
| 6227 |
|
|
return x;
|
| 6228 |
|
|
}
|
| 6229 |
|
|
|
| 6230 |
|
|
/* Substitute into the current INSN the registers into which we have reloaded
|
| 6231 |
|
|
the things that need reloading. The array `replacements'
|
| 6232 |
|
|
contains the locations of all pointers that must be changed
|
| 6233 |
|
|
and says what to replace them with.
|
| 6234 |
|
|
|
| 6235 |
|
|
Return the rtx that X translates into; usually X, but modified. */
|
| 6236 |
|
|
|
| 6237 |
|
|
void
|
| 6238 |
|
|
subst_reloads (rtx insn)
|
| 6239 |
|
|
{
|
| 6240 |
|
|
int i;
|
| 6241 |
|
|
|
| 6242 |
|
|
for (i = 0; i < n_replacements; i++)
|
| 6243 |
|
|
{
|
| 6244 |
|
|
struct replacement *r = &replacements[i];
|
| 6245 |
|
|
rtx reloadreg = rld[r->what].reg_rtx;
|
| 6246 |
|
|
if (reloadreg)
|
| 6247 |
|
|
{
|
| 6248 |
|
|
#ifdef DEBUG_RELOAD
|
| 6249 |
|
|
/* This checking takes a very long time on some platforms
|
| 6250 |
|
|
causing the gcc.c-torture/compile/limits-fnargs.c test
|
| 6251 |
|
|
to time out during testing. See PR 31850.
|
| 6252 |
|
|
|
| 6253 |
|
|
Internal consistency test. Check that we don't modify
|
| 6254 |
|
|
anything in the equivalence arrays. Whenever something from
|
| 6255 |
|
|
those arrays needs to be reloaded, it must be unshared before
|
| 6256 |
|
|
being substituted into; the equivalence must not be modified.
|
| 6257 |
|
|
Otherwise, if the equivalence is used after that, it will
|
| 6258 |
|
|
have been modified, and the thing substituted (probably a
|
| 6259 |
|
|
register) is likely overwritten and not a usable equivalence. */
|
| 6260 |
|
|
int check_regno;
|
| 6261 |
|
|
|
| 6262 |
|
|
for (check_regno = 0; check_regno < max_regno; check_regno++)
|
| 6263 |
|
|
{
|
| 6264 |
|
|
#define CHECK_MODF(ARRAY) \
|
| 6265 |
|
|
gcc_assert (!ARRAY[check_regno] \
|
| 6266 |
|
|
|| !loc_mentioned_in_p (r->where, \
|
| 6267 |
|
|
ARRAY[check_regno]))
|
| 6268 |
|
|
|
| 6269 |
|
|
CHECK_MODF (reg_equiv_constant);
|
| 6270 |
|
|
CHECK_MODF (reg_equiv_memory_loc);
|
| 6271 |
|
|
CHECK_MODF (reg_equiv_address);
|
| 6272 |
|
|
CHECK_MODF (reg_equiv_mem);
|
| 6273 |
|
|
#undef CHECK_MODF
|
| 6274 |
|
|
}
|
| 6275 |
|
|
#endif /* DEBUG_RELOAD */
|
| 6276 |
|
|
|
| 6277 |
|
|
/* If we're replacing a LABEL_REF with a register, there must
|
| 6278 |
|
|
already be an indication (to e.g. flow) which label this
|
| 6279 |
|
|
register refers to. */
|
| 6280 |
|
|
gcc_assert (GET_CODE (*r->where) != LABEL_REF
|
| 6281 |
|
|
|| !JUMP_P (insn)
|
| 6282 |
|
|
|| find_reg_note (insn,
|
| 6283 |
|
|
REG_LABEL_OPERAND,
|
| 6284 |
|
|
XEXP (*r->where, 0))
|
| 6285 |
|
|
|| label_is_jump_target_p (XEXP (*r->where, 0), insn));
|
| 6286 |
|
|
|
| 6287 |
|
|
/* Encapsulate RELOADREG so its machine mode matches what
|
| 6288 |
|
|
used to be there. Note that gen_lowpart_common will
|
| 6289 |
|
|
do the wrong thing if RELOADREG is multi-word. RELOADREG
|
| 6290 |
|
|
will always be a REG here. */
|
| 6291 |
|
|
if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
|
| 6292 |
|
|
reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode);
|
| 6293 |
|
|
|
| 6294 |
|
|
/* If we are putting this into a SUBREG and RELOADREG is a
|
| 6295 |
|
|
SUBREG, we would be making nested SUBREGs, so we have to fix
|
| 6296 |
|
|
this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */
|
| 6297 |
|
|
|
| 6298 |
|
|
if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG)
|
| 6299 |
|
|
{
|
| 6300 |
|
|
if (GET_MODE (*r->subreg_loc)
|
| 6301 |
|
|
== GET_MODE (SUBREG_REG (reloadreg)))
|
| 6302 |
|
|
*r->subreg_loc = SUBREG_REG (reloadreg);
|
| 6303 |
|
|
else
|
| 6304 |
|
|
{
|
| 6305 |
|
|
int final_offset =
|
| 6306 |
|
|
SUBREG_BYTE (*r->subreg_loc) + SUBREG_BYTE (reloadreg);
|
| 6307 |
|
|
|
| 6308 |
|
|
/* When working with SUBREGs the rule is that the byte
|
| 6309 |
|
|
offset must be a multiple of the SUBREG's mode. */
|
| 6310 |
|
|
final_offset = (final_offset /
|
| 6311 |
|
|
GET_MODE_SIZE (GET_MODE (*r->subreg_loc)));
|
| 6312 |
|
|
final_offset = (final_offset *
|
| 6313 |
|
|
GET_MODE_SIZE (GET_MODE (*r->subreg_loc)));
|
| 6314 |
|
|
|
| 6315 |
|
|
*r->where = SUBREG_REG (reloadreg);
|
| 6316 |
|
|
SUBREG_BYTE (*r->subreg_loc) = final_offset;
|
| 6317 |
|
|
}
|
| 6318 |
|
|
}
|
| 6319 |
|
|
else
|
| 6320 |
|
|
*r->where = reloadreg;
|
| 6321 |
|
|
}
|
| 6322 |
|
|
/* If reload got no reg and isn't optional, something's wrong. */
|
| 6323 |
|
|
else
|
| 6324 |
|
|
gcc_assert (rld[r->what].optional);
|
| 6325 |
|
|
}
|
| 6326 |
|
|
}
|
| 6327 |
|
|
|
| 6328 |
|
|
/* Make a copy of any replacements being done into X and move those
|
| 6329 |
|
|
copies to locations in Y, a copy of X. */
|
| 6330 |
|
|
|
| 6331 |
|
|
void
|
| 6332 |
|
|
copy_replacements (rtx x, rtx y)
|
| 6333 |
|
|
{
|
| 6334 |
|
|
/* We can't support X being a SUBREG because we might then need to know its
|
| 6335 |
|
|
location if something inside it was replaced. */
|
| 6336 |
|
|
gcc_assert (GET_CODE (x) != SUBREG);
|
| 6337 |
|
|
|
| 6338 |
|
|
copy_replacements_1 (&x, &y, n_replacements);
|
| 6339 |
|
|
}
|
| 6340 |
|
|
|
| 6341 |
|
|
static void
|
| 6342 |
|
|
copy_replacements_1 (rtx *px, rtx *py, int orig_replacements)
|
| 6343 |
|
|
{
|
| 6344 |
|
|
int i, j;
|
| 6345 |
|
|
rtx x, y;
|
| 6346 |
|
|
struct replacement *r;
|
| 6347 |
|
|
enum rtx_code code;
|
| 6348 |
|
|
const char *fmt;
|
| 6349 |
|
|
|
| 6350 |
|
|
for (j = 0; j < orig_replacements; j++)
|
| 6351 |
|
|
{
|
| 6352 |
|
|
if (replacements[j].subreg_loc == px)
|
| 6353 |
|
|
{
|
| 6354 |
|
|
r = &replacements[n_replacements++];
|
| 6355 |
|
|
r->where = replacements[j].where;
|
| 6356 |
|
|
r->subreg_loc = py;
|
| 6357 |
|
|
r->what = replacements[j].what;
|
| 6358 |
|
|
r->mode = replacements[j].mode;
|
| 6359 |
|
|
}
|
| 6360 |
|
|
else if (replacements[j].where == px)
|
| 6361 |
|
|
{
|
| 6362 |
|
|
r = &replacements[n_replacements++];
|
| 6363 |
|
|
r->where = py;
|
| 6364 |
|
|
r->subreg_loc = 0;
|
| 6365 |
|
|
r->what = replacements[j].what;
|
| 6366 |
|
|
r->mode = replacements[j].mode;
|
| 6367 |
|
|
}
|
| 6368 |
|
|
}
|
| 6369 |
|
|
|
| 6370 |
|
|
x = *px;
|
| 6371 |
|
|
y = *py;
|
| 6372 |
|
|
code = GET_CODE (x);
|
| 6373 |
|
|
fmt = GET_RTX_FORMAT (code);
|
| 6374 |
|
|
|
| 6375 |
|
|
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 6376 |
|
|
{
|
| 6377 |
|
|
if (fmt[i] == 'e')
|
| 6378 |
|
|
copy_replacements_1 (&XEXP (x, i), &XEXP (y, i), orig_replacements);
|
| 6379 |
|
|
else if (fmt[i] == 'E')
|
| 6380 |
|
|
for (j = XVECLEN (x, i); --j >= 0; )
|
| 6381 |
|
|
copy_replacements_1 (&XVECEXP (x, i, j), &XVECEXP (y, i, j),
|
| 6382 |
|
|
orig_replacements);
|
| 6383 |
|
|
}
|
| 6384 |
|
|
}
|
| 6385 |
|
|
|
| 6386 |
|
|
/* Change any replacements being done to *X to be done to *Y. */
|
| 6387 |
|
|
|
| 6388 |
|
|
void
|
| 6389 |
|
|
move_replacements (rtx *x, rtx *y)
|
| 6390 |
|
|
{
|
| 6391 |
|
|
int i;
|
| 6392 |
|
|
|
| 6393 |
|
|
for (i = 0; i < n_replacements; i++)
|
| 6394 |
|
|
if (replacements[i].subreg_loc == x)
|
| 6395 |
|
|
replacements[i].subreg_loc = y;
|
| 6396 |
|
|
else if (replacements[i].where == x)
|
| 6397 |
|
|
{
|
| 6398 |
|
|
replacements[i].where = y;
|
| 6399 |
|
|
replacements[i].subreg_loc = 0;
|
| 6400 |
|
|
}
|
| 6401 |
|
|
}
|
| 6402 |
|
|
|
| 6403 |
|
|
/* If LOC was scheduled to be replaced by something, return the replacement.
|
| 6404 |
|
|
Otherwise, return *LOC. */
|
| 6405 |
|
|
|
| 6406 |
|
|
rtx
|
| 6407 |
|
|
find_replacement (rtx *loc)
|
| 6408 |
|
|
{
|
| 6409 |
|
|
struct replacement *r;
|
| 6410 |
|
|
|
| 6411 |
|
|
for (r = &replacements[0]; r < &replacements[n_replacements]; r++)
|
| 6412 |
|
|
{
|
| 6413 |
|
|
rtx reloadreg = rld[r->what].reg_rtx;
|
| 6414 |
|
|
|
| 6415 |
|
|
if (reloadreg && r->where == loc)
|
| 6416 |
|
|
{
|
| 6417 |
|
|
if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
|
| 6418 |
|
|
reloadreg = gen_rtx_REG (r->mode, REGNO (reloadreg));
|
| 6419 |
|
|
|
| 6420 |
|
|
return reloadreg;
|
| 6421 |
|
|
}
|
| 6422 |
|
|
else if (reloadreg && r->subreg_loc == loc)
|
| 6423 |
|
|
{
|
| 6424 |
|
|
/* RELOADREG must be either a REG or a SUBREG.
|
| 6425 |
|
|
|
| 6426 |
|
|
??? Is it actually still ever a SUBREG? If so, why? */
|
| 6427 |
|
|
|
| 6428 |
|
|
if (REG_P (reloadreg))
|
| 6429 |
|
|
return gen_rtx_REG (GET_MODE (*loc),
|
| 6430 |
|
|
(REGNO (reloadreg) +
|
| 6431 |
|
|
subreg_regno_offset (REGNO (SUBREG_REG (*loc)),
|
| 6432 |
|
|
GET_MODE (SUBREG_REG (*loc)),
|
| 6433 |
|
|
SUBREG_BYTE (*loc),
|
| 6434 |
|
|
GET_MODE (*loc))));
|
| 6435 |
|
|
else if (GET_MODE (reloadreg) == GET_MODE (*loc))
|
| 6436 |
|
|
return reloadreg;
|
| 6437 |
|
|
else
|
| 6438 |
|
|
{
|
| 6439 |
|
|
int final_offset = SUBREG_BYTE (reloadreg) + SUBREG_BYTE (*loc);
|
| 6440 |
|
|
|
| 6441 |
|
|
/* When working with SUBREGs the rule is that the byte
|
| 6442 |
|
|
offset must be a multiple of the SUBREG's mode. */
|
| 6443 |
|
|
final_offset = (final_offset / GET_MODE_SIZE (GET_MODE (*loc)));
|
| 6444 |
|
|
final_offset = (final_offset * GET_MODE_SIZE (GET_MODE (*loc)));
|
| 6445 |
|
|
return gen_rtx_SUBREG (GET_MODE (*loc), SUBREG_REG (reloadreg),
|
| 6446 |
|
|
final_offset);
|
| 6447 |
|
|
}
|
| 6448 |
|
|
}
|
| 6449 |
|
|
}
|
| 6450 |
|
|
|
| 6451 |
|
|
/* If *LOC is a PLUS, MINUS, or MULT, see if a replacement is scheduled for
|
| 6452 |
|
|
what's inside and make a new rtl if so. */
|
| 6453 |
|
|
if (GET_CODE (*loc) == PLUS || GET_CODE (*loc) == MINUS
|
| 6454 |
|
|
|| GET_CODE (*loc) == MULT)
|
| 6455 |
|
|
{
|
| 6456 |
|
|
rtx x = find_replacement (&XEXP (*loc, 0));
|
| 6457 |
|
|
rtx y = find_replacement (&XEXP (*loc, 1));
|
| 6458 |
|
|
|
| 6459 |
|
|
if (x != XEXP (*loc, 0) || y != XEXP (*loc, 1))
|
| 6460 |
|
|
return gen_rtx_fmt_ee (GET_CODE (*loc), GET_MODE (*loc), x, y);
|
| 6461 |
|
|
}
|
| 6462 |
|
|
|
| 6463 |
|
|
return *loc;
|
| 6464 |
|
|
}
|
| 6465 |
|
|
|
| 6466 |
|
|
/* Return nonzero if register in range [REGNO, ENDREGNO)
|
| 6467 |
|
|
appears either explicitly or implicitly in X
|
| 6468 |
|
|
other than being stored into (except for earlyclobber operands).
|
| 6469 |
|
|
|
| 6470 |
|
|
References contained within the substructure at LOC do not count.
|
| 6471 |
|
|
LOC may be zero, meaning don't ignore anything.
|
| 6472 |
|
|
|
| 6473 |
|
|
This is similar to refers_to_regno_p in rtlanal.c except that we
|
| 6474 |
|
|
look at equivalences for pseudos that didn't get hard registers. */
|
| 6475 |
|
|
|
| 6476 |
|
|
static int
|
| 6477 |
|
|
refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
|
| 6478 |
|
|
rtx x, rtx *loc)
|
| 6479 |
|
|
{
|
| 6480 |
|
|
int i;
|
| 6481 |
|
|
unsigned int r;
|
| 6482 |
|
|
RTX_CODE code;
|
| 6483 |
|
|
const char *fmt;
|
| 6484 |
|
|
|
| 6485 |
|
|
if (x == 0)
|
| 6486 |
|
|
return 0;
|
| 6487 |
|
|
|
| 6488 |
|
|
repeat:
|
| 6489 |
|
|
code = GET_CODE (x);
|
| 6490 |
|
|
|
| 6491 |
|
|
switch (code)
|
| 6492 |
|
|
{
|
| 6493 |
|
|
case REG:
|
| 6494 |
|
|
r = REGNO (x);
|
| 6495 |
|
|
|
| 6496 |
|
|
/* If this is a pseudo, a hard register must not have been allocated.
|
| 6497 |
|
|
X must therefore either be a constant or be in memory. */
|
| 6498 |
|
|
if (r >= FIRST_PSEUDO_REGISTER)
|
| 6499 |
|
|
{
|
| 6500 |
|
|
if (reg_equiv_memory_loc[r])
|
| 6501 |
|
|
return refers_to_regno_for_reload_p (regno, endregno,
|
| 6502 |
|
|
reg_equiv_memory_loc[r],
|
| 6503 |
|
|
(rtx*) 0);
|
| 6504 |
|
|
|
| 6505 |
|
|
gcc_assert (reg_equiv_constant[r] || reg_equiv_invariant[r]);
|
| 6506 |
|
|
return 0;
|
| 6507 |
|
|
}
|
| 6508 |
|
|
|
| 6509 |
|
|
return (endregno > r
|
| 6510 |
|
|
&& regno < r + (r < FIRST_PSEUDO_REGISTER
|
| 6511 |
|
|
? hard_regno_nregs[r][GET_MODE (x)]
|
| 6512 |
|
|
: 1));
|
| 6513 |
|
|
|
| 6514 |
|
|
case SUBREG:
|
| 6515 |
|
|
/* If this is a SUBREG of a hard reg, we can see exactly which
|
| 6516 |
|
|
registers are being modified. Otherwise, handle normally. */
|
| 6517 |
|
|
if (REG_P (SUBREG_REG (x))
|
| 6518 |
|
|
&& REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
|
| 6519 |
|
|
{
|
| 6520 |
|
|
unsigned int inner_regno = subreg_regno (x);
|
| 6521 |
|
|
unsigned int inner_endregno
|
| 6522 |
|
|
= inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
|
| 6523 |
|
|
? subreg_nregs (x) : 1);
|
| 6524 |
|
|
|
| 6525 |
|
|
return endregno > inner_regno && regno < inner_endregno;
|
| 6526 |
|
|
}
|
| 6527 |
|
|
break;
|
| 6528 |
|
|
|
| 6529 |
|
|
case CLOBBER:
|
| 6530 |
|
|
case SET:
|
| 6531 |
|
|
if (&SET_DEST (x) != loc
|
| 6532 |
|
|
/* Note setting a SUBREG counts as referring to the REG it is in for
|
| 6533 |
|
|
a pseudo but not for hard registers since we can
|
| 6534 |
|
|
treat each word individually. */
|
| 6535 |
|
|
&& ((GET_CODE (SET_DEST (x)) == SUBREG
|
| 6536 |
|
|
&& loc != &SUBREG_REG (SET_DEST (x))
|
| 6537 |
|
|
&& REG_P (SUBREG_REG (SET_DEST (x)))
|
| 6538 |
|
|
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
|
| 6539 |
|
|
&& refers_to_regno_for_reload_p (regno, endregno,
|
| 6540 |
|
|
SUBREG_REG (SET_DEST (x)),
|
| 6541 |
|
|
loc))
|
| 6542 |
|
|
/* If the output is an earlyclobber operand, this is
|
| 6543 |
|
|
a conflict. */
|
| 6544 |
|
|
|| ((!REG_P (SET_DEST (x))
|
| 6545 |
|
|
|| earlyclobber_operand_p (SET_DEST (x)))
|
| 6546 |
|
|
&& refers_to_regno_for_reload_p (regno, endregno,
|
| 6547 |
|
|
SET_DEST (x), loc))))
|
| 6548 |
|
|
return 1;
|
| 6549 |
|
|
|
| 6550 |
|
|
if (code == CLOBBER || loc == &SET_SRC (x))
|
| 6551 |
|
|
return 0;
|
| 6552 |
|
|
x = SET_SRC (x);
|
| 6553 |
|
|
goto repeat;
|
| 6554 |
|
|
|
| 6555 |
|
|
default:
|
| 6556 |
|
|
break;
|
| 6557 |
|
|
}
|
| 6558 |
|
|
|
| 6559 |
|
|
/* X does not match, so try its subexpressions. */
|
| 6560 |
|
|
|
| 6561 |
|
|
fmt = GET_RTX_FORMAT (code);
|
| 6562 |
|
|
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 6563 |
|
|
{
|
| 6564 |
|
|
if (fmt[i] == 'e' && loc != &XEXP (x, i))
|
| 6565 |
|
|
{
|
| 6566 |
|
|
if (i == 0)
|
| 6567 |
|
|
{
|
| 6568 |
|
|
x = XEXP (x, 0);
|
| 6569 |
|
|
goto repeat;
|
| 6570 |
|
|
}
|
| 6571 |
|
|
else
|
| 6572 |
|
|
if (refers_to_regno_for_reload_p (regno, endregno,
|
| 6573 |
|
|
XEXP (x, i), loc))
|
| 6574 |
|
|
return 1;
|
| 6575 |
|
|
}
|
| 6576 |
|
|
else if (fmt[i] == 'E')
|
| 6577 |
|
|
{
|
| 6578 |
|
|
int j;
|
| 6579 |
|
|
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
| 6580 |
|
|
if (loc != &XVECEXP (x, i, j)
|
| 6581 |
|
|
&& refers_to_regno_for_reload_p (regno, endregno,
|
| 6582 |
|
|
XVECEXP (x, i, j), loc))
|
| 6583 |
|
|
return 1;
|
| 6584 |
|
|
}
|
| 6585 |
|
|
}
|
| 6586 |
|
|
return 0;
|
| 6587 |
|
|
}
|
| 6588 |
|
|
|
| 6589 |
|
|
/* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
|
| 6590 |
|
|
we check if any register number in X conflicts with the relevant register
|
| 6591 |
|
|
numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
|
| 6592 |
|
|
contains a MEM (we don't bother checking for memory addresses that can't
|
| 6593 |
|
|
conflict because we expect this to be a rare case.
|
| 6594 |
|
|
|
| 6595 |
|
|
This function is similar to reg_overlap_mentioned_p in rtlanal.c except
|
| 6596 |
|
|
that we look at equivalences for pseudos that didn't get hard registers. */
|
| 6597 |
|
|
|
| 6598 |
|
|
int
|
| 6599 |
|
|
reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
|
| 6600 |
|
|
{
|
| 6601 |
|
|
int regno, endregno;
|
| 6602 |
|
|
|
| 6603 |
|
|
/* Overly conservative. */
|
| 6604 |
|
|
if (GET_CODE (x) == STRICT_LOW_PART
|
| 6605 |
|
|
|| GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
|
| 6606 |
|
|
x = XEXP (x, 0);
|
| 6607 |
|
|
|
| 6608 |
|
|
/* If either argument is a constant, then modifying X can not affect IN. */
|
| 6609 |
|
|
if (CONSTANT_P (x) || CONSTANT_P (in))
|
| 6610 |
|
|
return 0;
|
| 6611 |
|
|
else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
|
| 6612 |
|
|
return refers_to_mem_for_reload_p (in);
|
| 6613 |
|
|
else if (GET_CODE (x) == SUBREG)
|
| 6614 |
|
|
{
|
| 6615 |
|
|
regno = REGNO (SUBREG_REG (x));
|
| 6616 |
|
|
if (regno < FIRST_PSEUDO_REGISTER)
|
| 6617 |
|
|
regno += subreg_regno_offset (REGNO (SUBREG_REG (x)),
|
| 6618 |
|
|
GET_MODE (SUBREG_REG (x)),
|
| 6619 |
|
|
SUBREG_BYTE (x),
|
| 6620 |
|
|
GET_MODE (x));
|
| 6621 |
|
|
endregno = regno + (regno < FIRST_PSEUDO_REGISTER
|
| 6622 |
|
|
? subreg_nregs (x) : 1);
|
| 6623 |
|
|
|
| 6624 |
|
|
return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0);
|
| 6625 |
|
|
}
|
| 6626 |
|
|
else if (REG_P (x))
|
| 6627 |
|
|
{
|
| 6628 |
|
|
regno = REGNO (x);
|
| 6629 |
|
|
|
| 6630 |
|
|
/* If this is a pseudo, it must not have been assigned a hard register.
|
| 6631 |
|
|
Therefore, it must either be in memory or be a constant. */
|
| 6632 |
|
|
|
| 6633 |
|
|
if (regno >= FIRST_PSEUDO_REGISTER)
|
| 6634 |
|
|
{
|
| 6635 |
|
|
if (reg_equiv_memory_loc[regno])
|
| 6636 |
|
|
return refers_to_mem_for_reload_p (in);
|
| 6637 |
|
|
gcc_assert (reg_equiv_constant[regno]);
|
| 6638 |
|
|
return 0;
|
| 6639 |
|
|
}
|
| 6640 |
|
|
|
| 6641 |
|
|
endregno = END_HARD_REGNO (x);
|
| 6642 |
|
|
|
| 6643 |
|
|
return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0);
|
| 6644 |
|
|
}
|
| 6645 |
|
|
else if (MEM_P (x))
|
| 6646 |
|
|
return refers_to_mem_for_reload_p (in);
|
| 6647 |
|
|
else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC
|
| 6648 |
|
|
|| GET_CODE (x) == CC0)
|
| 6649 |
|
|
return reg_mentioned_p (x, in);
|
| 6650 |
|
|
else
|
| 6651 |
|
|
{
|
| 6652 |
|
|
gcc_assert (GET_CODE (x) == PLUS);
|
| 6653 |
|
|
|
| 6654 |
|
|
/* We actually want to know if X is mentioned somewhere inside IN.
|
| 6655 |
|
|
We must not say that (plus (sp) (const_int 124)) is in
|
| 6656 |
|
|
(plus (sp) (const_int 64)), since that can lead to incorrect reload
|
| 6657 |
|
|
allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS
|
| 6658 |
|
|
into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */
|
| 6659 |
|
|
while (MEM_P (in))
|
| 6660 |
|
|
in = XEXP (in, 0);
|
| 6661 |
|
|
if (REG_P (in))
|
| 6662 |
|
|
return 0;
|
| 6663 |
|
|
else if (GET_CODE (in) == PLUS)
|
| 6664 |
|
|
return (rtx_equal_p (x, in)
|
| 6665 |
|
|
|| reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0))
|
| 6666 |
|
|
|| reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1)));
|
| 6667 |
|
|
else return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in)
|
| 6668 |
|
|
|| reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in));
|
| 6669 |
|
|
}
|
| 6670 |
|
|
|
| 6671 |
|
|
gcc_unreachable ();
|
| 6672 |
|
|
}
|
| 6673 |
|
|
|
| 6674 |
|
|
/* Return nonzero if anything in X contains a MEM. Look also for pseudo
|
| 6675 |
|
|
registers. */
|
| 6676 |
|
|
|
| 6677 |
|
|
static int
|
| 6678 |
|
|
refers_to_mem_for_reload_p (rtx x)
|
| 6679 |
|
|
{
|
| 6680 |
|
|
const char *fmt;
|
| 6681 |
|
|
int i;
|
| 6682 |
|
|
|
| 6683 |
|
|
if (MEM_P (x))
|
| 6684 |
|
|
return 1;
|
| 6685 |
|
|
|
| 6686 |
|
|
if (REG_P (x))
|
| 6687 |
|
|
return (REGNO (x) >= FIRST_PSEUDO_REGISTER
|
| 6688 |
|
|
&& reg_equiv_memory_loc[REGNO (x)]);
|
| 6689 |
|
|
|
| 6690 |
|
|
fmt = GET_RTX_FORMAT (GET_CODE (x));
|
| 6691 |
|
|
for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
|
| 6692 |
|
|
if (fmt[i] == 'e'
|
| 6693 |
|
|
&& (MEM_P (XEXP (x, i))
|
| 6694 |
|
|
|| refers_to_mem_for_reload_p (XEXP (x, i))))
|
| 6695 |
|
|
return 1;
|
| 6696 |
|
|
|
| 6697 |
|
|
return 0;
|
| 6698 |
|
|
}
|
| 6699 |
|
|
|
| 6700 |
|
|
/* Check the insns before INSN to see if there is a suitable register
|
| 6701 |
|
|
containing the same value as GOAL.
|
| 6702 |
|
|
If OTHER is -1, look for a register in class RCLASS.
|
| 6703 |
|
|
Otherwise, just see if register number OTHER shares GOAL's value.
|
| 6704 |
|
|
|
| 6705 |
|
|
Return an rtx for the register found, or zero if none is found.
|
| 6706 |
|
|
|
| 6707 |
|
|
If RELOAD_REG_P is (short *)1,
|
| 6708 |
|
|
we reject any hard reg that appears in reload_reg_rtx
|
| 6709 |
|
|
because such a hard reg is also needed coming into this insn.
|
| 6710 |
|
|
|
| 6711 |
|
|
If RELOAD_REG_P is any other nonzero value,
|
| 6712 |
|
|
it is a vector indexed by hard reg number
|
| 6713 |
|
|
and we reject any hard reg whose element in the vector is nonnegative
|
| 6714 |
|
|
as well as any that appears in reload_reg_rtx.
|
| 6715 |
|
|
|
| 6716 |
|
|
If GOAL is zero, then GOALREG is a register number; we look
|
| 6717 |
|
|
for an equivalent for that register.
|
| 6718 |
|
|
|
| 6719 |
|
|
MODE is the machine mode of the value we want an equivalence for.
|
| 6720 |
|
|
If GOAL is nonzero and not VOIDmode, then it must have mode MODE.
|
| 6721 |
|
|
|
| 6722 |
|
|
This function is used by jump.c as well as in the reload pass.
|
| 6723 |
|
|
|
| 6724 |
|
|
If GOAL is the sum of the stack pointer and a constant, we treat it
|
| 6725 |
|
|
as if it were a constant except that sp is required to be unchanging. */
|
| 6726 |
|
|
|
| 6727 |
|
|
rtx
|
| 6728 |
|
|
find_equiv_reg (rtx goal, rtx insn, enum reg_class rclass, int other,
|
| 6729 |
|
|
short *reload_reg_p, int goalreg, enum machine_mode mode)
|
| 6730 |
|
|
{
|
| 6731 |
|
|
rtx p = insn;
|
| 6732 |
|
|
rtx goaltry, valtry, value, where;
|
| 6733 |
|
|
rtx pat;
|
| 6734 |
|
|
int regno = -1;
|
| 6735 |
|
|
int valueno;
|
| 6736 |
|
|
int goal_mem = 0;
|
| 6737 |
|
|
int goal_const = 0;
|
| 6738 |
|
|
int goal_mem_addr_varies = 0;
|
| 6739 |
|
|
int need_stable_sp = 0;
|
| 6740 |
|
|
int nregs;
|
| 6741 |
|
|
int valuenregs;
|
| 6742 |
|
|
int num = 0;
|
| 6743 |
|
|
|
| 6744 |
|
|
if (goal == 0)
|
| 6745 |
|
|
regno = goalreg;
|
| 6746 |
|
|
else if (REG_P (goal))
|
| 6747 |
|
|
regno = REGNO (goal);
|
| 6748 |
|
|
else if (MEM_P (goal))
|
| 6749 |
|
|
{
|
| 6750 |
|
|
enum rtx_code code = GET_CODE (XEXP (goal, 0));
|
| 6751 |
|
|
if (MEM_VOLATILE_P (goal))
|
| 6752 |
|
|
return 0;
|
| 6753 |
|
|
if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal)))
|
| 6754 |
|
|
return 0;
|
| 6755 |
|
|
/* An address with side effects must be reexecuted. */
|
| 6756 |
|
|
switch (code)
|
| 6757 |
|
|
{
|
| 6758 |
|
|
case POST_INC:
|
| 6759 |
|
|
case PRE_INC:
|
| 6760 |
|
|
case POST_DEC:
|
| 6761 |
|
|
case PRE_DEC:
|
| 6762 |
|
|
case POST_MODIFY:
|
| 6763 |
|
|
case PRE_MODIFY:
|
| 6764 |
|
|
return 0;
|
| 6765 |
|
|
default:
|
| 6766 |
|
|
break;
|
| 6767 |
|
|
}
|
| 6768 |
|
|
goal_mem = 1;
|
| 6769 |
|
|
}
|
| 6770 |
|
|
else if (CONSTANT_P (goal))
|
| 6771 |
|
|
goal_const = 1;
|
| 6772 |
|
|
else if (GET_CODE (goal) == PLUS
|
| 6773 |
|
|
&& XEXP (goal, 0) == stack_pointer_rtx
|
| 6774 |
|
|
&& CONSTANT_P (XEXP (goal, 1)))
|
| 6775 |
|
|
goal_const = need_stable_sp = 1;
|
| 6776 |
|
|
else if (GET_CODE (goal) == PLUS
|
| 6777 |
|
|
&& XEXP (goal, 0) == frame_pointer_rtx
|
| 6778 |
|
|
&& CONSTANT_P (XEXP (goal, 1)))
|
| 6779 |
|
|
goal_const = 1;
|
| 6780 |
|
|
else
|
| 6781 |
|
|
return 0;
|
| 6782 |
|
|
|
| 6783 |
|
|
num = 0;
|
| 6784 |
|
|
/* Scan insns back from INSN, looking for one that copies
|
| 6785 |
|
|
a value into or out of GOAL.
|
| 6786 |
|
|
Stop and give up if we reach a label. */
|
| 6787 |
|
|
|
| 6788 |
|
|
while (1)
|
| 6789 |
|
|
{
|
| 6790 |
|
|
p = PREV_INSN (p);
|
| 6791 |
|
|
if (p && DEBUG_INSN_P (p))
|
| 6792 |
|
|
continue;
|
| 6793 |
|
|
num++;
|
| 6794 |
|
|
if (p == 0 || LABEL_P (p)
|
| 6795 |
|
|
|| num > PARAM_VALUE (PARAM_MAX_RELOAD_SEARCH_INSNS))
|
| 6796 |
|
|
return 0;
|
| 6797 |
|
|
|
| 6798 |
|
|
if (NONJUMP_INSN_P (p)
|
| 6799 |
|
|
/* If we don't want spill regs ... */
|
| 6800 |
|
|
&& (! (reload_reg_p != 0
|
| 6801 |
|
|
&& reload_reg_p != (short *) (HOST_WIDE_INT) 1)
|
| 6802 |
|
|
/* ... then ignore insns introduced by reload; they aren't
|
| 6803 |
|
|
useful and can cause results in reload_as_needed to be
|
| 6804 |
|
|
different from what they were when calculating the need for
|
| 6805 |
|
|
spills. If we notice an input-reload insn here, we will
|
| 6806 |
|
|
reject it below, but it might hide a usable equivalent.
|
| 6807 |
|
|
That makes bad code. It may even fail: perhaps no reg was
|
| 6808 |
|
|
spilled for this insn because it was assumed we would find
|
| 6809 |
|
|
that equivalent. */
|
| 6810 |
|
|
|| INSN_UID (p) < reload_first_uid))
|
| 6811 |
|
|
{
|
| 6812 |
|
|
rtx tem;
|
| 6813 |
|
|
pat = single_set (p);
|
| 6814 |
|
|
|
| 6815 |
|
|
/* First check for something that sets some reg equal to GOAL. */
|
| 6816 |
|
|
if (pat != 0
|
| 6817 |
|
|
&& ((regno >= 0
|
| 6818 |
|
|
&& true_regnum (SET_SRC (pat)) == regno
|
| 6819 |
|
|
&& (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
|
| 6820 |
|
|
||
|
| 6821 |
|
|
(regno >= 0
|
| 6822 |
|
|
&& true_regnum (SET_DEST (pat)) == regno
|
| 6823 |
|
|
&& (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0)
|
| 6824 |
|
|
||
|
| 6825 |
|
|
(goal_const && rtx_equal_p (SET_SRC (pat), goal)
|
| 6826 |
|
|
/* When looking for stack pointer + const,
|
| 6827 |
|
|
make sure we don't use a stack adjust. */
|
| 6828 |
|
|
&& !reg_overlap_mentioned_for_reload_p (SET_DEST (pat), goal)
|
| 6829 |
|
|
&& (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
|
| 6830 |
|
|
|| (goal_mem
|
| 6831 |
|
|
&& (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0
|
| 6832 |
|
|
&& rtx_renumbered_equal_p (goal, SET_SRC (pat)))
|
| 6833 |
|
|
|| (goal_mem
|
| 6834 |
|
|
&& (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0
|
| 6835 |
|
|
&& rtx_renumbered_equal_p (goal, SET_DEST (pat)))
|
| 6836 |
|
|
/* If we are looking for a constant,
|
| 6837 |
|
|
and something equivalent to that constant was copied
|
| 6838 |
|
|
into a reg, we can use that reg. */
|
| 6839 |
|
|
|| (goal_const && REG_NOTES (p) != 0
|
| 6840 |
|
|
&& (tem = find_reg_note (p, REG_EQUIV, NULL_RTX))
|
| 6841 |
|
|
&& ((rtx_equal_p (XEXP (tem, 0), goal)
|
| 6842 |
|
|
&& (valueno
|
| 6843 |
|
|
= true_regnum (valtry = SET_DEST (pat))) >= 0)
|
| 6844 |
|
|
|| (REG_P (SET_DEST (pat))
|
| 6845 |
|
|
&& GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
|
| 6846 |
|
|
&& SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
|
| 6847 |
|
|
&& CONST_INT_P (goal)
|
| 6848 |
|
|
&& 0 != (goaltry
|
| 6849 |
|
|
= operand_subword (XEXP (tem, 0), 0, 0,
|
| 6850 |
|
|
VOIDmode))
|
| 6851 |
|
|
&& rtx_equal_p (goal, goaltry)
|
| 6852 |
|
|
&& (valtry
|
| 6853 |
|
|
= operand_subword (SET_DEST (pat), 0, 0,
|
| 6854 |
|
|
VOIDmode))
|
| 6855 |
|
|
&& (valueno = true_regnum (valtry)) >= 0)))
|
| 6856 |
|
|
|| (goal_const && (tem = find_reg_note (p, REG_EQUIV,
|
| 6857 |
|
|
NULL_RTX))
|
| 6858 |
|
|
&& REG_P (SET_DEST (pat))
|
| 6859 |
|
|
&& GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
|
| 6860 |
|
|
&& SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
|
| 6861 |
|
|
&& CONST_INT_P (goal)
|
| 6862 |
|
|
&& 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0,
|
| 6863 |
|
|
VOIDmode))
|
| 6864 |
|
|
&& rtx_equal_p (goal, goaltry)
|
| 6865 |
|
|
&& (valtry
|
| 6866 |
|
|
= operand_subword (SET_DEST (pat), 1, 0, VOIDmode))
|
| 6867 |
|
|
&& (valueno = true_regnum (valtry)) >= 0)))
|
| 6868 |
|
|
{
|
| 6869 |
|
|
if (other >= 0)
|
| 6870 |
|
|
{
|
| 6871 |
|
|
if (valueno != other)
|
| 6872 |
|
|
continue;
|
| 6873 |
|
|
}
|
| 6874 |
|
|
else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER)
|
| 6875 |
|
|
continue;
|
| 6876 |
|
|
else if (!in_hard_reg_set_p (reg_class_contents[(int) rclass],
|
| 6877 |
|
|
mode, valueno))
|
| 6878 |
|
|
continue;
|
| 6879 |
|
|
value = valtry;
|
| 6880 |
|
|
where = p;
|
| 6881 |
|
|
break;
|
| 6882 |
|
|
}
|
| 6883 |
|
|
}
|
| 6884 |
|
|
}
|
| 6885 |
|
|
|
| 6886 |
|
|
/* We found a previous insn copying GOAL into a suitable other reg VALUE
|
| 6887 |
|
|
(or copying VALUE into GOAL, if GOAL is also a register).
|
| 6888 |
|
|
Now verify that VALUE is really valid. */
|
| 6889 |
|
|
|
| 6890 |
|
|
/* VALUENO is the register number of VALUE; a hard register. */
|
| 6891 |
|
|
|
| 6892 |
|
|
/* Don't try to re-use something that is killed in this insn. We want
|
| 6893 |
|
|
to be able to trust REG_UNUSED notes. */
|
| 6894 |
|
|
if (REG_NOTES (where) != 0 && find_reg_note (where, REG_UNUSED, value))
|
| 6895 |
|
|
return 0;
|
| 6896 |
|
|
|
| 6897 |
|
|
/* If we propose to get the value from the stack pointer or if GOAL is
|
| 6898 |
|
|
a MEM based on the stack pointer, we need a stable SP. */
|
| 6899 |
|
|
if (valueno == STACK_POINTER_REGNUM || regno == STACK_POINTER_REGNUM
|
| 6900 |
|
|
|| (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx,
|
| 6901 |
|
|
goal)))
|
| 6902 |
|
|
need_stable_sp = 1;
|
| 6903 |
|
|
|
| 6904 |
|
|
/* Reject VALUE if the copy-insn moved the wrong sort of datum. */
|
| 6905 |
|
|
if (GET_MODE (value) != mode)
|
| 6906 |
|
|
return 0;
|
| 6907 |
|
|
|
| 6908 |
|
|
/* Reject VALUE if it was loaded from GOAL
|
| 6909 |
|
|
and is also a register that appears in the address of GOAL. */
|
| 6910 |
|
|
|
| 6911 |
|
|
if (goal_mem && value == SET_DEST (single_set (where))
|
| 6912 |
|
|
&& refers_to_regno_for_reload_p (valueno, end_hard_regno (mode, valueno),
|
| 6913 |
|
|
goal, (rtx*) 0))
|
| 6914 |
|
|
return 0;
|
| 6915 |
|
|
|
| 6916 |
|
|
/* Reject registers that overlap GOAL. */
|
| 6917 |
|
|
|
| 6918 |
|
|
if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
|
| 6919 |
|
|
nregs = hard_regno_nregs[regno][mode];
|
| 6920 |
|
|
else
|
| 6921 |
|
|
nregs = 1;
|
| 6922 |
|
|
valuenregs = hard_regno_nregs[valueno][mode];
|
| 6923 |
|
|
|
| 6924 |
|
|
if (!goal_mem && !goal_const
|
| 6925 |
|
|
&& regno + nregs > valueno && regno < valueno + valuenregs)
|
| 6926 |
|
|
return 0;
|
| 6927 |
|
|
|
| 6928 |
|
|
/* Reject VALUE if it is one of the regs reserved for reloads.
|
| 6929 |
|
|
Reload1 knows how to reuse them anyway, and it would get
|
| 6930 |
|
|
confused if we allocated one without its knowledge.
|
| 6931 |
|
|
(Now that insns introduced by reload are ignored above,
|
| 6932 |
|
|
this case shouldn't happen, but I'm not positive.) */
|
| 6933 |
|
|
|
| 6934 |
|
|
if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1)
|
| 6935 |
|
|
{
|
| 6936 |
|
|
int i;
|
| 6937 |
|
|
for (i = 0; i < valuenregs; ++i)
|
| 6938 |
|
|
if (reload_reg_p[valueno + i] >= 0)
|
| 6939 |
|
|
return 0;
|
| 6940 |
|
|
}
|
| 6941 |
|
|
|
| 6942 |
|
|
/* Reject VALUE if it is a register being used for an input reload
|
| 6943 |
|
|
even if it is not one of those reserved. */
|
| 6944 |
|
|
|
| 6945 |
|
|
if (reload_reg_p != 0)
|
| 6946 |
|
|
{
|
| 6947 |
|
|
int i;
|
| 6948 |
|
|
for (i = 0; i < n_reloads; i++)
|
| 6949 |
|
|
if (rld[i].reg_rtx != 0 && rld[i].in)
|
| 6950 |
|
|
{
|
| 6951 |
|
|
int regno1 = REGNO (rld[i].reg_rtx);
|
| 6952 |
|
|
int nregs1 = hard_regno_nregs[regno1]
|
| 6953 |
|
|
[GET_MODE (rld[i].reg_rtx)];
|
| 6954 |
|
|
if (regno1 < valueno + valuenregs
|
| 6955 |
|
|
&& regno1 + nregs1 > valueno)
|
| 6956 |
|
|
return 0;
|
| 6957 |
|
|
}
|
| 6958 |
|
|
}
|
| 6959 |
|
|
|
| 6960 |
|
|
if (goal_mem)
|
| 6961 |
|
|
/* We must treat frame pointer as varying here,
|
| 6962 |
|
|
since it can vary--in a nonlocal goto as generated by expand_goto. */
|
| 6963 |
|
|
goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0));
|
| 6964 |
|
|
|
| 6965 |
|
|
/* Now verify that the values of GOAL and VALUE remain unaltered
|
| 6966 |
|
|
until INSN is reached. */
|
| 6967 |
|
|
|
| 6968 |
|
|
p = insn;
|
| 6969 |
|
|
while (1)
|
| 6970 |
|
|
{
|
| 6971 |
|
|
p = PREV_INSN (p);
|
| 6972 |
|
|
if (p == where)
|
| 6973 |
|
|
return value;
|
| 6974 |
|
|
|
| 6975 |
|
|
/* Don't trust the conversion past a function call
|
| 6976 |
|
|
if either of the two is in a call-clobbered register, or memory. */
|
| 6977 |
|
|
if (CALL_P (p))
|
| 6978 |
|
|
{
|
| 6979 |
|
|
int i;
|
| 6980 |
|
|
|
| 6981 |
|
|
if (goal_mem || need_stable_sp)
|
| 6982 |
|
|
return 0;
|
| 6983 |
|
|
|
| 6984 |
|
|
if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
|
| 6985 |
|
|
for (i = 0; i < nregs; ++i)
|
| 6986 |
|
|
if (call_used_regs[regno + i]
|
| 6987 |
|
|
|| HARD_REGNO_CALL_PART_CLOBBERED (regno + i, mode))
|
| 6988 |
|
|
return 0;
|
| 6989 |
|
|
|
| 6990 |
|
|
if (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER)
|
| 6991 |
|
|
for (i = 0; i < valuenregs; ++i)
|
| 6992 |
|
|
if (call_used_regs[valueno + i]
|
| 6993 |
|
|
|| HARD_REGNO_CALL_PART_CLOBBERED (valueno + i, mode))
|
| 6994 |
|
|
return 0;
|
| 6995 |
|
|
}
|
| 6996 |
|
|
|
| 6997 |
|
|
if (INSN_P (p))
|
| 6998 |
|
|
{
|
| 6999 |
|
|
pat = PATTERN (p);
|
| 7000 |
|
|
|
| 7001 |
|
|
/* Watch out for unspec_volatile, and volatile asms. */
|
| 7002 |
|
|
if (volatile_insn_p (pat))
|
| 7003 |
|
|
return 0;
|
| 7004 |
|
|
|
| 7005 |
|
|
/* If this insn P stores in either GOAL or VALUE, return 0.
|
| 7006 |
|
|
If GOAL is a memory ref and this insn writes memory, return 0.
|
| 7007 |
|
|
If GOAL is a memory ref and its address is not constant,
|
| 7008 |
|
|
and this insn P changes a register used in GOAL, return 0. */
|
| 7009 |
|
|
|
| 7010 |
|
|
if (GET_CODE (pat) == COND_EXEC)
|
| 7011 |
|
|
pat = COND_EXEC_CODE (pat);
|
| 7012 |
|
|
if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
|
| 7013 |
|
|
{
|
| 7014 |
|
|
rtx dest = SET_DEST (pat);
|
| 7015 |
|
|
while (GET_CODE (dest) == SUBREG
|
| 7016 |
|
|
|| GET_CODE (dest) == ZERO_EXTRACT
|
| 7017 |
|
|
|| GET_CODE (dest) == STRICT_LOW_PART)
|
| 7018 |
|
|
dest = XEXP (dest, 0);
|
| 7019 |
|
|
if (REG_P (dest))
|
| 7020 |
|
|
{
|
| 7021 |
|
|
int xregno = REGNO (dest);
|
| 7022 |
|
|
int xnregs;
|
| 7023 |
|
|
if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
|
| 7024 |
|
|
xnregs = hard_regno_nregs[xregno][GET_MODE (dest)];
|
| 7025 |
|
|
else
|
| 7026 |
|
|
xnregs = 1;
|
| 7027 |
|
|
if (xregno < regno + nregs && xregno + xnregs > regno)
|
| 7028 |
|
|
return 0;
|
| 7029 |
|
|
if (xregno < valueno + valuenregs
|
| 7030 |
|
|
&& xregno + xnregs > valueno)
|
| 7031 |
|
|
return 0;
|
| 7032 |
|
|
if (goal_mem_addr_varies
|
| 7033 |
|
|
&& reg_overlap_mentioned_for_reload_p (dest, goal))
|
| 7034 |
|
|
return 0;
|
| 7035 |
|
|
if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
|
| 7036 |
|
|
return 0;
|
| 7037 |
|
|
}
|
| 7038 |
|
|
else if (goal_mem && MEM_P (dest)
|
| 7039 |
|
|
&& ! push_operand (dest, GET_MODE (dest)))
|
| 7040 |
|
|
return 0;
|
| 7041 |
|
|
else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
|
| 7042 |
|
|
&& reg_equiv_memory_loc[regno] != 0)
|
| 7043 |
|
|
return 0;
|
| 7044 |
|
|
else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
|
| 7045 |
|
|
return 0;
|
| 7046 |
|
|
}
|
| 7047 |
|
|
else if (GET_CODE (pat) == PARALLEL)
|
| 7048 |
|
|
{
|
| 7049 |
|
|
int i;
|
| 7050 |
|
|
for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
|
| 7051 |
|
|
{
|
| 7052 |
|
|
rtx v1 = XVECEXP (pat, 0, i);
|
| 7053 |
|
|
if (GET_CODE (v1) == COND_EXEC)
|
| 7054 |
|
|
v1 = COND_EXEC_CODE (v1);
|
| 7055 |
|
|
if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
|
| 7056 |
|
|
{
|
| 7057 |
|
|
rtx dest = SET_DEST (v1);
|
| 7058 |
|
|
while (GET_CODE (dest) == SUBREG
|
| 7059 |
|
|
|| GET_CODE (dest) == ZERO_EXTRACT
|
| 7060 |
|
|
|| GET_CODE (dest) == STRICT_LOW_PART)
|
| 7061 |
|
|
dest = XEXP (dest, 0);
|
| 7062 |
|
|
if (REG_P (dest))
|
| 7063 |
|
|
{
|
| 7064 |
|
|
int xregno = REGNO (dest);
|
| 7065 |
|
|
int xnregs;
|
| 7066 |
|
|
if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
|
| 7067 |
|
|
xnregs = hard_regno_nregs[xregno][GET_MODE (dest)];
|
| 7068 |
|
|
else
|
| 7069 |
|
|
xnregs = 1;
|
| 7070 |
|
|
if (xregno < regno + nregs
|
| 7071 |
|
|
&& xregno + xnregs > regno)
|
| 7072 |
|
|
return 0;
|
| 7073 |
|
|
if (xregno < valueno + valuenregs
|
| 7074 |
|
|
&& xregno + xnregs > valueno)
|
| 7075 |
|
|
return 0;
|
| 7076 |
|
|
if (goal_mem_addr_varies
|
| 7077 |
|
|
&& reg_overlap_mentioned_for_reload_p (dest,
|
| 7078 |
|
|
goal))
|
| 7079 |
|
|
return 0;
|
| 7080 |
|
|
if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
|
| 7081 |
|
|
return 0;
|
| 7082 |
|
|
}
|
| 7083 |
|
|
else if (goal_mem && MEM_P (dest)
|
| 7084 |
|
|
&& ! push_operand (dest, GET_MODE (dest)))
|
| 7085 |
|
|
return 0;
|
| 7086 |
|
|
else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
|
| 7087 |
|
|
&& reg_equiv_memory_loc[regno] != 0)
|
| 7088 |
|
|
return 0;
|
| 7089 |
|
|
else if (need_stable_sp
|
| 7090 |
|
|
&& push_operand (dest, GET_MODE (dest)))
|
| 7091 |
|
|
return 0;
|
| 7092 |
|
|
}
|
| 7093 |
|
|
}
|
| 7094 |
|
|
}
|
| 7095 |
|
|
|
| 7096 |
|
|
if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p))
|
| 7097 |
|
|
{
|
| 7098 |
|
|
rtx link;
|
| 7099 |
|
|
|
| 7100 |
|
|
for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0;
|
| 7101 |
|
|
link = XEXP (link, 1))
|
| 7102 |
|
|
{
|
| 7103 |
|
|
pat = XEXP (link, 0);
|
| 7104 |
|
|
if (GET_CODE (pat) == CLOBBER)
|
| 7105 |
|
|
{
|
| 7106 |
|
|
rtx dest = SET_DEST (pat);
|
| 7107 |
|
|
|
| 7108 |
|
|
if (REG_P (dest))
|
| 7109 |
|
|
{
|
| 7110 |
|
|
int xregno = REGNO (dest);
|
| 7111 |
|
|
int xnregs
|
| 7112 |
|
|
= hard_regno_nregs[xregno][GET_MODE (dest)];
|
| 7113 |
|
|
|
| 7114 |
|
|
if (xregno < regno + nregs
|
| 7115 |
|
|
&& xregno + xnregs > regno)
|
| 7116 |
|
|
return 0;
|
| 7117 |
|
|
else if (xregno < valueno + valuenregs
|
| 7118 |
|
|
&& xregno + xnregs > valueno)
|
| 7119 |
|
|
return 0;
|
| 7120 |
|
|
else if (goal_mem_addr_varies
|
| 7121 |
|
|
&& reg_overlap_mentioned_for_reload_p (dest,
|
| 7122 |
|
|
goal))
|
| 7123 |
|
|
return 0;
|
| 7124 |
|
|
}
|
| 7125 |
|
|
|
| 7126 |
|
|
else if (goal_mem && MEM_P (dest)
|
| 7127 |
|
|
&& ! push_operand (dest, GET_MODE (dest)))
|
| 7128 |
|
|
return 0;
|
| 7129 |
|
|
else if (need_stable_sp
|
| 7130 |
|
|
&& push_operand (dest, GET_MODE (dest)))
|
| 7131 |
|
|
return 0;
|
| 7132 |
|
|
}
|
| 7133 |
|
|
}
|
| 7134 |
|
|
}
|
| 7135 |
|
|
|
| 7136 |
|
|
#ifdef AUTO_INC_DEC
|
| 7137 |
|
|
/* If this insn auto-increments or auto-decrements
|
| 7138 |
|
|
either regno or valueno, return 0 now.
|
| 7139 |
|
|
If GOAL is a memory ref and its address is not constant,
|
| 7140 |
|
|
and this insn P increments a register used in GOAL, return 0. */
|
| 7141 |
|
|
{
|
| 7142 |
|
|
rtx link;
|
| 7143 |
|
|
|
| 7144 |
|
|
for (link = REG_NOTES (p); link; link = XEXP (link, 1))
|
| 7145 |
|
|
if (REG_NOTE_KIND (link) == REG_INC
|
| 7146 |
|
|
&& REG_P (XEXP (link, 0)))
|
| 7147 |
|
|
{
|
| 7148 |
|
|
int incno = REGNO (XEXP (link, 0));
|
| 7149 |
|
|
if (incno < regno + nregs && incno >= regno)
|
| 7150 |
|
|
return 0;
|
| 7151 |
|
|
if (incno < valueno + valuenregs && incno >= valueno)
|
| 7152 |
|
|
return 0;
|
| 7153 |
|
|
if (goal_mem_addr_varies
|
| 7154 |
|
|
&& reg_overlap_mentioned_for_reload_p (XEXP (link, 0),
|
| 7155 |
|
|
goal))
|
| 7156 |
|
|
return 0;
|
| 7157 |
|
|
}
|
| 7158 |
|
|
}
|
| 7159 |
|
|
#endif
|
| 7160 |
|
|
}
|
| 7161 |
|
|
}
|
| 7162 |
|
|
}
|
| 7163 |
|
|
|
| 7164 |
|
|
/* Find a place where INCED appears in an increment or decrement operator
|
| 7165 |
|
|
within X, and return the amount INCED is incremented or decremented by.
|
| 7166 |
|
|
The value is always positive. */
|
| 7167 |
|
|
|
| 7168 |
|
|
static int
|
| 7169 |
|
|
find_inc_amount (rtx x, rtx inced)
|
| 7170 |
|
|
{
|
| 7171 |
|
|
enum rtx_code code = GET_CODE (x);
|
| 7172 |
|
|
const char *fmt;
|
| 7173 |
|
|
int i;
|
| 7174 |
|
|
|
| 7175 |
|
|
if (code == MEM)
|
| 7176 |
|
|
{
|
| 7177 |
|
|
rtx addr = XEXP (x, 0);
|
| 7178 |
|
|
if ((GET_CODE (addr) == PRE_DEC
|
| 7179 |
|
|
|| GET_CODE (addr) == POST_DEC
|
| 7180 |
|
|
|| GET_CODE (addr) == PRE_INC
|
| 7181 |
|
|
|| GET_CODE (addr) == POST_INC)
|
| 7182 |
|
|
&& XEXP (addr, 0) == inced)
|
| 7183 |
|
|
return GET_MODE_SIZE (GET_MODE (x));
|
| 7184 |
|
|
else if ((GET_CODE (addr) == PRE_MODIFY
|
| 7185 |
|
|
|| GET_CODE (addr) == POST_MODIFY)
|
| 7186 |
|
|
&& GET_CODE (XEXP (addr, 1)) == PLUS
|
| 7187 |
|
|
&& XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
|
| 7188 |
|
|
&& XEXP (addr, 0) == inced
|
| 7189 |
|
|
&& CONST_INT_P (XEXP (XEXP (addr, 1), 1)))
|
| 7190 |
|
|
{
|
| 7191 |
|
|
i = INTVAL (XEXP (XEXP (addr, 1), 1));
|
| 7192 |
|
|
return i < 0 ? -i : i;
|
| 7193 |
|
|
}
|
| 7194 |
|
|
}
|
| 7195 |
|
|
|
| 7196 |
|
|
fmt = GET_RTX_FORMAT (code);
|
| 7197 |
|
|
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
| 7198 |
|
|
{
|
| 7199 |
|
|
if (fmt[i] == 'e')
|
| 7200 |
|
|
{
|
| 7201 |
|
|
int tem = find_inc_amount (XEXP (x, i), inced);
|
| 7202 |
|
|
if (tem != 0)
|
| 7203 |
|
|
return tem;
|
| 7204 |
|
|
}
|
| 7205 |
|
|
if (fmt[i] == 'E')
|
| 7206 |
|
|
{
|
| 7207 |
|
|
int j;
|
| 7208 |
|
|
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
| 7209 |
|
|
{
|
| 7210 |
|
|
int tem = find_inc_amount (XVECEXP (x, i, j), inced);
|
| 7211 |
|
|
if (tem != 0)
|
| 7212 |
|
|
return tem;
|
| 7213 |
|
|
}
|
| 7214 |
|
|
}
|
| 7215 |
|
|
}
|
| 7216 |
|
|
|
| 7217 |
|
|
return 0;
|
| 7218 |
|
|
}
|
| 7219 |
|
|
|
| 7220 |
|
|
/* Return 1 if registers from REGNO to ENDREGNO are the subjects of a
|
| 7221 |
|
|
REG_INC note in insn INSN. REGNO must refer to a hard register. */
|
| 7222 |
|
|
|
| 7223 |
|
|
#ifdef AUTO_INC_DEC
|
| 7224 |
|
|
static int
|
| 7225 |
|
|
reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
|
| 7226 |
|
|
rtx insn)
|
| 7227 |
|
|
{
|
| 7228 |
|
|
rtx link;
|
| 7229 |
|
|
|
| 7230 |
|
|
gcc_assert (insn);
|
| 7231 |
|
|
|
| 7232 |
|
|
if (! INSN_P (insn))
|
| 7233 |
|
|
return 0;
|
| 7234 |
|
|
|
| 7235 |
|
|
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
|
| 7236 |
|
|
if (REG_NOTE_KIND (link) == REG_INC)
|
| 7237 |
|
|
{
|
| 7238 |
|
|
unsigned int test = (int) REGNO (XEXP (link, 0));
|
| 7239 |
|
|
if (test >= regno && test < endregno)
|
| 7240 |
|
|
return 1;
|
| 7241 |
|
|
}
|
| 7242 |
|
|
return 0;
|
| 7243 |
|
|
}
|
| 7244 |
|
|
#else
|
| 7245 |
|
|
|
| 7246 |
|
|
#define reg_inc_found_and_valid_p(regno,endregno,insn) 0
|
| 7247 |
|
|
|
| 7248 |
|
|
#endif
|
| 7249 |
|
|
|
| 7250 |
|
|
/* Return 1 if register REGNO is the subject of a clobber in insn INSN.
|
| 7251 |
|
|
If SETS is 1, also consider SETs. If SETS is 2, enable checking
|
| 7252 |
|
|
REG_INC. REGNO must refer to a hard register. */
|
| 7253 |
|
|
|
| 7254 |
|
|
int
|
| 7255 |
|
|
regno_clobbered_p (unsigned int regno, rtx insn, enum machine_mode mode,
|
| 7256 |
|
|
int sets)
|
| 7257 |
|
|
{
|
| 7258 |
|
|
unsigned int nregs, endregno;
|
| 7259 |
|
|
|
| 7260 |
|
|
/* regno must be a hard register. */
|
| 7261 |
|
|
gcc_assert (regno < FIRST_PSEUDO_REGISTER);
|
| 7262 |
|
|
|
| 7263 |
|
|
nregs = hard_regno_nregs[regno][mode];
|
| 7264 |
|
|
endregno = regno + nregs;
|
| 7265 |
|
|
|
| 7266 |
|
|
if ((GET_CODE (PATTERN (insn)) == CLOBBER
|
| 7267 |
|
|
|| (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
|
| 7268 |
|
|
&& REG_P (XEXP (PATTERN (insn), 0)))
|
| 7269 |
|
|
{
|
| 7270 |
|
|
unsigned int test = REGNO (XEXP (PATTERN (insn), 0));
|
| 7271 |
|
|
|
| 7272 |
|
|
return test >= regno && test < endregno;
|
| 7273 |
|
|
}
|
| 7274 |
|
|
|
| 7275 |
|
|
if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn))
|
| 7276 |
|
|
return 1;
|
| 7277 |
|
|
|
| 7278 |
|
|
if (GET_CODE (PATTERN (insn)) == PARALLEL)
|
| 7279 |
|
|
{
|
| 7280 |
|
|
int i = XVECLEN (PATTERN (insn), 0) - 1;
|
| 7281 |
|
|
|
| 7282 |
|
|
for (; i >= 0; i--)
|
| 7283 |
|
|
{
|
| 7284 |
|
|
rtx elt = XVECEXP (PATTERN (insn), 0, i);
|
| 7285 |
|
|
if ((GET_CODE (elt) == CLOBBER
|
| 7286 |
|
|
|| (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
|
| 7287 |
|
|
&& REG_P (XEXP (elt, 0)))
|
| 7288 |
|
|
{
|
| 7289 |
|
|
unsigned int test = REGNO (XEXP (elt, 0));
|
| 7290 |
|
|
|
| 7291 |
|
|
if (test >= regno && test < endregno)
|
| 7292 |
|
|
return 1;
|
| 7293 |
|
|
}
|
| 7294 |
|
|
if (sets == 2
|
| 7295 |
|
|
&& reg_inc_found_and_valid_p (regno, endregno, elt))
|
| 7296 |
|
|
return 1;
|
| 7297 |
|
|
}
|
| 7298 |
|
|
}
|
| 7299 |
|
|
|
| 7300 |
|
|
return 0;
|
| 7301 |
|
|
}
|
| 7302 |
|
|
|
| 7303 |
|
|
/* Find the low part, with mode MODE, of a hard regno RELOADREG. */
|
| 7304 |
|
|
rtx
|
| 7305 |
|
|
reload_adjust_reg_for_mode (rtx reloadreg, enum machine_mode mode)
|
| 7306 |
|
|
{
|
| 7307 |
|
|
int regno;
|
| 7308 |
|
|
|
| 7309 |
|
|
if (GET_MODE (reloadreg) == mode)
|
| 7310 |
|
|
return reloadreg;
|
| 7311 |
|
|
|
| 7312 |
|
|
regno = REGNO (reloadreg);
|
| 7313 |
|
|
|
| 7314 |
|
|
if (WORDS_BIG_ENDIAN)
|
| 7315 |
|
|
regno += (int) hard_regno_nregs[regno][GET_MODE (reloadreg)]
|
| 7316 |
|
|
- (int) hard_regno_nregs[regno][mode];
|
| 7317 |
|
|
|
| 7318 |
|
|
return gen_rtx_REG (mode, regno);
|
| 7319 |
|
|
}
|
| 7320 |
|
|
|
| 7321 |
|
|
static const char *const reload_when_needed_name[] =
|
| 7322 |
|
|
{
|
| 7323 |
|
|
"RELOAD_FOR_INPUT",
|
| 7324 |
|
|
"RELOAD_FOR_OUTPUT",
|
| 7325 |
|
|
"RELOAD_FOR_INSN",
|
| 7326 |
|
|
"RELOAD_FOR_INPUT_ADDRESS",
|
| 7327 |
|
|
"RELOAD_FOR_INPADDR_ADDRESS",
|
| 7328 |
|
|
"RELOAD_FOR_OUTPUT_ADDRESS",
|
| 7329 |
|
|
"RELOAD_FOR_OUTADDR_ADDRESS",
|
| 7330 |
|
|
"RELOAD_FOR_OPERAND_ADDRESS",
|
| 7331 |
|
|
"RELOAD_FOR_OPADDR_ADDR",
|
| 7332 |
|
|
"RELOAD_OTHER",
|
| 7333 |
|
|
"RELOAD_FOR_OTHER_ADDRESS"
|
| 7334 |
|
|
};
|
| 7335 |
|
|
|
| 7336 |
|
|
/* These functions are used to print the variables set by 'find_reloads' */
|
| 7337 |
|
|
|
| 7338 |
|
|
void
|
| 7339 |
|
|
debug_reload_to_stream (FILE *f)
|
| 7340 |
|
|
{
|
| 7341 |
|
|
int r;
|
| 7342 |
|
|
const char *prefix;
|
| 7343 |
|
|
|
| 7344 |
|
|
if (! f)
|
| 7345 |
|
|
f = stderr;
|
| 7346 |
|
|
for (r = 0; r < n_reloads; r++)
|
| 7347 |
|
|
{
|
| 7348 |
|
|
fprintf (f, "Reload %d: ", r);
|
| 7349 |
|
|
|
| 7350 |
|
|
if (rld[r].in != 0)
|
| 7351 |
|
|
{
|
| 7352 |
|
|
fprintf (f, "reload_in (%s) = ",
|
| 7353 |
|
|
GET_MODE_NAME (rld[r].inmode));
|
| 7354 |
|
|
print_inline_rtx (f, rld[r].in, 24);
|
| 7355 |
|
|
fprintf (f, "\n\t");
|
| 7356 |
|
|
}
|
| 7357 |
|
|
|
| 7358 |
|
|
if (rld[r].out != 0)
|
| 7359 |
|
|
{
|
| 7360 |
|
|
fprintf (f, "reload_out (%s) = ",
|
| 7361 |
|
|
GET_MODE_NAME (rld[r].outmode));
|
| 7362 |
|
|
print_inline_rtx (f, rld[r].out, 24);
|
| 7363 |
|
|
fprintf (f, "\n\t");
|
| 7364 |
|
|
}
|
| 7365 |
|
|
|
| 7366 |
|
|
fprintf (f, "%s, ", reg_class_names[(int) rld[r].rclass]);
|
| 7367 |
|
|
|
| 7368 |
|
|
fprintf (f, "%s (opnum = %d)",
|
| 7369 |
|
|
reload_when_needed_name[(int) rld[r].when_needed],
|
| 7370 |
|
|
rld[r].opnum);
|
| 7371 |
|
|
|
| 7372 |
|
|
if (rld[r].optional)
|
| 7373 |
|
|
fprintf (f, ", optional");
|
| 7374 |
|
|
|
| 7375 |
|
|
if (rld[r].nongroup)
|
| 7376 |
|
|
fprintf (f, ", nongroup");
|
| 7377 |
|
|
|
| 7378 |
|
|
if (rld[r].inc != 0)
|
| 7379 |
|
|
fprintf (f, ", inc by %d", rld[r].inc);
|
| 7380 |
|
|
|
| 7381 |
|
|
if (rld[r].nocombine)
|
| 7382 |
|
|
fprintf (f, ", can't combine");
|
| 7383 |
|
|
|
| 7384 |
|
|
if (rld[r].secondary_p)
|
| 7385 |
|
|
fprintf (f, ", secondary_reload_p");
|
| 7386 |
|
|
|
| 7387 |
|
|
if (rld[r].in_reg != 0)
|
| 7388 |
|
|
{
|
| 7389 |
|
|
fprintf (f, "\n\treload_in_reg: ");
|
| 7390 |
|
|
print_inline_rtx (f, rld[r].in_reg, 24);
|
| 7391 |
|
|
}
|
| 7392 |
|
|
|
| 7393 |
|
|
if (rld[r].out_reg != 0)
|
| 7394 |
|
|
{
|
| 7395 |
|
|
fprintf (f, "\n\treload_out_reg: ");
|
| 7396 |
|
|
print_inline_rtx (f, rld[r].out_reg, 24);
|
| 7397 |
|
|
}
|
| 7398 |
|
|
|
| 7399 |
|
|
if (rld[r].reg_rtx != 0)
|
| 7400 |
|
|
{
|
| 7401 |
|
|
fprintf (f, "\n\treload_reg_rtx: ");
|
| 7402 |
|
|
print_inline_rtx (f, rld[r].reg_rtx, 24);
|
| 7403 |
|
|
}
|
| 7404 |
|
|
|
| 7405 |
|
|
prefix = "\n\t";
|
| 7406 |
|
|
if (rld[r].secondary_in_reload != -1)
|
| 7407 |
|
|
{
|
| 7408 |
|
|
fprintf (f, "%ssecondary_in_reload = %d",
|
| 7409 |
|
|
prefix, rld[r].secondary_in_reload);
|
| 7410 |
|
|
prefix = ", ";
|
| 7411 |
|
|
}
|
| 7412 |
|
|
|
| 7413 |
|
|
if (rld[r].secondary_out_reload != -1)
|
| 7414 |
|
|
fprintf (f, "%ssecondary_out_reload = %d\n",
|
| 7415 |
|
|
prefix, rld[r].secondary_out_reload);
|
| 7416 |
|
|
|
| 7417 |
|
|
prefix = "\n\t";
|
| 7418 |
|
|
if (rld[r].secondary_in_icode != CODE_FOR_nothing)
|
| 7419 |
|
|
{
|
| 7420 |
|
|
fprintf (f, "%ssecondary_in_icode = %s", prefix,
|
| 7421 |
|
|
insn_data[rld[r].secondary_in_icode].name);
|
| 7422 |
|
|
prefix = ", ";
|
| 7423 |
|
|
}
|
| 7424 |
|
|
|
| 7425 |
|
|
if (rld[r].secondary_out_icode != CODE_FOR_nothing)
|
| 7426 |
|
|
fprintf (f, "%ssecondary_out_icode = %s", prefix,
|
| 7427 |
|
|
insn_data[rld[r].secondary_out_icode].name);
|
| 7428 |
|
|
|
| 7429 |
|
|
fprintf (f, "\n");
|
| 7430 |
|
|
}
|
| 7431 |
|
|
}
|
| 7432 |
|
|
|
| 7433 |
|
|
void
|
| 7434 |
|
|
debug_reload (void)
|
| 7435 |
|
|
{
|
| 7436 |
|
|
debug_reload_to_stream (stderr);
|
| 7437 |
|
|
}
|