OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20000804-1.c] - Blame information for rev 297

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 297 jeremybenn
/* This does not work on m68hc11 or h8300 due to the use of an asm
2
   statement to force a 'long long' (64-bits) to go in a register.  */
3
/* { dg-do assemble } */
4
/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ilp32 && { ! nonpic } } } { "*" } { "" } } */
5
/* { dg-skip-if "No 64-bit registers" { m32c-*-* } { "*" } { "" } } */
6
/* { dg-xfail-if "" { m6811-*-* m6812-*-* h8300-*-* } { "*" } { "" } } */
7
 
8
/* Copyright (C) 2000, 2003 Free Software Foundation */
9
__complex__ long long f ()
10
{
11
  int i[99];
12
  __complex__ long long v;
13
 
14
  v += f ();
15
  asm("": "+r" (v) : "r" (0), "r" (1));
16
  v = 2;
17
  return v;
18
  g (&v);
19
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.