OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.c-torture/] [unsorted/] [SIset.c] - Blame information for rev 414

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 297 jeremybenn 
#define E0 ((type *)10000000)
2 
#define reg0 r0
3 
#define indreg0 (*p0)
4 
#define imm0 22
5 
#define limm0 ((type)(int)&glob0)
6 
#define adr0 (*E0)
7 
#define adrreg0 (p0[10000000])
8 
#define adrx0 (E0[x0])
9 
#define regx0 (p0[x0])
10 
 
11 
#define E1 ((type *)11111111)
12 
#define reg1 r1
13 
#define indreg1 (*p1)
14 
#define imm1 33
15 
#define limm1 ((type)(int)&glob1)
16 
#define adr1 (*E1)
17 
#define adrreg1 (p1[1111111/4])
18 
#define adrx1 (E1[x1])
19 
#define regx1 (p1[x1])
20 
 
21 
int glob0, glob1;
22 
 
23 
#define type int
24 
 
25 
reg0reg1_set (r0, r1, x0, x1, p0, p1)
26 
type r0, r1;  type *p0, *p1;
27 
{reg0 = reg1;  }
28 
 
29 
reg0indreg1_set (r0, r1, x0, x1, p0, p1)
30 
type r0, r1;  type *p0, *p1;
31 
{reg0 = indreg1;  }
32 
 
33 
reg0imm1_set (r0, r1, x0, x1, p0, p1)
34 
type r0, r1;  type *p0, *p1;
35 
{reg0 = imm1;  }
36 
 
37 
reg0limm1_set (r0, r1, x0, x1, p0, p1)
38 
type r0, r1;  type *p0, *p1;
39 
{reg0 = limm1;  }
40 
 
41 
reg0adr1_set (r0, r1, x0, x1, p0, p1)
42 
type r0, r1;  type *p0, *p1;
43 
{reg0 = adr1;  }
44 
 
45 
reg0adrreg1_set (r0, r1, x0, x1, p0, p1)
46 
type r0, r1;  type *p0, *p1;
47 
{reg0 = adrreg1;  }
48 
 
49 
reg0adrx1_set (r0, r1, x0, x1, p0, p1)
50 
type r0, r1;  type *p0, *p1;
51 
{reg0 = adrx1;  }
52 
 
53 
reg0regx1_set (r0, r1, x0, x1, p0, p1)
54 
type r0, r1;  type *p0, *p1;
55 
{reg0 = regx1;  }
56 
 
57 
indreg0reg1_set (r0, r1, x0, x1, p0, p1)
58 
type r0, r1;  type *p0, *p1;
59 
{indreg0 = reg1;  }
60 
 
61 
indreg0indreg1_set (r0, r1, x0, x1, p0, p1)
62 
type r0, r1;  type *p0, *p1;
63 
{indreg0 = indreg1;  }
64 
 
65 
indreg0imm1_set (r0, r1, x0, x1, p0, p1)
66 
type r0, r1;  type *p0, *p1;
67 
{indreg0 = imm1;  }
68 
 
69 
indreg0limm1_set (r0, r1, x0, x1, p0, p1)
70 
type r0, r1;  type *p0, *p1;
71 
{indreg0 = limm1;  }
72 
 
73 
indreg0adr1_set (r0, r1, x0, x1, p0, p1)
74 
type r0, r1;  type *p0, *p1;
75 
{indreg0 = adr1;  }
76 
 
77 
indreg0adrreg1_set (r0, r1, x0, x1, p0, p1)
78 
type r0, r1;  type *p0, *p1;
79 
{indreg0 = adrreg1;  }
80 
 
81 
indreg0adrx1_set (r0, r1, x0, x1, p0, p1)
82 
type r0, r1;  type *p0, *p1;
83 
{indreg0 = adrx1;  }
84 
 
85 
indreg0regx1_set (r0, r1, x0, x1, p0, p1)
86 
type r0, r1;  type *p0, *p1;
87 
{indreg0 = regx1;  }
88 
 
89 
adr0reg1_set (r0, r1, x0, x1, p0, p1)
90 
type r0, r1;  type *p0, *p1;
91 
{adr0 = reg1;  }
92 
 
93 
adr0indreg1_set (r0, r1, x0, x1, p0, p1)
94 
type r0, r1;  type *p0, *p1;
95 
{adr0 = indreg1;  }
96 
 
97 
adr0imm1_set (r0, r1, x0, x1, p0, p1)
98 
type r0, r1;  type *p0, *p1;
99 
{adr0 = imm1;  }
100 
 
101 
adr0limm1_set (r0, r1, x0, x1, p0, p1)
102 
type r0, r1;  type *p0, *p1;
103 
{adr0 = limm1;  }
104 
 
105 
adr0adr1_set (r0, r1, x0, x1, p0, p1)
106 
type r0, r1;  type *p0, *p1;
107 
{adr0 = adr1;  }
108 
 
109 
adr0adrreg1_set (r0, r1, x0, x1, p0, p1)
110 
type r0, r1;  type *p0, *p1;
111 
{adr0 = adrreg1;  }
112 
 
113 
adr0adrx1_set (r0, r1, x0, x1, p0, p1)
114 
type r0, r1;  type *p0, *p1;
115 
{adr0 = adrx1;  }
116 
 
117 
adr0regx1_set (r0, r1, x0, x1, p0, p1)
118 
type r0, r1;  type *p0, *p1;
119 
{adr0 = regx1;  }
120 
 
121 
adrreg0reg1_set (r0, r1, x0, x1, p0, p1)
122 
type r0, r1;  type *p0, *p1;
123 
{adrreg0 = reg1;  }
124 
 
125 
adrreg0indreg1_set (r0, r1, x0, x1, p0, p1)
126 
type r0, r1;  type *p0, *p1;
127 
{adrreg0 = indreg1;  }
128 
 
129 
adrreg0imm1_set (r0, r1, x0, x1, p0, p1)
130 
type r0, r1;  type *p0, *p1;
131 
{adrreg0 = imm1;  }
132 
 
133 
adrreg0limm1_set (r0, r1, x0, x1, p0, p1)
134 
type r0, r1;  type *p0, *p1;
135 
{adrreg0 = limm1;  }
136 
 
137 
adrreg0adr1_set (r0, r1, x0, x1, p0, p1)
138 
type r0, r1;  type *p0, *p1;
139 
{adrreg0 = adr1;  }
140 
 
141 
adrreg0adrreg1_set (r0, r1, x0, x1, p0, p1)
142 
type r0, r1;  type *p0, *p1;
143 
{adrreg0 = adrreg1;  }
144 
 
145 
adrreg0adrx1_set (r0, r1, x0, x1, p0, p1)
146 
type r0, r1;  type *p0, *p1;
147 
{adrreg0 = adrx1;  }
148 
 
149 
adrreg0regx1_set (r0, r1, x0, x1, p0, p1)
150 
type r0, r1;  type *p0, *p1;
151 
{adrreg0 = regx1;  }
152 
 
153 
adrx0reg1_set (r0, r1, x0, x1, p0, p1)
154 
type r0, r1;  type *p0, *p1;
155 
{adrx0 = reg1;  }
156 
 
157 
adrx0indreg1_set (r0, r1, x0, x1, p0, p1)
158 
type r0, r1;  type *p0, *p1;
159 
{adrx0 = indreg1;  }
160 
 
161 
adrx0imm1_set (r0, r1, x0, x1, p0, p1)
162 
type r0, r1;  type *p0, *p1;
163 
{adrx0 = imm1;  }
164 
 
165 
adrx0limm1_set (r0, r1, x0, x1, p0, p1)
166 
type r0, r1;  type *p0, *p1;
167 
{adrx0 = limm1;  }
168 
 
169 
adrx0adr1_set (r0, r1, x0, x1, p0, p1)
170 
type r0, r1;  type *p0, *p1;
171 
{adrx0 = adr1;  }
172 
 
173 
adrx0adrreg1_set (r0, r1, x0, x1, p0, p1)
174 
type r0, r1;  type *p0, *p1;
175 
{adrx0 = adrreg1;  }
176 
 
177 
adrx0adrx1_set (r0, r1, x0, x1, p0, p1)
178 
type r0, r1;  type *p0, *p1;
179 
{adrx0 = adrx1;  }
180 
 
181 
adrx0regx1_set (r0, r1, x0, x1, p0, p1)
182 
type r0, r1;  type *p0, *p1;
183 
{adrx0 = regx1;  }
184 
 
185 
regx0reg1_set (r0, r1, x0, x1, p0, p1)
186 
type r0, r1;  type *p0, *p1;
187 
{regx0 = reg1;  }
188 
 
189 
regx0indreg1_set (r0, r1, x0, x1, p0, p1)
190 
type r0, r1;  type *p0, *p1;
191 
{regx0 = indreg1;  }
192 
 
193 
regx0imm1_set (r0, r1, x0, x1, p0, p1)
194 
type r0, r1;  type *p0, *p1;
195 
{regx0 = imm1;  }
196 
 
197 
regx0limm1_set (r0, r1, x0, x1, p0, p1)
198 
type r0, r1;  type *p0, *p1;
199 
{regx0 = limm1;  }
200 
 
201 
regx0adr1_set (r0, r1, x0, x1, p0, p1)
202 
type r0, r1;  type *p0, *p1;
203 
{regx0 = adr1;  }
204 
 
205 
regx0adrreg1_set (r0, r1, x0, x1, p0, p1)
206 
type r0, r1;  type *p0, *p1;
207 
{regx0 = adrreg1;  }
208 
 
209 
regx0adrx1_set (r0, r1, x0, x1, p0, p1)
210 
type r0, r1;  type *p0, *p1;
211 
{regx0 = adrx1;  }
212 
 
213 
regx0regx1_set (r0, r1, x0, x1, p0, p1)
214 
type r0, r1;  type *p0, *p1;
215 
{regx0 = regx1;  }
216 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.