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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [pr27861-1.c] - Blame information for rev 298

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Line No. Rev Author Line
1 298 jeremybenn
/* PR target/27861 */
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/* The following code used to cause an ICE during RTL expansion, as
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   expand shift was stripping the SUBREG of a rotate shift count, and
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   later producing a VAR_DECL tree whose DECL_RTL's mode didn't match
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   the VAR_DECL's type's mode.  */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef struct sim_state *SIM_DESC;
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typedef enum
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{
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  SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG
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}
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SIM_RC;
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typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__)));
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typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__)));
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typedef unsigned32 unsigned_address;
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typedef unsigned_address address_word;
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static __inline__ unsigned64
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  __attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift)
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{
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  unsigned64 result;
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  result = (((val) >> (shift)) | ((val) << ((64) - (shift))));
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  return result;
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}
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typedef struct _sim_cpu sim_cpu;
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enum
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{
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    TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX,
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};
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typedef struct _trace_data
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{
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  char trace_flags[32];
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}
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TRACE_DATA;
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typedef enum
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{
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    nr_watchpoint_types,
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}
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watchpoint_type;
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typedef struct _sim_watchpoints
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{
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  TRACE_DATA trace_data;
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}
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sim_cpu_base;
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struct _sim_cpu
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{
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  sim_cpu_base base;
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};
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struct sim_state
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{
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  sim_cpu cpu[1];
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};
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typedef address_word instruction_address;
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do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x,
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         unsigned64 y)
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{
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  unsigned64 result;
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  result = ROTR64 (x, y);
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    {
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      if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0
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           && (((&(((&(sd)->cpu[0])))->base.trace_data))->
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               trace_flags)[TRACE_ALU_IDX] != 0))
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        trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result));
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    }
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}
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