OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [spill-1.c] - Blame information for rev 404

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* This caused an ICE during register spilling when targeting thumb.
2
   There are 8 registers available for arithmetic operations (r0-r7)
3
   r7 is the frame pointer, and r0-r3 are used to pass arguments.
4
   Combine was extending the lives of the arguments (in r0-r3) up until the
5
   call to z. This leaves only 3 regs free which isn't enough to preform the
6
   doubleword addition.  */
7
/* { dg-do compile } */
8
/* { dg-options "-O2 -fno-omit-frame-pointer" } */
9
void z(int);
10
int foo(int a, int b, int c, int d, long long *q)
11
{
12
  *q=*q+1;
13
  z (a+b+c+d);
14
}
15
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.