OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [tree-ssa/] [pr38533.c] - Blame information for rev 298

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* PR middle-end/38533 */
2
/* { dg-do compile } */
3
/* { dg-options "-O2 -fdump-tree-reassoc1" } */
4
 
5
#define A asm volatile ("" : "=r" (f) : "0" (0)); e |= f;
6
#define B A A A A A A A A A A A
7
#define C B B B B B B B B B B B
8
 
9
int
10
foo (void)
11
{
12
  int e = 0, f;
13
  C C B B B B B A A A A A A
14
  return e;
15
}
16
 
17
int
18
main (void)
19
{
20
  if (foo ())
21
    __builtin_abort ();
22
  return 0;
23
}
24
 
25
/* Verify that reassoc hasn't increased register pressure too much
26
   by moving all bitwise ors after the last __asm__.  There should
27
   be exactly 2 (first) __asm__ stmts with no intervening stmts,
28
   all others should have some bitwise or in between.  */
29
/* { dg-final { scan-tree-dump-times "__asm__\[^;\n]*;\n *__asm__" 1 "reassoc1"} } */
30
/* { dg-final { cleanup-tree-dump "reassoc1" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.