OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.dg/] [vmx/] [5-07t.c] - Blame information for rev 298

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* { dg-do compile } */
2
#include <altivec.h>
3
typedef vector unsigned char t_u8;
4
typedef vector signed char t_s8;
5
typedef vector bool char t_b8;
6
typedef vector unsigned short t_u16;
7
typedef vector signed short t_s16;
8
typedef vector bool short t_b16;
9
typedef vector unsigned int t_u32;
10
typedef vector signed int t_s32;
11
typedef vector bool int t_b32;
12
typedef vector float t_f32;
13
typedef vector pixel t_p16;
14
 
15
t_u8 u8 = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
16
t_s8 s8 = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
17
t_b8 b8 = {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
18
t_u16 u16 = {1,1,1,1,1,1,1,1};
19
t_s16 s16 = {1,1,1,1,1,1,1,1};
20
t_b16 b16 = {1,1,1,1,1,1,1,1};
21
t_u32 u32 = {1,1,1,1};
22
t_s32 s32 = {1,1,1,1};
23
t_b32 b32 = {1,1,1,1};
24
t_f32 f32 = {1,1,1,1};
25
t_p16 p16 = {1,1,1,1,1,1,1,1};
26
 
27
t_u8 u8_ = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
28
t_s8 s8_ = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
29
t_b8 b8_ = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
30
t_u16 u16_ = {1,2,3,4,5,6,7,8};
31
t_s16 s16_ = {1,2,3,4,5,6,7,8};
32
t_b16 b16_ = {1,2,3,4,5,6,7,8};
33
t_u32 u32_ = {1,2,3,4};
34
t_s32 s32_ = {1,2,3,4};
35
t_b32 b32_ = {1,2,3,4};
36
t_f32 f32_ = {1,2,3,4};
37
t_p16 p16_ = {1,2,3,4,5,6,7,8};

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.