OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vbslQs8.c] - Blame information for rev 378

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* Test the `vbslQs8' ARM Neon intrinsic.  */
2
/* This file was autogenerated by neon-testgen.  */
3
 
4
/* { dg-do assemble } */
5
/* { dg-require-effective-target arm_neon_ok } */
6
/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
7
 
8
#include "arm_neon.h"
9
 
10
void test_vbslQs8 (void)
11
{
12
  int8x16_t out_int8x16_t;
13
  uint8x16_t arg0_uint8x16_t;
14
  int8x16_t arg1_int8x16_t;
15
  int8x16_t arg2_int8x16_t;
16
 
17
  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
18
}
19
 
20
/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
21
/* { dg-final { cleanup-saved-temps } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.