OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vdupQ_lanes8.c] - Blame information for rev 313

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
2
/* This file was autogenerated by neon-testgen.  */
3
 
4
/* { dg-do assemble } */
5
/* { dg-require-effective-target arm_neon_ok } */
6
/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
7
 
8
#include "arm_neon.h"
9
 
10
void test_vdupQ_lanes8 (void)
11
{
12
  int8x16_t out_int8x16_t;
13
  int8x8_t arg0_int8x8_t;
14
 
15
  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
16
}
17
 
18
/* { dg-final { scan-assembler "vdup\.8\[       \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
19
/* { dg-final { cleanup-saved-temps } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.