OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vfp-shift-a2t2.c] - Blame information for rev 326

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* Check that NEON vector shifts support immediate values == size.  /*
2
 
3
/* { dg-do compile } */
4
/* { dg-require-effective-target arm_neon_ok } */
5
/* { dg-options "-save-temps -mfpu=neon -mfloat-abi=softfp" } */
6
 
7
#include <arm_neon.h>
8
 
9
uint16x8_t test_vshll_n_u8 (uint8x8_t a)
10
{
11
    return vshll_n_u8(a, 8);
12
}
13
 
14
uint32x4_t test_vshll_n_u16 (uint16x4_t a)
15
{
16
    return vshll_n_u16(a, 16);
17
}
18
 
19
uint64x2_t test_vshll_n_u32 (uint32x2_t a)
20
{
21
    return vshll_n_u32(a, 32);
22
}
23
 
24
/* { dg-final { scan-assembler "vshll\.u16\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
25
/* { dg-final { scan-assembler "vshll\.u32\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
26
/* { dg-final { scan-assembler "vshll\.u8\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
27
/* { dg-final { cleanup-saved-temps } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.