URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vld3Qf32.c] - Blame information for rev 313

Line No.	Rev	Author	Line
1	313	jeremybenn	/* Test the `vld3Qf32' ARM Neon intrinsic. */
2			`/* This file was autogenerated by neon-testgen. */`
3
4			`/* { dg-do assemble } */`
5			`/* { dg-require-effective-target arm_neon_ok } */`
6			`/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */`
7
8			`#include "arm_neon.h"`
9
10			`void test_vld3Qf32 (void)`
11			`{`
12			`float32x4x3_t out_float32x4x3_t;`
13
14			`out_float32x4x3_t = vld3q_f32 (0);`
15			`}`
16
17			`/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)\|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */`
18			`/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)\|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */`
19			`/* { dg-final { cleanup-saved-temps } } */`