OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [register-variables.c] - Blame information for rev 326

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-O" } */
3
 
4
#include <stdlib.h>
5
 
6
void __attribute__((noinline))
7
bar(int a, int b)
8
{
9
  if (a != 43 || b != 42)
10
    abort();
11
}
12
 
13
int main(void)
14
{
15
    register int r0 asm("r0") = 42;
16
    register int r1 asm("r1") = 43;
17
    asm volatile("": "+r" (r0), "+r" (r1));
18
    bar(r1, r0);
19
    return 0;
20
}
21
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.