OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [thumb-ltu.c] - Blame information for rev 313

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 313 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-mcpu=arm1136jf-s -mthumb -O2" } */
3
 
4
void f(unsigned a, unsigned b, unsigned c, unsigned d)
5
{
6
  if (a <= b || c > d)
7
    foo();
8
  else
9
    bar();
10
}
11
 
12
/* { dg-final { scan-assembler-not "uxtb" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.