OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [frv/] [fr450-builtins-8.c] - Blame information for rev 317

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 317 jeremybenn
/* Test a situation in which an M6 instruction (mdcutssi) and M4 instruction
2
   (mqmulhu) can be issued together.  */
3
/* { dg-options "-mcpu=fr450" } */
4
/* { dg-do run } */
5
extern void abort (void);
6
extern void exit (int);
7
 
8
int
9
main ()
10
{
11
  __MQMULHU (0, 0x0001001101111111ULL, 0x0001000200030004ULL);
12
  __MQMULHU (8, 0x0002002202222222ULL, 0x0004000400040004ULL);
13
  if (__MDCUTSSI (0, 8)
14
      + __MDCUTSSI (2, 8)
15
      + __MDCUTSSI (8, 8)
16
      + __MDCUTSSI (10, 8)
17
      != (0x0000000100000022ULL + 0x0000033300004444ULL
18
          + 0x0000000800000088ULL + 0x0000088800008888ULL))
19
    abort ();
20
 
21
  exit (0);
22
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.