OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [20060512-3.c] - Blame information for rev 328

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target ilp32 } */
3
/* { dg-require-effective-target sse2 } */
4
/* { dg-options "-std=gnu99 -msse2 -mstackrealign -mpreferred-stack-boundary=4" } */
5
 
6
#include "sse2-check.h"
7
 
8
#include <emmintrin.h>
9
 
10
__m128i __attribute__ ((__noinline__))
11
vector_using_function ()
12
{
13
  volatile __m128i vx;  /* We want to force a vector-aligned store into the stack.  */
14
  vx = _mm_xor_si128 (vx, vx);
15
  return vx;
16
}
17
int __attribute__ ((__noinline__))
18
self_aligning_function (int x, int y)
19
{
20
  __m128i ignored = vector_using_function ();
21
  return (x + y);
22
}
23
int g_1 = 20;
24
int g_2 = 22;
25
 
26
static void
27
sse2_test (void)
28
{
29
  int result;
30
  asm ("pushl %esi");           /* Disalign runtime stack.  */
31
  result = self_aligning_function (g_1, g_2);
32
  if (result != 42)
33
    abort ();
34
  asm ("popl %esi");
35
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.