OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [aesdec.c] - Blame information for rev 328

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target aes } */
3
/* { dg-options "-O2 -maes" } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "aes-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST aes_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
#include <wmmintrin.h>
16
#include <string.h>
17
 
18
extern void abort (void);
19
 
20
#define NUM 1024
21
 
22
static __m128i src1[NUM];
23
static __m128i src2[NUM];
24
static __m128i edst[NUM];
25
 
26
static __m128i resdst[NUM];
27
 
28
/* Initialize input/output vectors.  (Currently, there is only one set
29
   of input/output vectors).  */
30
static void
31
init_data (__m128i *s1, __m128i *s2, __m128i *d)
32
{
33
  int i;
34
  for (i = 0; i < NUM; i++)
35
    {
36
      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
37
                              0x73745665, 0x7b5b5465);
38
      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
39
                              0x68617929, 0x48692853);
40
      d[i]  = _mm_setr_epi32 (0xb730392a, 0xb58eb95e,
41
                              0xfaea2787, 0x138ac342);
42
    }
43
}
44
 
45
static void
46
TEST (void)
47
{
48
  int i;
49
 
50
  init_data (src1, src2, edst);
51
 
52
  for (i = 0; i < NUM; i += 16)
53
    {
54
      resdst[i] = _mm_aesdec_si128 (src1[i], src2[i]);
55
      resdst[i + 1] = _mm_aesdec_si128 (src1[i + 1], src2[i + 1]);
56
      resdst[i + 2] = _mm_aesdec_si128 (src1[i + 2], src2[i + 2]);
57
      resdst[i + 3] = _mm_aesdec_si128 (src1[i + 3], src2[i + 3]);
58
      resdst[i + 4] = _mm_aesdec_si128 (src1[i + 4], src2[i + 4]);
59
      resdst[i + 5] = _mm_aesdec_si128 (src1[i + 5], src2[i + 5]);
60
      resdst[i + 6] = _mm_aesdec_si128 (src1[i + 6], src2[i + 6]);
61
      resdst[i + 7] = _mm_aesdec_si128 (src1[i + 7], src2[i + 7]);
62
      resdst[i + 8] = _mm_aesdec_si128 (src1[i + 8], src2[i + 8]);
63
      resdst[i + 9] = _mm_aesdec_si128 (src1[i + 9], src2[i + 9]);
64
      resdst[i + 10] = _mm_aesdec_si128 (src1[i + 10], src2[i + 10]);
65
      resdst[i + 11] = _mm_aesdec_si128 (src1[i + 11], src2[i + 11]);
66
      resdst[i + 12] = _mm_aesdec_si128 (src1[i + 12], src2[i + 12]);
67
      resdst[i + 13] = _mm_aesdec_si128 (src1[i + 13], src2[i + 13]);
68
      resdst[i + 14] = _mm_aesdec_si128 (src1[i + 14], src2[i + 14]);
69
      resdst[i + 15] = _mm_aesdec_si128 (src1[i + 15], src2[i + 15]);
70
    }
71
 
72
  for (i = 0; i < NUM; i++)
73
    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
74
      abort ();
75
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.