OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [avx-vtestpd-256-3.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target avx } */
3
/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
4
/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
5
/* { dg-message " from " "include chain" { target default_packed } 0 } */
6
 
7
#include "avx-check.h"
8
 
9
static void
10
avx_test ()
11
{
12
    int i;
13
    union256d source1, source2;
14
 
15
    double s1[4] = {0, -5463, 86456, 0};
16
    double s2[4] = {0, -1223, 0,     1};
17
    int    d[1];
18
    int    e[1];
19
    int c=1;
20
    int z=1;
21
 
22
    source1.x = _mm256_loadu_pd(s1);
23
    source2.x = _mm256_loadu_pd(s2);
24
    d[0] = _mm256_testnzc_pd(source1.x, source2.x);
25
 
26
    e[0] = 1;
27
    for (i = 0; i < 4; i++) {
28
        union ieee754_double u1, u2;
29
        u1.d = s1[i];
30
        u2.d = s2[i];
31
        if (u1.bits.sign && u2.bits.sign)
32
            z = 0;
33
 
34
        if (!u1.bits.sign && u2.bits.sign)
35
            c = 0;
36
    }
37
    e[0] = (c==0 && z==0) ? 1:0;
38
 
39
   if (checkVi(d, e, 1))
40
     abort ();
41
}
42
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.