OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [crc32-1.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2 -mcrc32" } */
3
/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */
4
/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */
5
/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */
6
 
7
unsigned int
8
crc32b (unsigned int x, unsigned char y)
9
{
10
  return __builtin_ia32_crc32qi (x, y);
11
}
12
 
13
unsigned int
14
crc32w (unsigned int x, unsigned short y)
15
{
16
  return __builtin_ia32_crc32hi (x, y);
17
}
18
 
19
unsigned int
20
crc32d (unsigned int x, unsigned int y)
21
{
22
  return __builtin_ia32_crc32si (x, y);
23
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.