OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [incoming-5.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* PR middle-end/37009 */
2
/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
3
/* { dg-options "-m32 -mincoming-stack-boundary=2 -mpreferred-stack-boundary=2" } */
4
 
5
extern void bar (double *);
6
 
7
double
8
foo(double x)
9
{
10
  double xxx = x + 13.0;
11
 
12
  bar (&xxx);
13
  return xxx;
14
}
15
 
16
/* { dg-final { scan-assembler "andl\[\\t \]*\\$-8,\[\\t \]*%esp" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.