OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr12092-1.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* PR rtl-optimization/12092  */
2
/* Test case reduced by Andrew Pinski <pinskia@physics.uc.edu> */
3
/* { dg-do compile } */
4
/* { dg-require-effective-target ilp32 } */
5
/* { dg-options "-O2 -mtune=i486 -march=pentium4 -fprefetch-loop-arrays" } */
6
 
7
void DecodeAC(int index,int *matrix)
8
{
9
  int *mptr;
10
 
11
  for(mptr=matrix+index;mptr<matrix+64;mptr++) {*mptr = 0;}
12
}
13
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.