OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr21291.c] - Blame information for rev 318

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* The asm has 2 "r" in/out operands, 1 earlyclobber "r" output, 1 "r"
2
   input and 2 fixed "r" clobbers (eax and edx), so there are a total of
3
   6 registers that must not conflict.  Add to that the PIC register,
4
   the frame pointer, and the stack pointer, and we've run out of
5
   registers on 32-bit targets.  */
6
/* { dg-do compile } */
7
/* { dg-options "-O" } */
8
 
9
typedef unsigned long bngdigit;
10
typedef bngdigit *bng;
11
typedef unsigned int bngcarry;
12
typedef unsigned long bngsize;
13
 
14
bngdigit
15
bng_ia32_mult_sub_digit (bng a, bngsize alen, bng b, bngsize blen, bngdigit d)
16
{
17
  bngdigit out, tmp;
18
  bngcarry carry;
19
  bngdigit a11;
20
 
21
  alen -= blen;
22
  out = 0;
23
  asm (""
24
       : "+r" (a), "+r" (b), "+mr" (blen), "+mr" (out), "=&r" (tmp)
25
       : "mr" (d)
26
       : "eax", "edx");
27
  if (alen == 0)
28
    {
29
      a11 = out;
30
      goto t;
31
    }
32
 
33
  a11 = 1;
34
 t:
35
  return a11;
36
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.