OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr22432.c] - Blame information for rev 327

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2 -mmmx" } */
3
/* { dg-final { scan-assembler-not "paddb" } } */
4
 
5
typedef int v2si __attribute__ ((__vector_size__ (8)));
6
typedef short v4hi __attribute__ ((__vector_size__ (8)));
7
typedef char v8qi __attribute__ ((__vector_size__ (8)));
8
 
9
int
10
foo (unsigned int *a, unsigned int *b)
11
{
12
  long long i, j, k;
13
 
14
  i = (long long) __builtin_ia32_vec_init_v2si (*a, 0);
15
  j = (long long) __builtin_ia32_vec_init_v2si (*b, 0);
16
  i = (long long) __builtin_ia32_punpcklbw ((v8qi) i, (v8qi) 0ll);
17
  j = (long long) __builtin_ia32_punpcklbw ((v8qi) j, (v8qi) 0ll);
18
  k = (long long) __builtin_ia32_paddw ((v4hi) i, (v4hi) j);
19
  return __builtin_ia32_vec_ext_v2si ((v2si) k, 0);
20
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.