OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr35160.c] - Blame information for rev 322

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* PR inline-asm/35160 */
2
/* { dg-do run } */
3
/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */
4
/* { dg-options "-O2" } */
5
 
6
extern void abort (void);
7
 
8
void
9
__attribute__((noinline))
10
foo (unsigned int *y)
11
{
12
   unsigned int c0, c1, c2, d0, d1, d2;
13
   d0 = 0; d1 = 0; d2 = 0; c0 = c1 = c2 = 0;
14
 
15
   __asm__ ("movl $7, %k0; movl $8, %k1; movl $9, %k2"
16
            : "+r" (d0), "+r" (d1), "+r" (d2));
17
   __asm__ ("movl %3, %0; movl %4, %1; movl %5, %2"
18
            : "+r" (c0), "+r" (c1), "+r" (c2), "+r" (d0), "+r" (d1), "+r" (d2));
19
   y[0] = c0;
20
   y[1] = c1;
21
   y[2] = c2;
22
}
23
 
24
int
25
main (void)
26
{
27
  unsigned int y[3];
28
  foo (y);
29
  if (y[0] != 7 || y[1] != 8 || y[2] != 9)
30
    abort ();
31
  return 0;
32
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.